JP2000269351A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein a self-matching contact hole is stably opened with no deteriorated transistor characteristics. SOLUTION: In an active region of a semiconductor substrate, a conductive layer 32 and offset insulating film 23a are formed, while a side wall insulating film 24a on its side wall part, with an etching stopper film 25 formed on the entire surface. With the side wall insulating film and etching stopper film as masks, a conductive impurity D2 is introduced by allowing it to transmit the etching stopper film on the upper layer of the substrate, to form a source/drain diffusion layer 12. Then, an interlayer insulating film is formed at the upper layer of the etching stopper film, and a contact hole for exposing the etching stopper film is opened by such etching as the interlayer insulating film is selectively removed from the etching stopper film, before the etching stopper film at the bottom of the contact hole is removed. Then, an upper wiring such as a plug is formed in the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having fine contact junctions.

[0002]

2. Description of the Related Art As seen in recent VLSIs,
With the progress of miniaturization, high integration, and high performance of semiconductor devices, the technical elements of dry etching of an interlayer insulating layer made of silicon oxide (SiO ₂ ) have become more severe. For example, MOS (Metal-Oxide-
Semiconductor) Gate electrode and source of transistor
The distance from the contact hole to the drain diffusion layer is becoming shorter. For this reason, there arises a problem that the gate electrode and the contact to the source / drain diffusion layer are short-circuited due to misalignment in the lithography process for forming the contact hole.

In order to avoid the above problem, the upper part and the side wall of the gate electrode are covered with a material different from the interlayer insulating film such as silicon nitride to prevent the contact from coming into contact with or close to the gate electrode, and to align the contact hole. Self-aligned contact (hereinafter abbreviated as SAC) technology has been developed and proposed, which can eliminate the need for a design margin on a mask for SAC, and active research on SAC has been made to date.

Further, similarly to the above-described SAC, the contact is arranged on the element isolation region due to misalignment between the contact hole and the source / drain diffusion layer, and the element isolation insulating film is etched when the contact hole is formed. There's a problem. This will be described with reference to the drawings. FIG. 14A is a cross-sectional view of the semiconductor device before a step of forming a contact hole. STI (Shallow) embedded in the isolation trench T of the silicon semiconductor substrate 10
A gate insulating film 22 made of silicon oxide is formed on an active region separated by a trench isolation (element isolation insulating film) 21.
Is formed thereon, and a gate electrode 32 having a polycide structure comprising a lower gate electrode 30a made of polysilicon and an upper gate electrode 31a made of tungsten silicide is formed thereon. The side wall of the gate electrode 32 is covered with, for example, silicon nitride, and is made of LDD (Lightly
Doped Drain) Side wall insulating film 2 to be spacer
In the semiconductor substrate 10 on both sides of the gate electrode 32, source / drain diffusion layers having an LDD structure including a low concentration diffusion layer 11 and a high concentration diffusion layer 12 are formed. Is configured.

[0005] are interlayer insulating film 26 made of the entire surface, for example, silicon oxide by covering the transistor is formed, and thereon, a resist film R _CH an opening pattern has been transferred the contact hole is formed. Here, due to misalignment in the photolithography process or the like, the opening of the contact hole opening pattern is STI.
It is assumed that it covers the element isolation insulating film 21.

From the above structure, by performing etching such as RIE (reactive ion etching) using the resist film _RCH as a mask, a contact hole CH is opened in the interlayer insulating film 26 as shown in FIG. But
Since the opening of the opening pattern of the contact hole CH covers the STI element isolation insulating film 21 as described above, even the element isolation insulating film portion X in the contact hole CH is etched, and When the surface of the silicon semiconductor substrate 10 is exposed and a buried electrode or the like is formed in the contact hole CH, a problem occurs that a junction leak current increases.

In order to prevent the element isolation insulating film in the contact hole from being etched, the source / drain diffusion layer and the element isolation insulating film are covered with an etching stopper film made of, for example, silicon nitride. Methods of protection have been developed. FIG. 15 (a)
FIG. 4 is a cross-sectional view of the semiconductor device before a step of forming a contact hole. FIG.
The semiconductor device shown in FIG. 2A is different from the semiconductor device shown in FIG. 1A in that an etching stopper film 25 of, for example, silicon nitride is formed on the entire surface to cover the transistor, and an interlayer insulating film of silicon oxide is formed thereon. I have.

In the case where a contact hole is opened in the above structure, RIE is performed using the resist film _RCH as a mask.
Etching such as (reactive ion etching) is performed on the etching stopper film 25 so as to slow down the etching, and the etching is stopped once on the etching stopper film 25 as shown in FIG.

Next, as shown in FIG. 15C, the etching condition is changed to selectively remove the silicon nitride exposed in the contact hole CH, thereby etching the contact hole CH. The stopper film 25 is removed to expose the source / drain diffusion layers. In the subsequent steps, a desired semiconductor device is formed by forming a buried electrode or the like in the contact hole CH.

According to the above-described method for manufacturing a semiconductor device, even the element isolation insulating film portion in the contact hole is prevented from being etched, and the problem that the junction leak current increases can be avoided. In recent years, in order to further improve the degree of integration, the layout has been drastically reduced, and accordingly, a contact to the diffusion layer with respect to the gate electrode has been formed in a self-aligned manner, It is necessary to achieve both the prevention of etching of the element isolation insulating film at the time of contact formation.

A description will be given of a method of manufacturing a semiconductor device in which a contact with the diffusion layer with respect to the gate electrode is formed in a self-aligned manner, and a device isolation insulating film is prevented from being etched when the contact is formed. First, FIG.
As shown in (a), for example, CVD (Chemical Vapor D)
Silicon nitride is deposited on the silicon semiconductor substrate 10 by an eposition method, and the active region is, for example, a DRAM.
A resist film (not shown) is formed in a pattern that opens the element isolation region except for the region 1 serving as a (memory) portion and the region 2 serving as a logic portion, and is nitrided by etching such as RIE (reactive ion etching). The silicon is removed to form a mask layer 20 for forming an element isolation groove. Here, the region 1 has a gate line width of 0.13 μm so that the interval between the gate electrodes of the plurality of transistors is 0.18 μm in the subsequent steps, while the region 2 has a gate line width of 0.14 μm. Is an area in which is formed.

Next, as shown in FIG. 16B, etching such as RIE is performed using the mask layer 20 as a mask.
An isolation trench T is formed in the semiconductor substrate 10.

Next, as shown in FIG. 16C, after a not-shown trench inner wall protective film is formed on the inner wall of the isolation trench T by, for example, a thermal oxidation method, for example, a high density plasma CV is formed.
After silicon oxide is deposited on the entire surface by the method D while filling the trench-shaped isolation trench T, the CMP (Chem.
The device isolation insulating film 21 is formed by polishing the upper surface of the silicon oxide film by using the mask layer 20 as a stopper by an ical mechanical polishing method.

Next, as shown in FIG. 17D, the mask layer 20 is removed by wet etching using, for example, hot phosphoric acid. At this time, the element isolation insulating film 21 has a shape protruding from the surface of the semiconductor substrate 10 by the thickness of the mask layer 20 after the above-described CMP process.

Next, as shown in FIG. 17E, after a well is formed by ion implantation, a silicon oxide layer is formed to a thickness of several nm by, for example, a thermal oxidation method to form a gate insulating film 22. Next, polysilicon is deposited in a thickness of 70 nm on the gate insulating film 22 by, for example, a CVD method to form a lower gate electrode layer 30. Next, tungsten nitride and tungsten are stacked to a thickness of 5 nm and 60 nm, respectively, by, for example, a CVD method to form an upper gate electrode layer 31. Next, silicon nitride is deposited to a thickness of 100 nm by, for example, a CVD method to form an offset insulating film 23.

Next, as shown in FIG. 17 (f), a resist film R is formed on the gate electrode pattern by a photolithography process, and RIE is performed using the resist film R as a mask.
The upper gate electrode layer 31 and the lower gate electrode layer 30 are sequentially patterned to form a lower gate electrode 30a of polysilicon and an upper gate electrode 3 which is a laminate of tungsten nitride and tungsten.
1a, and an offset insulating film 23 of silicon nitride.
The gate electrode 32 with a is formed. Here, as described above, the gate electrode 32 has a distance b ₁ between the gate electrodes of a plurality of transistors in the region 1 of 0.18 μm, while the distance b ₂ between the gate electrodes in the region ₂ is 0. Gate electrodes having a gate line width a of 0.13 μm are formed so as to have a thickness of 24 μm. At this time, the thin gate insulating film 22 is also processed into a gate electrode pattern.

Next, as shown in FIG. 18 (g), using the gate electrode 32 as a mask, a conductive impurity D1 such as phosphorus or boron is ion-implanted to form an active region of the semiconductor substrate 10 on both sides of the gate electrode 32. A low concentration diffusion layer 11 is formed therein.

Next, as shown in FIG. 18 (h), the gate electrode 32 is coated by, for example, a CVD method, and silicon nitride is deposited to a thickness of 70 nm on the entire surface to form a layer 24 for a sidewall insulating film. .

Next, as shown in FIG. 18I, etch back is performed by, for example, RIE or the like, and the other portions are removed while leaving the sidewall insulating film layer 24 on both sides of the gate electrode 32. A sidewall insulating film 24a having a thickness of about 70 nm which is almost the same as the thickness at the time of deposition and serving as an LDD spacer is formed. Accordingly, at this time, the interval between the side wall insulating films 24a between the gate electrodes 32 in the region 1 is 0.04 μm, and in the region 2, it is 0.10 μm.

Next, as shown in FIG. 19 (j), the conductive impurity D2 is formed using the sidewall insulating film 24a as a mask.
To form a high-concentration diffusion layer 12 connected to the low-concentration diffusion layer 11 in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. As a result, a source / drain diffusion layer having an LDD structure is formed.

Next, as shown in FIG. 19 (k), the offset insulating film 23a, the sidewall insulating film 24a, the upper layer of the high concentration diffusion layer 12 and the upper layer of the element isolation insulating film 21 are formed by, for example, the CVD method. 2 silicon nitride over the entire surface
An etching stopper film 25 is formed by depositing a film having a thickness of 0 nm. Here, in the region 1, the space between the sidewall insulating films 24a between the gate electrodes 32 is filled with the etching stopper film 25.

Next, as shown in FIG. 19 (l), an interlayer insulating film 26 is formed by depositing silicon oxide such as BPSG by, for example, a CVD method and flattening by reflow, etch-back, or a CMP method. .

Next, as shown in FIG. 20 (m), a resist film (not shown) of a contact hole opening pattern is formed on the interlayer insulating film 26 by a photolithography step, and is subjected to RIE or plasma etching. In the region 1, the first etching stopper film 25 is etched under such conditions that the etching is delayed.
The contact hole CH1 is opened in the region 2 and the second contact hole CH2 is opened. The etching is stopped once at the etching stopper film 25.

Next, as shown in FIG. 20 (n), the etching conditions are changed so that the silicon nitride exposed in the contact holes CH1 and CH2 is selectively removed by etching. Is removed to expose the source / drain diffusion layers. As described above, the etching stopper film 25 covers the source / drain diffusion layer and the upper layer of the element isolation insulating film. The etching is stopped once, and the source / drain diffusion layer region is opened again. Etching of the isolation insulating film can be prevented. In addition, since the top and side walls of the gate electrode are covered with a material different from the interlayer insulating film such as silicon nitride, the contact is opened in a self-aligned manner with respect to the diffusion layer, and even if the opening pattern is misaligned. It is possible to prevent the contact from contacting or approaching the gate electrode.

In the subsequent steps, for example, the contact hole is filled with tungsten to form a plug connected to the source / drain diffusion layer, and an upper layer wiring such as aluminum is formed thereon to form a desired semiconductor device. Leads to.

[0026]

However, in the above-described method for manufacturing a semiconductor device, the etching stopper film in the contact hole CH is formed by etching under such conditions that the silicon nitride exposed in the contact hole is selectively removed. In the step of removing the part, in the region 2, a part 2 of the sidewall-shaped etching stopper film is formed.
A contact hole reaching the high-concentration diffusion layer 12 is formed and the contact hole reaching the high-concentration diffusion layer 12 is opened in a region other than between the gate electrodes 32 in the region 1. Since the portion between the side wall insulating films 24a between the gate electrodes 32 in the region 1 is buried in the etching stopper film 25, as shown in FIG. The film 25c is left, resulting in an opening failure, and a contact failure of the contact occurs.

In order to avoid the above problem, when the thickness of the sidewall insulating film serving as the LDD spacer is reduced and the space between the sidewall insulating films between the gate electrodes is widened,
There is no problem with the opening of the contact hole, but in this case, the width of the LDD spacer is reduced, that is,
Another problem occurs in that the LDD width is reduced and the short channel effect of the transistor is increased. In particular, in a salicide process in which a silicide layer is formed in a self-aligned manner with the source / drain diffusion layers, the silicide layer becomes too close to the channel formation region of the transistor, and the diffusion of the refractory metal and the stress caused by the silicide layer cause In this case, the short channel effect increases, and the leakage current in the diffusion layer around the gate electrode increases.

The present invention has been made in view of the above circumstances, and therefore, the present invention stably opens a self-aligned contact hole without deteriorating transistor characteristics such as an increase in the short channel effect of the transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be used.

[0029]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a conductive layer in an active region of a semiconductor substrate, and forming an offset insulating film on the conductive layer. Forming a sidewall insulating film on sidewalls of the offset insulating film and the conductive layer; and covering the offset insulating film, the sidewall insulating film and the semiconductor substrate with an etching stopper film. Forming, using the sidewall insulating film and the etching stopper film as a mask, introducing a conductive impurity while transmitting the etching stopper film in an upper layer portion of the semiconductor substrate; Forming a first impurity-containing region containing a conductive impurity, and forming a first impurity-containing region entirely on the etching stopper film. Forming an edge film and exposing the etching stopper film in the contact hole opening region by etching with a selectivity to the etching stopper film to remove the insulating film in the contact hole opening region. Removing the etching stopper film exposed in the contact hole opening region and opening a contact hole exposing the first impurity-containing region.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the offset insulating film,
Prior to the step of forming the sidewall insulating film, a conductive impurity is introduced using the offset insulating film as a mask, and a second concentration of the conductive impurity is lower than the first concentration in the semiconductor substrate. And forming the first impurity-containing region. The step of forming the first impurity-containing region includes connecting to the second impurity-containing region.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, before the step of forming the conductive layer, the method further includes a step of forming an element isolation insulating film in an element isolation region of the semiconductor substrate, wherein the step of forming the etching stopper film The insulating film is formed by further coating. More preferably, in the step of opening the contact hole, the contact hole is formed such that a part of the element isolation region is included in the contact hole opening region.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, after the step of opening the contact hole,
Forming a buried electrode connected to the high-concentration impurity-containing region by filling the contact hole with a conductor.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the etching stopper film is formed of a silicon nitride-containing layer, and the insulating film is formed of a silicon oxide-containing layer. More preferably, the offset insulating film and the sidewall insulating film are formed of a silicon nitride-containing layer.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the step of forming the element isolation insulating film includes a step of forming an element isolation groove in the semiconductor substrate, and a step of filling the element isolation groove with an insulator. More preferably, the element isolation insulating film is formed of a silicon oxide containing layer.

The method of manufacturing a semiconductor device according to the present invention described above includes:
Forming an element isolation insulating film in an element isolation region of a semiconductor substrate,
A conductive layer is formed in an active region of a semiconductor substrate, an offset insulating film is formed above the conductive layer, and a conductive impurity is introduced using the offset insulating film as a mask to introduce the conductive impurity into the semiconductor substrate at a second concentration. A second impurity-containing region is formed, and a sidewall insulating film is formed on sidewall portions of the offset insulating film and the conductive layer. Next, the offset insulating film,
An etching stopper film is formed by covering the sidewall insulating film, the semiconductor substrate (the second impurity-containing region), and the element isolation insulating film. Next, using the sidewall insulating film and the etching stopper film as a mask, the semiconductor substrate (second
The conductive impurity is introduced while passing through the etching stopper film in the upper layer portion of the impurity-containing region, and the conductive impurity is contained in the semiconductor substrate at a first concentration higher than the second concentration. Forming a first impurity-containing region connected to the impurity-containing region; Next, an insulating film is formed over the entire surface of the etching stopper film, and an etching stopper is formed in the contact hole opening region by etching with a selectivity to the etching stopper film to remove the insulating film in the contact hole opening region. The film is exposed, the etching stopper film exposed in the contact hole opening region is removed, and a contact hole exposing the first impurity-containing region is opened.

According to the method of manufacturing a semiconductor device of the present invention described above, the semiconductor substrate (the second impurity-containing region) is formed by using the sidewall insulating film and the etching stopper film as a mask.
The first impurity-containing region is formed by introducing a conductive impurity while transmitting the etching stopper film in the upper layer portion. Therefore, since the sidewall insulating film and the etching stopper film have a function as an LDD spacer,
Even when the thickness of the sidewall insulating film is reduced, the sidewall insulating film can be formed without deteriorating transistor characteristics such as an increase in a short channel effect of the transistor. Further, the thickness of the sidewall insulating film can be reduced. Therefore, the gap between the sidewall insulating films between the gate electrodes is prevented from being buried in the etching stopper film. A consistent contact hole can be stably opened.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a conductive layer on a semiconductor substrate in a first region and a second region of the semiconductor substrate; Forming an offset insulating film on the conductive layer in the region and the second region, and forming a sidewall insulating film on a side wall of the offset insulating film and the conductive layer in the first region and the second region Forming an etching stopper film by covering the offset insulating film, the sidewall insulating film, and the semiconductor substrate in the first region and the second region; and forming the etching stopper film in the first region. Using the insulating film and the etching stopper film as a mask, the conductive film is formed while passing through the etching stopper film in the upper layer portion of the semiconductor substrate. A step of introducing a pure substance to form a first impurity-containing region containing a first concentration of a conductive impurity in the semiconductor substrate; and, in the second region, at least a side wall portion of the sidewall insulating film. Removing the etching stopper film at least in a portion covering the semiconductor substrate while leaving the etching stopper film; and, in the second region, the sidewall insulating film and the etching stopper in a sidewall portion of the sidewall insulating film. Introducing a conductive impurity using the film as a mask to form a second impurity-containing region containing a second concentration of the conductive impurity in the semiconductor substrate; and forming an entire surface in the first region and the second region. Forming an insulating film; and forming an insulating film on the first region and the second region. In the first region, the etching stopper film is exposed in the contact hole opening region by etching for removing the insulating film in the contact hole opening region with a selectivity, and the contact region is formed in the second region. Forming a contact hole exposing the high-concentration impurity-containing region in the hole opening region; and removing the etching stopper film exposed in the contact-hole opening region in the first region to remove the high-concentration impurity-containing region. Opening a contact hole for exposing the contact hole.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, in the first region and the second region, after the step of forming the offset insulating film, and before the step of forming the sidewall insulating film, conductive impurities are introduced using the offset insulating film as a mask. A third concentration lower than the first concentration and the second concentration in the semiconductor substrate;
Forming a third impurity-containing region containing a conductive impurity having a concentration of at least one of the following. In the step of forming the first impurity-containing region in the first region, the third impurity-containing region is connected to the third impurity-containing region. In the step of forming the second impurity-containing region in the second region, the second impurity-containing region is formed so as to be connected to the third impurity-containing region.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, after the step of forming the second impurity-containing region in the second region, and before the step of forming an insulating film in the first region and the second region, the second impurity is formed in the second region. Forming a metal silicide layer on a surface portion of the content region; and exposing the second impurity content region in the contact hole opening region in the second region. The metal silicide layer formed on the surface layer is exposed.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, in the first region and the second region, before the step of forming the conductive layer, an element isolation insulating film is provided on at least an element isolation region of the semiconductor substrate which is separated into the first region and the second region. The step of forming the etching stopper film further includes forming the element isolation insulating film. More preferably, in the step of opening the contact hole in the first region, the contact hole is formed such that a part of the element isolation region is included in the contact hole opening region.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, after the step of opening the contact hole in the first region, the method further includes the step of filling the contact hole with a conductor to form a buried electrode connected to the first impurity-containing region. Also, preferably,
After the step of opening the contact hole in the second region, the method further includes the step of filling the contact hole with a conductor to form a buried electrode connected to the second impurity-containing region.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the etching stopper film is formed of a silicon nitride-containing layer in the first region and the second region, and the insulating film is formed of a silicon oxide-containing layer in the first region and the second region. More preferably, in the first region and the second region, the offset insulating film and the sidewall insulating film are formed of a silicon nitride-containing layer.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the step of forming the element isolation insulating film includes a step of forming an element isolation groove in the semiconductor substrate, and a step of filling the element isolation groove with an insulator. More preferably, the element isolation insulating film is formed of a silicon oxide containing layer.

The method of manufacturing a semiconductor device according to the present invention described above
Forming an element isolation insulating film in an element isolation region of a semiconductor substrate,
In the first region and the second region separated by the element isolation insulating film, a conductive layer is formed on the semiconductor substrate, an offset insulating film is formed on the conductive layer, and conductive impurities are introduced using the offset insulating film as a mask. Forming a third impurity-containing region containing a conductive impurity at a third concentration in the semiconductor substrate;
A sidewall insulating film is formed on a side wall of the offset insulating film and the conductive layer. Next, an etching stopper film is formed in the first region and the second region by covering the offset insulating film, the sidewall insulating film, the semiconductor substrate (the third impurity-containing region), and the element isolation insulating film. Next, in the first region, using the sidewall insulating film and the etching stopper film as a mask, conductive impurities are introduced while transmitting the etching stopper film in the upper layer portion of the semiconductor substrate (the third impurity-containing region). A first impurity-containing region connected to the third impurity-containing region by forming a conductive impurity at a first concentration higher than the third concentration. Next, in the second region, at least a portion covering the semiconductor substrate (the third impurity-containing region) is removed while leaving the etching stopper film on at least the side wall of the sidewall insulating film,
Conductive impurities are introduced using the sidewall insulating film and the etching stopper film on the side wall of the sidewall insulating film as a mask, and the conductive impurity is contained in the semiconductor substrate at a second concentration higher than the third concentration. Then, a second impurity-containing region connected to the third impurity-containing region is formed. Next, an insulating film is formed on the entire surface of the first region and the second region, and the etching is performed to remove the insulating film in the contact hole opening region with a selectivity with respect to the etching stopper film. An etching stopper film is exposed in the contact hole opening region, and a contact hole for exposing the second impurity-containing region is opened in the contact hole opening region in the second region. Next, in the first region, a contact hole exposing the first impurity-containing region is formed by removing the etching stopper film exposed in the contact hole opening region.

According to the method of manufacturing a semiconductor device of the present invention, the etching stopper film in the upper portion of the semiconductor substrate (the third impurity-containing region) is formed in the first region using the sidewall insulating film and the etching stopper film as a mask. The first impurity-containing region is formed by introducing a conductive impurity while transmitting light. On the other hand, in the second region, the portion of the etching stopper film covering the semiconductor substrate (the third impurity-containing region) is removed while leaving the etching stopper film on the side wall portion of the sidewall insulating film. A second impurity-containing region is formed by introducing conductive impurities using the etching stopper film on the side wall of the sidewall insulating film as a mask. Therefore, in the first region, since the sidewall insulating film and the etching stopper film have a function as an LDD spacer, even if the thickness of the sidewall insulating film is reduced, the transistor characteristics such as an increase in the short channel effect of the transistor are obtained. And the thickness of the sidewall insulating film can be reduced, so that the gap between the sidewall insulating films between the gate electrodes is buried in the etching stopper film. Thus, it is possible to stably open the self-aligned contact hole by suppressing the occurrence of an opening defect in the step of removing the etching stopper film in the contact hole. On the other hand, in the second region, the side wall insulating film and the etching stopper film on the side wall of the side wall insulating film function as LDD spacers.
The transistor can be formed without deteriorating transistor characteristics such as an increase in a short channel effect of the transistor. Further, since the etching stopper film covering the semiconductor substrate (the third impurity-containing region) is removed, a silicide layer can be formed in a self-aligned manner on the source / drain diffusion layers. The film and the etching stopper film on the side wall of the sidewall insulating film prevent the silicide layer from being too close to the channel formation region of the transistor, suppress the short channel effect, and reduce the leakage current in the diffusion layer around the gate electrode. It is possible to form while suppressing the increase.

[0046]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment The semiconductor device according to the first embodiment is a semiconductor device having a contact connection by SAC, and FIG. 1 is a sectional view thereof. In the silicon semiconductor substrate 10, for example, an element isolation groove T is formed in an element isolation region which is divided into an active region such as a DRAM (memory) region 1 and a logic region 2.
Is formed, and an element isolation insulating film 21 made of, for example, silicon oxide is embedded therein.

In the region 1, the semiconductor substrate 10
In the upper layer, a lower gate electrode 30a of polysilicon and an upper gate electrode 31a, which is a laminate of tungsten nitride and tungsten, with a gate insulating film 22 interposed therebetween, and a gate electrode 32 with an offset insulating film 23a of silicon nitride is formed. Is formed. In the semiconductor substrate 10 on both sides of the gate electrode 32, a low concentration diffusion layer 11 containing a conductive impurity at a low concentration and a high concentration diffusion layer 12 containing a high concentration are formed.
A source / drain diffusion layer having a Doped Drain structure is formed. A sidewall insulating film 24a made of, for example, silicon nitride is formed on both sides of the gate electrode 32, and an etching stopper film 25 of silicon nitride is formed over the region 1 over the sidewall insulating film 24a. The LDD width of the source / drain diffusion layers is determined by the thicknesses of the sidewall insulating film 24a and the etching stopper film 25.

BPS is applied on the etching stopper film 25.
A silicon oxide-based interlayer insulating film 26 such as G (silicon oxide containing boron and phosphorus) is formed. In the interlayer insulating film 26 and the etching stopper film 25, a first contact hole CH1 reaching the high concentration diffusion layer 12 is opened. In the first contact hole CH1 opened in the region between the gate electrodes, a part 2 of the etching stopper film is formed on the side of the sidewall insulating film 24a.
A first contact hole CH1 reaching the high concentration diffusion layer 12 while leaving 5b is formed. An adhesion layer 33, which is a laminate of, for example, titanium and titanium nitride, is formed to cover the inner wall of the first contact hole CH1, and a plug 34a made of, for example, tungsten is formed in an upper layer so as to bury the inside of the first contact hole. Further, an upper layer wiring 35 made of, for example, aluminum is formed on the upper layer.

Next, a method for manufacturing the above semiconductor device will be described. First, as shown in FIG.
Silicon nitride is deposited on the silicon semiconductor substrate 10 by a VD (Chemical Vapor Deposition) method, and a pattern is formed as an active region, for example, opening an element isolation region except a region 1 serving as a DRAM (memory) portion and a region 2 serving as a logic portion. A resist film (not shown) is formed, silicon nitride in the element isolation region is removed by etching such as RIE (reactive ion etching), and a mask layer 20 for forming an element isolation groove is formed. Here, the region 1 is such that the distance between the gate electrodes of the plurality of transistors is 0.18 μm in the subsequent steps, while the region 2 is 0.24 μm.
m is a region in which a gate electrode having a gate line width of 0.13 μm is formed.

Next, as shown in FIG. 2B, etching such as RIE is performed using the mask layer 20 as a mask to form a trench T for element isolation in the semiconductor substrate 10.

Next, as shown in FIG. 2C, a not-shown trench inner wall protective film is formed on the inner wall of the isolation trench T by, for example, thermal oxidation, and then, for example, by high-density plasma CVD.
After depositing silicon oxide over the entire surface while filling the trench-shaped isolation trench T by the CMP method, a CMP (Chemic
Then, the upper surface of the silicon oxide film is polished using the mask layer 20 as a stopper to form an element isolation insulating film 21 by an al mechanical polishing method.

Next, as shown in FIG. 3D, the mask layer 2 is formed by wet etching using, for example, hot phosphoric acid.
Remove 0. At this time, the element isolation insulating film 21 has a thickness corresponding to the film thickness of the mask layer 20 after the above-mentioned CMP process.
It has a shape protruding from the zero surface.

Next, as shown in FIG. 3E, after a well is formed by ion implantation or a channel impurity is introduced, a silicon oxide layer is formed several n times by, for example, a thermal oxidation method.
m (for example, 3 nm), and the gate insulating film 22 is formed.
And Next, the gate insulating film 22 is formed by, for example, a CVD method.
Polysilicon is deposited in a thickness of 70 nm on the upper layer to form a lower gate electrode layer 30. Next, for example, CVD
Tungsten nitride and tungsten each by 5
The upper gate electrode layer 31 is formed by stacking layers having a thickness of 60 nm. Next, silicon nitride is deposited to a thickness of 100 nm by, for example, a CVD method to form an offset insulating film 23.

Next, as shown in FIG. 3F, a resist film R is formed on the pattern of the gate electrode by a photolithography process, and etching such as RIE is performed using the resist film R as a mask to form an upper gate electrode layer. 31 and the lower gate electrode layer 30 are sequentially patterned to form a polysilicon lower gate electrode 30a and an upper gate electrode 31 which is a laminate of tungsten nitride and tungsten.
a silicon nitride offset insulating film 23a
The gate electrode 32 is formed. Here, as described above, the gate electrode 32 has a distance b ₁ between the gate electrodes of a plurality of transistors in the region 1 of 0.18 μm, while the distance b ₂ between the gate electrodes in the region ₂ is 0. Gate electrodes having a gate line width a of 0.13 μm are formed so as to have a thickness of 24 μm. At this time, the thin gate insulating film 22 is also processed into a gate electrode pattern.

Next, as shown in FIG. 4G, using the gate electrode 32 as a mask, a conductive impurity D1 such as phosphorus or boron is ion-implanted to activate the semiconductor substrate 10 on both sides of the gate electrode 32. A low concentration diffusion layer 11 is formed in the region.

Next, as shown in FIG.
The gate electrode 32 is covered by the VD method, and silicon nitride is deposited to a thickness of 50 nm on the entire surface to form the side wall insulating film layer 24.

Next, as shown in FIG.
Etchback is performed by etching such as IE to remove the remaining portions of the sidewall insulating film layer 24 on both sides of the gate electrode 32, and to remove the sidewall insulating film having a thickness of about 50 nm which is almost the same as the thickness at the time of deposition. Membrane 24a
To form Therefore, at this time, the interval between the side wall insulating films 24a between the gate electrodes 32 in the region 1 is 0.08 μm, and in the region 2, it is 0.14 μm.

Next, as shown in FIG.
By VD method, silicon nitride is formed on the entire surface including the offset insulating film 23a, the sidewall insulating film 24a, the upper layer of the low-concentration diffusion layer 11 and the upper layer of the element isolation insulating film 21.
Then, an etching stopper film 25 is formed. Here, in the region 1, the space between the sidewall insulating films 24a between the gate electrodes 32 is not completely buried by the etching stopper film 25, and has a gap of, for example, 0.04 μm.

Next, as shown in FIG. 5 (k), a resist film R2 for protecting the region 2 and opening the region 1 is formed. In the region 1, the sidewall insulating film 24a and the etching stopper film 25 are used as a mask. The conductive impurity D2 is ion-implanted so as to have a higher concentration than the low concentration diffusion layer 11, and the high concentration diffusion layer 12 connected to the low concentration diffusion layer 11 is formed in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. To form As a result, a source / drain diffusion layer having an LDD structure is formed.

Next, as shown in FIG. 5 (l), a resist film R3 that protects the region 1 and opens the region 2 is formed, and the region 2 is etched back by etching such as RIE to form a side wall. Except for a part 25a of the sidewall-shaped etching stopper film on both sides of the insulating film 24a, the other portions are removed.

Next, as shown in FIG. 6 (m), in the region 2, the low concentration diffusion layer 11 is formed by using the side wall insulating film 24a and a part 25a of the etching stopper film as a mask.
The conductive impurity D3 is ion-implanted so as to have a higher concentration than the semiconductor substrate 10 on both sides of the gate electrode 32.
The high concentration diffusion layer 12 connected to the low concentration diffusion layer 11 is formed in the active region. As a result, even in the region 2, the LD
A source / drain diffusion layer having a D structure is formed. next,
For example, a lamp annealing process at 1000 ° C. for 10 seconds is performed in a nitrogen atmosphere to activate and diffuse the conductive impurities in the low concentration diffusion layer 11 and the high concentration diffusion layer 12 in the region 1 and the region 2.

Next, as shown in FIG. 6 (n), after removing the resist film R3, a metal such as cobalt is deposited to a thickness of 10 nm on the entire surface at a substrate temperature of 450 ° C., for example.
By performing a lamp annealing process at 550 ° C. for 30 seconds, a metal such as cobalt reacts with silicon on the substrate to form a silicide, and unreacted metal such as cobalt is removed with sulfuric acid and hydrogen peroxide. A metal silicide layer 13 such as a cobalt silicide layer is formed in a self-aligned manner.

Next, as shown in FIG.
1200n silicon oxide such as BPSG by VD method
m, and planarized by etch-back or CMP, etc., to form an interlayer insulating film 2 having a thickness of 700 nm.
6 is formed. In addition, planarization can be performed by reflow or the like.

Next, as shown in FIG. 7 (p), a resist film (not shown) of an opening pattern of the contact hole is patterned on the interlayer insulating film 26 by a photolithography process, and RIE or plasma etching is performed. Etching equivalent to a thickness of 900 nm of silicon oxide is performed under conditions such that the etching is slowed by the etching stopper film 25 (for example, conditions for removing silicon oxide at an etching rate 20 times that of silicon nitride), A first contact hole CH1 exposing the etching stopper film 25 in the region 1 and a second contact hole CH2 exposing the metal silicide layer 13 in the region 2 are opened. Here, as the etching conditions, for example, (RF power: 2 kW, gas flow rate: Ar / O ₂ / C ₄
F ₈ = 200/10 / 20sccm, pressure: 5Pa).

Next, as shown in FIG. 7 (q), the etching conditions are changed, for example, under conditions such that silicon nitride is removed at an etching rate 7 times that of silicon oxide.
By etching corresponding to a thickness of 30 nm of silicon nitride, the silicon nitride (etching stopper film 25) exposed in the first contact hole CH1 is selectively removed, and the high concentration diffusion layer 12 is exposed. Here, the etching conditions are, for example, (RF power: 500 W, gas flow rate: Ar / O ₂ / CHF ₃ = 100/10/20 sccm, pressure: 5 Pa). As described above, the etching stopper film 25 covers the source / drain diffusion layer and the upper layer of the element isolation insulating film,
Since the etching is stopped once and the source / drain diffusion layer region is opened again, the element isolation insulating film can be prevented from being etched at the time of forming the contact. In addition, since the top and side walls of the gate electrode are covered with a material different from the interlayer insulating film such as silicon nitride, the contact is opened in a self-aligned manner with respect to the diffusion layer, and even if the opening pattern is misaligned. It is possible to prevent the contact from contacting or approaching the gate electrode.

Next, for example, as shown in FIG.
Titanium and titanium nitride in contact hole
An adhesion layer 33 is formed by depositing a thickness of 0 nm and 50 nm, and tungsten is deposited by a CVD method to a thickness of 250 nm to fill the contact holes CH1 and CH2 to form a plug layer.

Next, as shown in FIG.
The plug layer 34 and the adhesion layer 33 deposited outside the contact holes CH1 and CH2 by the MP method or the like are removed,
Adhesion layer 33 in which contact holes CH1 and CH2 are embedded
And a plug 34a are formed.

In the subsequent steps, an upper wiring 35 is formed of a conductive material such as aluminum on the upper layer of the plug 34a to obtain the semiconductor device shown in FIG.

According to the method of manufacturing a semiconductor device of the present embodiment, in the region 1, the side wall insulating film 24
Since the conductive impurity D2 is ion-implanted using the mask a and the etching stopper film 25 as a mask, the sidewall insulating film 24a and the etching stopper film 25 have a function as an LDD spacer, and the thickness of the sidewall insulating film is reduced. Can be formed without deteriorating transistor characteristics such as an increase in the short channel effect of the transistor.

In the region 2, the conductive impurity D3 is ion-implanted using the sidewall insulating film 24a and a part 25a of the etching stopper film on the side wall of the sidewall insulating film as a mask. In addition, a portion 25a of the etching stopper film has a function as an LDD spacer, and can be formed without deteriorating transistor characteristics such as an increase in a short channel effect of the transistor even when the thickness of the sidewall insulating film is reduced. it can. Further, in the step of forming a silicide layer in a self-alignment manner with respect to the high concentration diffusion layer, since the region 1 is covered with the etching stopper film, silicidation is not performed, and the region 2 has a self-source / drain diffusion layer. A silicide layer can be formed consistently. Even in this case, the silicide layer is not too close to the channel formation region of the transistor due to the sidewall insulating film and the etching stopper film on the side wall portion of the sidewall insulating film; It is possible to form the diffusion layer while suppressing an increase in leakage current in the diffusion layer.

According to the above-described method of manufacturing a semiconductor device, it is possible to form a contact in a diffusion layer between gate electrodes at a narrower distance between gate electrodes, further reduce the design rule, improve the degree of integration, and improve the semiconductor device. It is possible to increase the operation speed of the device, reduce power consumption, and reduce cost. Further, the etching stopper film of the contact can also function as a silicidation prevention film in the salicide process, and salicide can be partially formed without increasing the number of steps.

Second Embodiment The semiconductor device according to the present embodiment is substantially the same as the semiconductor device according to the first embodiment, and a sectional view thereof is shown in FIG. The difference from the semiconductor device according to the first embodiment is that a plug 36a made of, for example, polysilicon is formed in the first contact hole CH1 in the region 1.

A method for manufacturing the above semiconductor device will be described. First, up to the state shown in FIG. 10A, the semiconductor device is formed in the same manner as the process up to the state shown in FIG.

Next, as shown in FIG. 10B, the region 2 is entirely protected by a photolithography step, and a resist film (not shown) of an opening pattern of a contact hole only in the region 1 is formed by an interlayer insulating film 26. Pattern is formed on the upper layer, and silicon oxide is etched under conditions such that etching is slowed by an etching stopper film 25 such as RIE or plasma etching (for example, such that silicon oxide is removed at an etching rate 20 times that of silicon nitride). Etching corresponding to a thickness of 900 nm is performed, and a first contact hole CH1 exposing the etching stopper film 25 is opened. Here, as the etching conditions, for example, (RF power: 2 kW, gas flow rate: Ar / O ₂ / C ₄
F ₈ = 200/10 / 20sccm, pressure: 5Pa).

Next, as shown in FIG. 11C, the film thickness of 30 nm of silicon nitride is changed by changing the etching conditions so that, for example, silicon nitride is removed at an etching rate seven times that of silicon oxide. By the etching corresponding to the thickness, the silicon nitride (etching stopper film 25) exposed in the first contact hole CH1 is selectively removed, and the high concentration diffusion layer 12 is exposed. Here, the etching conditions are, for example, (RF power: 500 W, gas flow rate: Ar / O ₂ / CHF ₃ = 100/10/20 sccm, pressure: 5 Pa).

Next, as shown in FIG. 11D, the first contact hole CH1 is buried by, for example, a CVD method, and polysilicon is deposited on the entire surface to form a plug layer 36.

Next, as shown in FIG. 12E, the polysilicon deposited outside the first contact hole CH1 is removed by etch back, CMP, or the like.
Plug 3 embedded in first contact hole CH1
6a is formed.

Next, as shown in FIG. 12F, the region 1 is entirely protected by a photolithography step, and a resist film (not shown) of an opening pattern of a contact hole only in the region 2 is formed by an interlayer insulating film 26. Pattern is formed on the upper layer, and silicon oxide is etched under conditions such that etching is slowed by an etching stopper film 25 such as RIE or plasma etching (for example, such that silicon oxide is removed at an etching rate 20 times that of silicon nitride). The second contact hole C exposing the metal silicide layer 13 by performing etching corresponding to a thickness of 900 nm
Open H2. Here, as the etching conditions, for example, (RF power: 2 kW, gas flow rate: Ar / O ₂ / C ₄ F ₈ = 200
/ 10/20 sccm, pressure: 5 Pa).

Next, as shown in FIG. 13 (g), for example, titanium and titanium nitride are deposited in the second contact hole CH2 to a thickness of 20 nm and 50 nm, respectively, to form an adhesion layer 33, and furthermore, a CVD method. Tungsten is deposited to a thickness of 250 nm by a method to fill the second contact hole CH2 to form the plug layer 34.

Next, as shown in FIG. 13H, the plug layer 34 and the adhesion layer 33 deposited outside the second contact hole CH2 are removed by, for example, the CMP method or the like, and the second contact hole CH2 is removed. The embedded adhesion layer 33 and plug 34a are formed.

The subsequent steps include plugs 34a, 36
A semiconductor device shown in FIG. 9 can be obtained by forming an upper wiring 35 such as aluminum on the upper layer a.

According to the method of manufacturing the semiconductor device of the present embodiment, the region 1 and the region 2 are formed as in the first embodiment.
, Even if the thickness of the sidewall insulating film is reduced,
The transistor can be formed without deteriorating transistor characteristics such as an increase in a short channel effect of the transistor.

According to the present invention, in a semiconductor device of a MOS transistor such as a DRAM, for example, a semiconductor device in which a DRAM and a logic circuit are mixedly mounted, a contact hole is formed in a region between narrow electrodes formed on a semiconductor substrate. The present invention can be applied to any manufacturing method of a semiconductor device to be formed.

The present invention is not limited to the above embodiment. For example, each of the offset insulating film and the sidewall insulating film may be a single layer, or may be a multilayer or more. It is also possible to use an insulating material other than silicon nitride. The interlayer insulating film formed by covering the inner wall of the contact hole may have a single-layer structure or a multilayer structure. Further, the etching stopper film can be made of another insulating material, and can be a single layer or a multilayer. In addition, various changes can be made without departing from the spirit of the present invention.

[0086]

According to the present invention, there is provided a method of manufacturing a semiconductor device capable of stably forming a self-aligned contact hole without deteriorating transistor characteristics such as an increase in a short channel effect of the transistor. Can be.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 2A illustrates a process up to a process of forming a mask layer for forming an isolation trench. 4A shows up to the step of forming an element isolation groove, and FIG. 4C shows up to the step of forming an element isolation insulating film.

FIG. 3 is a sectional view showing a step subsequent to that of FIG. 2;
(D) shows up to the mask layer removing step, (e) shows up to the offset insulating film forming step, and (f) shows up to the gate electrode pattern processing step.

FIG. 4 is a sectional view showing a step subsequent to that of FIG. 3;
(G) shows up to the step of forming a low-concentration diffusion layer, (h) shows up to the step of forming a layer for a sidewall insulating film, and (i) shows up to the step of forming a sidewall insulating film.

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;
(J) shows the process up to the step of forming the etching stopper film (k).
(L) until the step of forming the high concentration diffusion layer in the region 1
Shows the process up to the step of removing the etching stopper film on the side of the side wall insulating film in the region 2.

FIG. 6 is a sectional view showing a step subsequent to that of FIG. 5;
(M) shows the process up to the step of forming the high concentration diffusion layer in the region 2.
(N) shows up to the step of forming a self-aligned silicide layer in the region 2, and (o) shows up to the step of forming an interlayer insulating film.

FIG. 7 is a sectional view showing a step subsequent to that of FIG. 6;
(P) shows the process up to the step of opening the contact hole, and (q) shows the process up to the step of removing the etching stopper film at the bottom of the contact hole.

FIG. 8 is a sectional view showing a step subsequent to that of FIG. 7;
(R) shows up to the plug layer forming step, and (s) shows the plug forming step.

FIG. 9 is a sectional view of a semiconductor device according to a second embodiment.

FIGS. 10A and 10B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a second embodiment, in which FIG. 10A illustrates up to a step of forming an interlayer insulating film, and FIG. The steps up to the opening step are shown.

11 is a cross-sectional view showing a step subsequent to that of FIG. 10. FIG. 11 (c) shows the step of removing the etching stopper film at the bottom of the contact hole in region 1, and FIG. 11 (d) shows the step of forming the plug layer. Is shown.

FIG. 12 is a cross-sectional view showing a step that follows the step shown in FIG. 11;
(F) shows up to the step of opening a contact hole in the region 2.

13 is a cross-sectional view showing a step subsequent to that of FIG. 12. FIG. 13 (g) shows up to a plug layer forming step, and FIG. 13 (h) shows a plug forming step in a region 2.

FIGS. 14A and 14B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a first conventional example. FIG.
(B) shows the process up to the contact hole opening step.

FIGS. 15A and 15B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a second conventional example. FIG. 15A illustrates a process of forming a resist film of an opening pattern of a contact hole.
(B) shows up to the step of opening the contact hole, and (c) shows the step up to the step of removing the etching stopper film at the bottom of the contact hole.

16A and 16B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a third conventional example. FIG. 16A illustrates a process up to a process of forming a mask layer for forming a trench for element isolation, and FIG. 4A shows up to the step of forming an element isolation groove, and FIG. 4C shows up to the step of forming an element isolation insulating film.

17 is a cross-sectional view showing a step subsequent to that of FIG. 16; FIG. 17 (d) shows a step until a mask layer removing step, FIG. 17 (e) shows a step until an offset insulating film forming step, and FIG. This shows up to the pattern processing step.

18 is a cross-sectional view showing a step that follows the step shown in FIG. 17; FIG. 18 (g) shows a step until a low-concentration diffusion layer is formed; FIG. ) Shows up to the step of forming the sidewall insulating film.

19 is a sectional view showing a step subsequent to that of FIG. 18; (j) shows a step of forming a high-concentration diffusion layer; (k) shows a step of forming an etching stopper film; The steps up to the step of forming an insulating film are shown.

20 is a cross-sectional view showing a step that follows the step shown in FIG. 19; FIG.
(N) shows the process up to the step of removing the etching stopper film at the bottom of the contact hole.

[Explanation of symbols]

Reference Signs List 10: semiconductor substrate, 11: low concentration diffusion layer, 12: high concentration diffusion layer, 13: metal silicide layer, 20: mask layer, 2
DESCRIPTION OF SYMBOLS 1 ... Element isolation insulating film, 22 ... Gate insulating film, 23, 23
a: Offset insulating film, 24: Layer for sidewall insulating film, 24a: Sidewall insulating film, 25, 25a, 2
5b, 25c etching stopper film, 26 interlayer insulating film, 30 lower gate electrode layer, 30a lower gate electrode, 31 upper gate electrode layer, 31a upper gate electrode, 32 gate electrode, 33 adhesion Layers, 34, 36: plug layer, 34a, 36a: plug, 35: upper wiring,
D1, D2, D3: conductive impurities, R1, R2, R3
R _CH resist film, CH, CH1, CH2 contact hole, T groove for element isolation.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/768 H01L 27/10 671Z 5F048 27/108 681F 5F083 21/8242 29/78 301P 29/78 21 / 336 F-term (reference) 4M104 AA01 BB01 BB14 BB20 CC01 DD02 DD04 DD07 DD08 DD17 DD19 DD26 DD43 DD79 DD84 DD94 EE05 EE09 EE15 EE17 FF13 FF22 GG14 GG16 HH15 5F004 AA16 BA04 DA00 DA16 DA23 A26 DA03 A03 A03 DA01 HH04 HH08 HH21 HH22 JJ18 JJ19 JJ33 KK01 KK25 MM08 MM15 NN06 NN07 NN40 PP06 QQ08 QQ09 QQ10 QQ13 QQ21 QQ25 QQ31 QQ37 QQ48 QQ58 ECQ65 QQ70 QQ73 QQ82 RR06 RR15 SS11 XXV TT15 SS01XXT EF02 EH02 EH07 EJ03 EK05 FA07 FA10 FA11 FB02 FB04 FC10 FC22 5F048 AB01 AB03 AC01 BB05 BB09 BB13 BC06 B F01 BF06 BF07 BF12 BF16 BG01 BG14 DA19 DA27 DA30 5F083 AD10 JA36 JA39 JA40 MA05 MA06 MA18 NA01 PR03 PR29 PR34 PR40

Claims (20)

[Claims] A step of forming a conductive layer in an active region of a semiconductor substrate; a step of forming an offset insulating film on the conductive layer; and a sidewall insulating film on sidewalls of the offset insulating film and the conductive layer. Forming an etching stopper film by covering the offset insulating film, the sidewall insulating film, and the semiconductor substrate; and forming the semiconductor substrate using the sidewall insulating film and the etching stopper film as a mask. Forming a first impurity-containing region containing a first concentration of conductive impurities in the semiconductor substrate by introducing conductive impurities while allowing the etching stopper film in the upper layer portion to pass therethrough; Forming an insulating film on the entire surface of the upper layer, and having a selectivity with respect to the etching stopper film. Exposing the etching stopper film in the contact hole opening region by etching to remove the insulating film in the contact hole opening region; and removing the etching stopper film exposed in the contact hole opening region to remove the first etching stopper film. Opening a contact hole exposing the impurity-containing region. 2. After the step of forming the offset insulating film and before the step of forming the sidewall insulating film,
A step of introducing a conductive impurity using the offset insulating film as a mask and forming a second impurity-containing region containing a second concentration of the conductive impurity lower than the first concentration in the semiconductor substrate; 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming the first impurity-containing region by connecting to the second impurity-containing region. 3. 3. The method according to claim 1, further comprising, before the step of forming the conductive layer, a step of forming an element isolation insulating film in an element isolation region of the semiconductor substrate.
2. The semiconductor device according to claim 1, wherein the device isolation insulating film is formed by further covering the device isolation insulating film.
The manufacturing method of the semiconductor device described in the above. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of opening the contact hole, the contact hole opening region is formed so as to include a part of the element isolation region. 5. The semiconductor device according to claim 1, further comprising, after the step of opening the contact hole, a step of filling the contact hole with a conductor to form a buried electrode connected to the high-concentration impurity-containing region. Manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein said etching stopper film is formed of a silicon nitride-containing layer, and said insulating film is formed of a silicon oxide-containing layer. 7. The method of manufacturing a semiconductor device according to claim 6, wherein said offset insulating film and said sidewall insulating film are formed of a silicon nitride-containing layer. 8. The semiconductor according to claim 3, wherein the step of forming the element isolation insulating film includes a step of forming an element isolation groove in the semiconductor substrate and a step of filling the element isolation groove with an insulator. Device manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 8, wherein said element isolation insulating film is formed of a silicon oxide containing layer. 10. A step of forming a conductive layer on the semiconductor substrate in a first region and a second region of a semiconductor substrate, and forming an offset insulating film on the conductive layer in the first region and the second region. Forming a sidewall insulating film on sidewalls of the offset insulating film and the conductive layer in the first region and the second region; and forming the offset insulating film in the first region and the second region. Forming an etching stopper film by covering the sidewall insulating film and the semiconductor substrate; and forming an etching stopper film in the first region by using the sidewall insulating film and the etching stopper film as a mask. A conductive impurity is introduced while passing through the etching stopper film, and a first concentration of the conductive impurity is introduced into the semiconductor substrate. Forming a first impurity-containing region to be contained; and in the second region, at least a portion of the etching stopper film covering the semiconductor substrate while leaving the etching stopper film on at least a side wall of the sidewall insulating film. Removing a conductive impurity in the second region by using the sidewall insulating film and the etching stopper film on the side wall of the sidewall insulating film as a mask, and introducing a second impurity into the semiconductor substrate. Forming a second impurity-containing region containing a conductive impurity, forming an insulating film on the entire surface of the first region and the second region, and etching the first region and the second region. The insulation in the contact hole opening region having a selectivity with respect to the stopper film By etching to remove the film, the etching stopper film is exposed in the contact hole opening region in the first region, and the high-concentration impurity-containing region is exposed in the contact hole opening region in the second region. A semiconductor device comprising: a step of opening a contact hole; and a step of opening a contact hole in the first region to remove the etching stopper film exposed in the contact hole opening region to expose the high-concentration impurity-containing region. Manufacturing method. 11. In the first region and the second region, after the step of forming the offset insulating film and before the step of forming the sidewall insulating film, conductive impurities are formed using the offset insulating film as a mask. And forming a third impurity-containing region in the semiconductor substrate, the third impurity-containing region containing a third concentration of a conductive impurity lower than the first concentration and the second concentration. In the step of forming the first impurity-containing region in one region, the first impurity-containing region is formed so as to be connected to the third impurity-containing region, and in the step of forming the second impurity-containing region in the second region, The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is formed so as to be connected to the third impurity-containing region. 12. The method according to claim 1, wherein the step of forming the second impurity-containing region in the second region and the step of forming an insulating film in the first region and the second region are performed in the second region. Forming a metal silicide layer on a surface portion of the impurity-containing region; and exposing the second impurity-containing region in the contact hole opening region in the second region, wherein the second impurity-containing region is formed. The method of manufacturing a semiconductor device according to claim 10, wherein the metal silicide layer formed in the surface layer portion is exposed. 13. In the first and second regions,
Prior to the step of forming the conductive layer, the method further includes a step of forming an element isolation insulating film in an element isolation region of the semiconductor substrate which is separated into at least the first region and the second region; In the forming step,
2. The semiconductor device according to claim 1, wherein the device isolation insulating film is formed by further covering the device isolation insulating film.
0. A method for manufacturing a semiconductor device according to item 0. 14. The manufacturing of a semiconductor device according to claim 13, wherein in the step of opening the contact hole in the first region, the contact hole opening region includes a part of the element isolation region. Method. 15. The method according to claim 10, further comprising: after the step of opening the contact hole in the first region, forming a buried electrode connected to the first impurity-containing region by filling the contact hole with a conductor. The manufacturing method of the semiconductor device described in the above. 16. The method according to claim 10, further comprising, after the step of opening the contact hole in the second region, forming a buried electrode connected to the second impurity-containing region by filling the contact hole with a conductor. The manufacturing method of the semiconductor device described in the above. 17. In the first and second regions,
The method according to claim 10, wherein the etching stopper film is formed of a silicon nitride-containing layer, and the insulating film is formed of a silicon oxide-containing layer in the first region and the second region. 18. In the first region and the second region,
18. The method of manufacturing a semiconductor device according to claim 17, wherein the offset insulating film and the sidewall insulating film are formed of a silicon nitride-containing layer. 19. The step of forming the element isolation insulating film includes the steps of:
2. The method according to claim 1, further comprising: forming an element isolation groove in the semiconductor substrate; and filling the element isolation groove with an insulator.
4. The method for manufacturing a semiconductor device according to item 3. 20. The method for manufacturing a semiconductor device according to claim 19, wherein said element isolation insulating film is formed of a silicon oxide containing layer.