JP2000268597A - Semiconductor memory and its address allotting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory and its address allotting method that can effectively utilized a spare memory cell array for redundancy when a defect does not exist. SOLUTION: This device is characterized in that an address of a normal memory cell array 21 is previously allotted to a spare memory cell array 22 for redundancy. When a defect occurs in a normal cell region, its defective address is allotted to a memory cell for redundancy, and it is replaced with an address allotted to a memory cell for redundancy before the replacement. When a defect does not exist or it is very few even if it exists, read-out margin exists, since bit line capacity is small, and a spare memory cell array 22 for redundancy in which a consumption current is small in bit line restoring can be effectively utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and an address allocating method thereof, and more particularly to a redundancy technology.

[0002]

2. Description of the Related Art In recent years, in a semiconductor memory device, in addition to a memory cell array normally used, a redundancy system having a memory cell array dedicated to redundancy has been widely used, and is called a centralized redundancy system.

Conventionally, in the centralized redundancy system, as shown in FIGS. 6A and 6B, a spare memory cell array 12 is arranged adjacent to a normal memory cell array 11.
If there is no defect in the normal cells in the normal memory cell array 11, only the normal memory cell array 11 is used as shown in FIG. (B) As shown in the figure, the spare memory cell array 12 is used in place of the redundancy cells. That is, when there is no defect in the normal cell, the normal memory cell array 1
, WLn,... In the spare memory cell array 12 are accessed.
WL is not accessed. On the other hand, for example, when a memory cell connected to the word line WLn in the normal memory cell array 11 has a defect, when the word line WLn in the normal memory cell array 11 is accessed, a spare is used instead of the word line WLn. The spare word line SWL in the memory cell array 12 is selected, and the defect is repaired in word line units.

However, in the above-described centralized redundancy system, if no failure occurs, the spare memory cell array 12 is wasted. The spare memory cell array 12 has the advantage that the bit line capacity is smaller than that of the normal memory cell array 11 so that there is a read margin and the current consumption in bit line restoration is small, but it has not been used effectively.

[0005]

As described above, in the conventional semiconductor memory device and its address allocation method, when there is no defect, the spare memory cell array is wasted and is not effectively used.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to effectively use a spare memory cell array for redundancy when no defect is present or when it is sufficiently small. An object of the present invention is to provide a semiconductor memory device that can be used and an address allocation method thereof.

[0007]

According to the first aspect of the present invention, a semiconductor memory device is not accessed when a defect does not exist, and a part of an address accessed in units of rows or columns when a defect occurs. And a memory cell array having a smaller storage capacity than the first memory cell and having the same number of rows or columns as the number of memory cells provided in one row or one column of the first memory cell array. An address corresponding to a memory cell having a memory cell in a column, which is allocated to a part of the first memory cell array and is accessed in a unit of row or column when a failure occurs, is accessed when a failure does not exist. A second memory cell array allocated as an address to be
When there is no defect, the first memory cell array is not accessed when there is no defect. When the defect occurs, the memory cell of the address other than the address accessed in units of rows or columns and the second memory cell array A memory cell at each address is accessed, and when a failure occurs in a memory cell in the first memory cell array, the memory cell in the second memory cell array is replaced in units of rows or columns. The address allocated to the memory cell in the second memory cell array to be accessed is not accessed when the defect in the first memory cell array does not exist, and is accessed in units of rows or columns when the defect occurs. It is characterized in that a memory cell at an address is replaced in units of rows or columns.

[0008] As described in claim 2, in the first memory cell array, an address which is not accessed when a defect does not exist, and which is accessed in units of rows or columns when a defect occurs, is the first memory cell array. It is an address of a memory cell in which a defect in the memory cell array is likely to occur.

According to a third aspect of the present invention, the address of the memory cell in which the defect is likely to occur is an address of a memory cell located at an end of the first memory cell array.

Further, according to the present invention, the first memory cell array is a normal memory cell array, and the second memory cell array is a spare memory cell array for redundancy.

Further, according to a fifth aspect of the present invention, there is provided a method of allocating addresses for a semiconductor memory device, wherein a portion of a first memory cell array is not accessed when a defect does not exist, and a row or a column is determined when a defect occurs. And the same number of memory cells provided in one row or one column of the first memory cell array as one row or one column, and the first memory The second memory cell array having a smaller storage capacity than the cell is not accessed when there is no defect allocated to a part of the first memory cell array, and is accessed in units of rows or columns when a defect occurs. An address corresponding to a memory cell to be accessed is assigned as an address to be accessed when no defect exists, and when no defect exists, the first memory is allocated. When a defect does not exist in the recell array, the memory cell is not accessed, and when a defect occurs, a memory cell of an address other than an address accessed in units of rows or columns and a memory cell of each address of the second memory cell array are accessed, When a failure occurs in a memory cell in the first memory cell array, the memory cell in the second memory cell array is replaced in units of rows or columns, and the memory in the replaced second memory cell array is replaced. The address assigned to the cell is stored in the first
When the defect does not exist in the memory cell array, the memory cell is not accessed, and when a defect occurs, the memory cell at the address accessed in the unit of row or column is replaced in the unit of row or column.

According to the present invention, the first memory cell array is a normal memory cell array, and the second memory cell array is a spare memory cell array for redundancy.

According to the first aspect of the present invention, when there is no defect, the second memory cell array having smaller parasitic capacitance, higher read margin and lower current consumption than the first memory cell array is accessed. Therefore, the second memory cell array having excellent characteristics can be effectively used.

According to a second aspect of the present invention, if the addresses of the memory cells in the first memory cell array where defects are likely to occur are allocated to the second memory cell array in advance,
The probability of performing defect relief is reduced.

As described in claim 3, since the address of the memory cell located at the end of the first memory cell array is liable to cause a defect, it is effective to reduce the probability of relieving the defect.

According to a fourth aspect of the present invention, if a normal memory cell array is provided as the first memory cell array and a spare memory cell array for redundancy is provided as the second memory cell array, the basic circuit configuration of the conventional semiconductor memory device can be obtained. Can be used.

According to the fifth aspect of the present invention, when there is no defect, the second memory cell array having a smaller parasitic capacitance, a higher read margin, and lower current consumption than the first memory cell array is preferred. The second memory cell array, which has excellent characteristics, can be effectively used.

According to a sixth aspect of the present invention, if a normal memory cell array is used as the first memory cell array and a spare memory cell array for redundancy is used as the second memory cell array, the conventional centralized redundancy system is applied. Addresses can be assigned while using the basic configuration described above.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B are for explaining an outline of a semiconductor memory device according to an embodiment of the present invention and an address allocating method thereof, and FIG. 1A shows no defective cell. FIG. 2B shows a case where a defective cell exists. (A) As shown in the figure,
The address of the normal cell in the normal memory cell array 21 is assigned to the spare cell for redundancy in the spare memory cell array 22. If there is a defect in the normal memory cell array 21, the defective address is assigned as shown in FIG. It is assigned to a spare cell in the spare memory cell array 22 and replaced with an address assigned to the spare cell in the spare memory cell array 22 before replacement. That is, when there is no defect in the normal cell, when the word line WL0 in the normal memory cell array 21 is accessed, the spare word line SWL in the spare memory cell array 22 is accessed and replaced in the normal memory cell array 21. , WL in the normal memory cell array 21 when another word line not accessed is accessed.
n,... are accessed. On the other hand, if there is a defect in a memory cell connected to the word line WLn in the normal memory cell array 21, for example, the address of the word line WLn is assigned to the spare word line SWL in the spare memory cell array 22, and the spare word line The address of the word line WL0 previously assigned to the SWL is assigned to the word line WL0 in the normal memory cell array 21. Thus, when word line WL0 in normal memory cell array 21 is accessed, normal memory cell array 21 is accessed, and when word line WLn is accessed, spare word line in spare memory cell array 22 is replaced with word line WLn. SWL is selected. As a result, when there is no defective cell, the spare cell array 21 is accessed, and a spare cell for redundancy, which has a small bit line capacity, has a read margin, and consumes little current in bit line restoration, can be used effectively.

FIG. 2 is a block diagram showing a schematic structure of a circuit portion related to address assignment in a semiconductor memory device for realizing the above-described address replacement. Sense amplifiers 23 and 24 are provided on both sides of the normal memory cell array 21, and sense amplifiers 25 and 26 are provided on both sides of the spare memory cell array 22. The row decoders 27 and 28 and the row decoder control circuit 34,
35 are provided. Although not shown, n normal memory cell arrays 21 are provided, and these n normal memory cell arrays 21 and sense amplifiers 23 and 2 are provided.
4. The row decoder 27 and the row decoder control circuit 34 constitute a unit cell array 29.

Output signal / FRHITi of redundancy selection circuit 30 for selecting whether or not to perform redundancy
("/" Added before the sign means an inverted signal, that is, a bar), / FRMISSi is supplied to the switching circuit 31, and the output signal / FSWLON of the switching circuit 31 is controlled by the row decoder of the spare memory cell array 22. Circuit 35
, And an output signal / FWLON is supplied to a row decoder control circuit 34 on the normal memory cell array 21 side, and a row decoder 27,
28 and the selection of a row address. Output signals of the respective sense amplifiers 23 to 26 are output via a DQ line 32 and an input / output circuit (I / O) 33. The input data is supplied to a normal cell or a spare cell for redundancy in each of the arrays 21 and 22 via the input / output circuit 33, the DQ line 32, and the sense amplifier.

FIG. 3 shows a configuration example of the normal memory cell array 21 and the spare memory cell array 22 in the circuit shown in FIG. Here is 64Mbit SD
A RAM is shown as an example. The normal memory cell array 21 and the spare memory cell array 22 are each divided into a large number of unit cell arrays, and the normal memory cell array 21 in each unit cell array has about 512 rows (= 512 word lines) / about 2048 columns (= 2048).
Bit line pairs, 2048 sense amplifiers). The spare memory cell array 22 has about 128 rows (=
128 word lines) / approximately 2048 columns (= 2048 bit line pairs, 2048 sense amplifiers). That is, while the normal memory cell array 21 has 1M bits, the spare memory cell array 22 has 256K bits.
Is a bit. As described above, generally, the storage capacity of the normal memory cell array 21 and the spare memory cell array 22 is smaller in the spare memory cell array 22.

FIG. 4 shows a configuration example of the redundancy selection circuit 30 in the circuit shown in FIG. The redundancy selection circuit 30 includes an address fuse circuit 40 capable of selecting an address by a fuse, a master fuse circuit 41, and a redundancy detection circuit 42 for detecting use of redundancy based on output signals of these circuits 40, 41. Have been. The address of the normal cell to be replaced at normal time is preprogrammed and assigned to the address fuse circuit 40. This address can be changed by blowing the fuse. The address fuse circuit 40 has address signals AR0 to ARn and its inverted signal / AR0.
To / ARn to output signals / FAR0 to / FARn. The input address signals AR0 to AR0 to A
When Rn, / AR0 to / ARn match the preprogrammed address, output signals / FAR0 to / FAR are output.
n is set to a low level. The master fuse circuit 41 normally sets the signal / FARM to a low level so as to declare the use of the redundancy cell, and cuts the fuse to generate the signal / FARM.
Is changed to a high level to declare that a normal cell is used without using a spare cell for redundancy. The redundancy detection circuit 42 outputs signals / FAR0 to / FR output from the address fuse circuit 40.
The use of the redundancy is detected by logically synthesizing the signal ARn and the signal / FARM output from the master fuse circuit 41. The redundancy detection circuit 42 outputs the signals / FAR0 to / FARn for a certain period after the input of the address.
/ FRHI is a signal / FRHI indicating that the use of redundancy has been detected when all signals are at the low level.
Ti (i = 0 to n) is output, and if any one is at a high level, the signal / FRMISSi (i = 0 to n) is output. That is, when the input address matches the address changed by pre-programming or blowing the fuse in the address fuse circuit 40 and the fuse is blown in the master fuse circuit 41, the redundancy selection circuit 30 selects the redundancy spare cell. It is configured to access.

If a normal cell other than the pre-programmed address has a defect, the address to be replaced is changed by cutting the fuse of the address fuse circuit 40, and the defective normal cell is replaced with a spare cell for redundancy. The pre-programmed address accesses a normal cell. At this time, the fuse of the master fuse circuit 41 is not blown. If there is a defect in the redundancy cell in which the preprogrammed address has been replaced, the fuse in the master fuse circuit 41 is blown to access the normal cell.

FIGS. 5A and 5B respectively show FIGS.
(A) is a circuit section for setting a spare state, and (b) is a circuit section for setting a normal state. The switching circuit 31 includes a redundancy selection circuit 30
In response to the output signals / FRHITi, / FRMISSi. Here, there are 32 unit cell arrays and i = 0 to
7 shows a circuit configuration example in the case of No. 7.

(A) The circuit section shown in FIG.
0 to 54, NOR gates 55 and 56, and an inverter 57. Signals / FRHIT0 and / FRHIT1, / FRHIT1, / FRHIT1, which indicate that the use of the redundancy output from the redundancy selection circuit 30 has been detected, are provided at the input terminals of the NAND gates 50 to 54, respectively.
2 and / FRHIT3, / FRHIT4 and / FRHIT
5, / FRHIT6 and / FRHIT7 are supplied, respectively. The output signals of the NAND gates 50 and 51 are supplied to a NOR gate 55, and the output signals of the NAND gates 52 and 53 are supplied to a NOR gate 56. Output signals of the NOR gates 55 and 56 are supplied to a NAND gate 54,
The output signal of NAND gate 54 is output via inverter 57 as signal / FSWLON.

On the other hand, the circuit section shown in FIG. 1B includes NOR gates 58 to 62, NAND gates 63 and 64, and an inverter 65. Noah gate 58-61
Are connected to the redundancy selection circuit 3
/ FRMISS0 and / FRMIS output from 0
S1, / FRMISS2 and / FRMISS3, / FRM
ISS4 and / FRMISS5, / FRMISS6 and / F
RMISS 7 is supplied. NOR gate 5
The output signals of 8, 59 are supplied to a NAND gate 63, and the output signals of the NOR gates 60, 61 are supplied to a NAND gate 64.
Supplied to The output signals of the NAND gates 63 and 64 are supplied to a NOR gate 62, and the output signal of the NOR gate 62 is output via an inverter 65 as a signal / FWLON.

According to the above configuration, when there is no defect or when there is a defect, the spare memory cell array 22 for redundancy can be effectively used. Spare memory cell array 2 for redundancy
Since the number of memory cells connected to one bit line 2 is 1/4 of that of the normal memory cell array 21, the bit line capacity is also about 1/4. Therefore, the initial potential difference of the bit line when data is read from the memory cell to the bit line is larger than that of the normal memory cell array 21, and the amplification operation can be performed more easily (the sense margin can be increased). In addition, it is also possible to reduce the current consumption in restoring (amplifying) the bit line to about ４ by reducing the bit line capacity.

[0030]

As described above, according to the present invention, a semiconductor memory device capable of effectively utilizing a spare memory cell array for redundancy and an address allocating method thereof when no defect is present or when there is a sufficiently small defect. Is obtained.

[Brief description of the drawings]

FIGS. 1A and 1B are for explaining an outline of a semiconductor memory device according to an embodiment of the present invention and an address allocating method thereof. FIG.
The figure shows a case where a defect exists.

FIG. 2 is a block diagram illustrating a schematic configuration of a semiconductor memory device that implements the address replacement shown in FIG.

3 is a circuit diagram showing a configuration example of a normal memory cell array and a spare memory cell array in the circuit shown in FIG. 2; FIG. 3 (a) is a normal memory cell array;
The figure shows a spare memory cell array.

FIG. 4 is a circuit diagram showing a configuration example of a redundancy selection circuit in the circuit shown in FIG. 2;

5A and 5B are diagrams for explaining a configuration example of a switching circuit in the circuit shown in FIG. 1; FIG. 5A shows a circuit section for setting a spare state, and FIG. 5B shows a circuit section for setting a normal state; FIG.

FIG. 6 is a diagram for explaining a conventional semiconductor memory device employing a centralized redundancy system and an address assignment method thereof.

[Explanation of symbols]

21: normal memory cell array (first memory cell array), 22: spare memory cell array (second memory cell array), 23 to 26: sense amplifier, 27, 28
... row decoder, 29 ... unit cell array, 30 ... redundancy selection circuit, 31 ... switching circuit, 32 ... DQ line, 3
3: Input / output circuit, WL0, WLn: Word line, SWL ...
Spare word line.

Continuing on the front page (72) Inventor Kazuyoshi Muraoka 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center Co., Ltd. (72) Shintaro Hayashi No. 1 Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor Makoto Hamada 580-1 Horikawa-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Co., Ltd. Inside Toshiba Semiconductor System Technology Center Co., Ltd. 580-1, Horikawa-cho, Ichiyuki-ku F-term (reference) in Toshiba Semiconductor System Engineering Center 5L106 CC04 CC17 CC32 EE02 EE07 FF01 GG00 GG06

Claims (6)

[Claims] 1. A first memory cell array in which an address which is not accessed when a defect does not exist and an address to be accessed in a unit of a row or a column when a defect occurs is partially assigned to the first memory cell array. Also has a small storage capacity, has the same number of memory cells in one row or one column as the memory cells provided in one row or one column of the first memory cell array, and is provided in a part of the first memory cell array. A second memory cell array, wherein the allocated address corresponding to the memory cell accessed in the unit of a row or a column when a defect occurs is allocated as an address accessed when a defect does not exist; Is not accessed when there is no defect in the first memory cell array when no defect exists, and when a defect occurs, a row or column unit A memory cell of an address other than an address to be accessed and a memory cell of each address of the second memory cell array are accessed, and when a failure occurs in a memory cell in the first memory cell array, the second memory When the memory cells in the cell array are replaced in units of rows or columns, and the addresses assigned to the replaced memory cells in the second memory cell array are replaced with the defective memory cells in the first memory cell array, A semiconductor memory device which is not accessed and is replaced in units of rows or columns with memory cells at addresses accessed in units of rows or columns when a defect occurs. 2. The method according to claim 1, wherein the first memory cell array includes:
The address that is not accessed when there is no defect and that is accessed in row or column units when a defect occurs is
2. The semiconductor memory device according to claim 1, wherein the address is the address of a memory cell in the first memory cell array where a defect is likely to occur. 3. The semiconductor memory device according to claim 2, wherein the address of the memory cell in which the defect is likely to occur is an address of a memory cell located at an end of the first memory cell array. 4. The device according to claim 1, wherein the first memory cell array is a normal memory cell array, and the second memory cell array is a spare memory cell array for redundancy. Semiconductor storage device. 5. A portion of the first memory cell array which is not accessed when a defect does not exist, is assigned an address to be accessed in a unit of row or column when a defect occurs, and is assigned to the first memory cell array. The second memory cell array, which has the same number of memory cells as one row or one column and one row or one column, and has a smaller storage capacity than the first memory cell, The address assigned to a part of the memory cell array is not accessed when there is no defect, and the address corresponding to the memory cell accessed in row or column units when the defect occurs is the address accessed when there is no defect When there is no defect, there is no access when there is no defect in the first memory cell array. A memory cell at an address other than an address accessed at a row or column unit and a memory cell at each address in the second memory cell array are accessed, and a failure occurs in a memory cell in the first memory cell array. Sometimes, the memory cells in the second memory cell array are replaced in units of rows or columns, and the addresses assigned to the replaced memory cells in the second memory cell array are stored in the first memory cell array. Address assignment in a semiconductor memory device, wherein a memory cell at an address accessed in a row or column unit is replaced in a row or column unit when a defect occurs, when the defect does not exist. Method. 6. The address assignment of the semiconductor memory device according to claim 5, wherein said first memory cell array is a normal memory cell array, and said second memory cell array is a spare memory cell array for redundancy. Method.