JP2000268017A - Pattern recognizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern recognizing device capable of recognizing a pattern and learning a reference vector for pattern recognition with a little wiring quantity and small circuit scale. SOLUTION: This pattern recognizing device is provided with a conversion means for converting the input pattern of an identification object to time sequential data for a prescribed bit length, identification means 13 and 14 for outputting the signal of the identified result on the input pattern by operating comparison between the time sequential data of that input pattern and the time sequential data for the prescribed bit of a reference pattern and a learning means 11 for updating the time sequential data of the reference pattern by operating the time sequential data of the input pattern and the time sequential data of the reference pattern most similar to that input pattern based on the identified result signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an odor / gas identification sensing system, a character / image recognition system,
The present invention relates to a pattern recognition device used for a voice recognition system or the like.

[0002]

2. Description of the Related Art Smell identification has been applied in many fields such as drug detection at airports, environmental measurement, and quality control of foods and beverages. Therefore, a method of identifying an odor from a plurality of sensor response patterns of the odor using a neural network has been considered.

When performing pattern recognition such as voice recognition and image recognition using a neural network as well as odor recognition, if the neural network is realized by software, the processing time becomes enormous for a complicated problem.
In addition, it is difficult to move a device such as a workstation, and the environment in which the device is used is limited. Therefore, it is necessary to reduce the size of the neural network having parallelism by increasing the speed of the neural network by hardware, and by using an LSI.

An example is shown below.

(1) Document 1: Digital neural network model (Katsuhiro Kamada, Yuzo Hirai, IEICE Technical Report, 1987, MBE)
87-157) A method is described in which a neural network is formed by transmitting signals between neurons using pulse signals, and the neural network is realized only by digital circuits. The strength of the signal is transmitted by the pulse frequency. However, the location of the synapse load is fixed at multiple bits and does not have a learning function.
In addition, positive and negative signals cannot be transmitted through one signal line for signal transmission, and two signals, an excitatory signal and a suppressive signal, are required.

(2) Document 2: Control system using 1-bit digital signal processing (Masanobu Segawa, Toshiro Higuchi, Minoru Kurosawa, Koichi Oka, SICE94, 109M-2) Indicates that operations such as addition, subtraction, multiplication, amplification, attenuation, and integration can be performed only by digital circuits.

(3) Literature 3: Research on measurement and identification circuit for odor sensor using 1-bit digital arithmetic method (Yasu Kubo, Takamichi Nakamoto, Toyoei Moriizumi, Institute of Electrical Engineers of Japan, 1998, SSA98- 11) In addition to the element circuit described in Document 2, the frequency change is Δ-Σ
We have developed a modulation circuit, an absolute value circuit, etc., and realized a measurement / identification circuit for an odor sensor by combining them. However, it does not have a learning function capable of dealing with various identification targets.

[0008]

As described above, conventionally,
ASIC (Application Specific Integratedcircui)
t), FPGA (Field Programmable Gate array)
There has been no pattern recognition apparatus that has both a discriminating function and a learning function with such a small wiring amount and circuit scale that can be easily integrated into one chip.

Accordingly, an object of the present invention is to provide a pattern recognition apparatus which can realize a pattern recognition and learning circuit with a 1-bit digital arithmetic circuit and can be easily configured with a small amount of wiring and a small circuit scale. .

[0010] That is, the present invention differs from Reference 1 in that
The synapse load can also configure a neural network with a small number of wires as a 1-bit digital signal and handle both positive and negative signals.
学習 Provides a learning operation function using a modulated signal.

[0011]

According to the present invention, there is provided a pattern recognition apparatus comprising: a conversion unit for converting an input pattern to be identified into 1-bit time-series data having a predetermined length;
Identification means for performing a comparison operation between the bit time-series data and one-bit time-series data of a predetermined length of the reference pattern to output an identification result signal for the input pattern; and the input pattern based on the identification result signal. Learning means for performing an operation between the 1-bit time-series data of the reference pattern and the 1-bit time-series data of the reference pattern closest to the input pattern to update the 1-bit time-series data of the reference pattern (By performing pattern recognition and learning of reference vectors used for pattern recognition by one-bit digital operation), pattern recognition and learning of reference vectors used for pattern recognition can be performed with a small amount of wiring and circuit scale. The above means can be distributed as a program that can be executed by a computer as well as a digital circuit by recording the program on a recording medium such as a floppy disk or a CD-ROM.

Further, the conversion means converts the input pattern into 1-bit time series data after normalizing the input pattern, so that pattern recognition can be performed without being affected by differences in environment such as odor / gas concentration and temperature. Can be done with precision.

Further, the identification means performs a comparison operation using a value (Manhattan distance) obtained by integrating an absolute value of a difference between the 1-bit time series data of the input pattern and the 1-bit time series data of the reference pattern. As a result, the transient response information itself of the sensor or the like can be used for identification, and the circuit can be easily configured as compared with the case of the Euclidean distance for calculating the square or the square root.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

(1) Odor / Gas Discrimination Device FIG. 1 shows a basic configuration example of a neuron unit constituting a learning / discrimination device according to this embodiment.

Each of the input signals from the plurality of sensors # 1, # 2, # 3,... Is, for example, time-division multiplexed in this order and input as an input pattern to the .DELTA .-. SIGMA.
Σ The signal is modulated and supplied to the neuron unit as a 1-bit signal. On the other hand, the synapse load is also time-division multiplexed, and Δ
−Σ The signal that has been modulated and converted into a 1-bit signal is stored in a serial memory (eg, FIFO (First In First Ou
t) The memory is stored in the synapse load storage unit 3. The arithmetic unit 2 sequentially reads out the synapse loads stored in the synapse load storage unit 3 and reads out the synapse loads from the synapse load storage unit 3.
After performing an operation on the 1-bit signal input from
It is output as a 1-bit signal. This output signal is input to the learning circuit 4 together with the teacher signal, and the 1
The bit signal is stored in the synapse load storage unit 3. By repeating this, learning can be performed.

FIG. 2 shows an example of the overall configuration of an odor / gas discriminating apparatus using the neuron unit of FIG.

The odor / gas discriminating apparatus shown in FIG. 2 multiplexes the sensor cell unit 101 and the output of the sensor cell unit 101 in order to measure the frequency change accompanying the adsorption amount of the odor / gas, and obtains the response pattern of the odor / gas. And a frequency measuring unit 102 for converting the data into 1-bit time-series data.
And a learning / identification circuit unit 103 for learning / identifying odor / gas response patterns by using a neural network configured by combining the neural units (the arithmetic unit 1, the learning circuit 4, and the synapse load storage unit 3). ing.

As shown in FIG. 13, here, the frequency measuring section 102 comprises four frequency counters 201a to 201a.
Using d, frequency changes from the four types of sensors are measured and multiplexed by the multiplexer 203. As the frequency counter, for example, a 14-bit binary counter that counts the number of pulses input during one second is used. Since the output of the counter constantly changes while being subjected to the coefficient, latch circuits 202a to 202d are required to hold data for one second.

In the frequency counters 201a to 201d,
The sensor signal before the odor is adsorbed is stored in the register as the initial value, and the sensor signal after the odor is adsorbed is newly counted from the value obtained by inverting each bit of the register value, thereby changing the frequency due to the odor adsorption. Is obtained.

In the frequency measuring section 102 shown in FIG.
The frequency counters 201a to 201d can measure the frequency changes of the four types of sensors in parallel and simultaneously.

The frequency change of each sensor is measured, and the multi-bit counter data is time-division multiplexed by the multiplexer 203. The odor / gas response pattern obtained in this manner is Δ-Σ modulated by the Δ-Σ modulator 204, and is 1-bit time-series data (for example, 2048-bit length)
Is converted to, for example, a FIF of 2048 bits × 1 configuration.
It is temporarily stored in the O memory 205.

The reason why the 1-bit time series data having a length of 2048 bits obtained by Δ-Σ modulation is stored in the FIFO memory 205 is, in particular, to repeatedly read input data during learning. In principle, the FIFO memory 205 is not necessary if measurement is performed every time learning is performed, but since this is inefficient, here, data used for learning is stored in the FIFO memory 205 in advance. In advance, the information is repeatedly read from here.

The 1-bit time series data sequentially read out from the FIFO memory 205 is input to the learning / identification circuit unit 103 and used for learning a neural network by LVQ (Learning Vector Quantization). .

Although Δ-Σ modulation is originally performed on analog data, here, 14-bit binary data is handled in the same manner as analog data, and Δ-Σ modulation is performed. A normal Δ-Σ modulation circuit is an analog subtractor,
Although an integrator is required, here, it can be constituted only by a digital circuit.

FIG. 14 shows an example of the configuration of the Δ-Σ modulator 12. Since the output of the integrator 211 is binary data,
The sign is determined by the value of the most significant bit. The inverted version of the most significant bit is the output. In FIG.
In the adder 210, the input is attenuated to 1 / K by the feedback gain K. This is the integrator 21
The value of K determines the measurable range of the frequency change. For example, here, the measurement range is 1024 Hz, and the gain is 1024 (2 ¹⁰ ) times.

FIG. 3 shows an example of the configuration of the learning / identification circuit unit 103 shown in FIG.
A part of the frequency measurement unit 102 is also shown in order to clearly show the connection relationship with. 2 is an LVQ circuit configured by combining the neuron units of FIG. This circuit determines a category to which an input pattern belongs. Hereinafter, the LVQ circuit will be described. However, the neuron unit of FIG. 1 can be applied to other neural networks such as a back vacation, an RBF (Radial Basis Function), and a Boltzmann machine.

In the LVQ, a number of reference vectors are arranged in a data space, and the distance between each reference vector and an input vector is calculated. Each reference vector belongs to one of the categories, and the category is predetermined.
Then, a reference vector closest to the input vector (this is referred to as a “nearest neighbor reference vector”) is detected, and it is determined that the category to which the reference vector belongs is the category of the input vector.

The distance calculation unit 13 calculates the distance between the 1-bit time series data of the response pattern of the odor and the gas and the reference vector of each category. The distance between the input vector and the reference vector is calculated by the following equation (1).

[0030]

(Equation 1)

This distance is not the Euclidean distance,
Time-division multiplexed waveform, that is, the Manhattan distance obtained by treating the response pattern itself as a vector and integrating the absolute value of the difference between the time-division multiplexed waveforms. When performing time-division multiplexing, not only the steady-state response of the sensor but also the transient response may be used. Therefore, if equation (1) is used, the transient response information itself can be used for identification.

In FIG. 3, for each reference vector (for example,
.., #N) corresponding to each of the N reference vectors is provided, and the distance calculation is performed in parallel. Determine the reference vector.

It should be noted that the subtraction circuit 21, the absolute value circuit 22, the integration circuit 23, and the distances obtained by all the distance calculation units 1 constitute each distance calculation unit 13 in FIG. 3 for calculating the distance based on the equation (1). 1 corresponds to the operation unit 2 in FIG. 1, and the reference vector FIFO memory 24 of each distance operation unit 13 in FIG. 3 is a synapse load storage unit in FIG. 3 and the nearest neighbor reference vector updating unit 11 in FIG. 3 corresponds to the learning circuit 4 in FIG.

The nearest reference vector detection unit 13 compares the distance between each input reference vector and the input vector, and detects the reference vector having the minimum value, that is, the nearest reference vector. Such a circuit is called WTA
(Winner Take All)
It is surprisingly difficult to construct a digital circuit. Usually, the minimum value is detected by a tournament method in which the magnitudes are sequentially compared two by two. However, when the number of reference vectors increases, the number of comparison operations increases dramatically. In addition, a huge number of comparators are required to perform simultaneous parallel comparison on all variables. Therefore, here, the following method is adopted.

That is, in the integrating circuit 23 at the last stage of each distance calculating section 13 in FIG. 3, the input 1-bit time series data is counted and integrated by an up / down counter (integrating counter). The output of the integration circuit 23 is multi-bit binary data, and the most significant bit indicates the sign of the integration value. Therefore, paying attention to this point, after the counting of the output of the absolute value circuit 22 is completed in all the integrating circuits 23 of each of the distance calculating sections 13, the integrating counter values are simultaneously simultaneously processed by all the integrating circuits 23. Decrease by "1". Then, when any of the counter values becomes negative, the nearest neighbor reference vector detection unit 14 determines the first negative reference vector of the integration counter as the nearest neighbor reference vector. Which one becomes negative first can be known by monitoring only the most significant bit of the integrating counter.
According to this method, an extra clock is required to reduce the value of the integrating counter. However, the detection circuit itself can be configured only with a simple configuration, and the circuit scale increases almost regardless of the number of reference vectors. do not do.

Next, the nearest neighbor reference vector updating unit 11 in FIG. 3 corresponding to the learning circuit 4 in FIG. 1 will be described. Here, the nearest neighbor reference vector is sequentially updated.

FIG. 4 shows an example of the configuration of the nearest neighbor reference vector updating unit 11. The nearest neighbor reference vector updating unit 11 determines whether the identification result is correct from the output (identification result) of the nearest neighbor reference vector detection unit 14 and the teacher signal generated by the control signal generation circuit 35, and increases the accuracy of the determination. , The nearest neighbor reference vector is updated.

The control signal generation circuit 35 generates a circuit operation timing in the learning / identification circuit section 103 of FIG. During learning, the reference vector F
The data in the IFO memory 24 is read and written. Note that the FIFO memory used here can simultaneously perform reading and writing, and write the updated reference vector simultaneously while reading the time-series data of the reference vector.

The following equation (2) is used for updating the nearest neighbor reference vector.

[0040]

(Equation 2)

The update amount α is a coefficient that monotonously decreases as the number of times of learning progresses. If the discrimination result coincides with the teacher signal, a positive sign is obtained by equation (2), and if not, a negative sign is obtained.

In FIG. 4, a subtraction circuit 32 obtains a difference between an input vector and a nearest reference vector before updating read out from the reference vector FIFO memory 13, and an attenuation circuit 33 calculates a difference between the input vector and the latest prior vector before updating. The difference from the side reference vector is multiplied by the update amount α.

In the adder circuit 34, as shown in FIG.
As shown in (a), if the identification result matches the teacher signal, the nearest reference vector is set as the input vector,

[0044]

(Equation 3)

As shown in FIG. 5B, if the discrimination result does not match the teacher signal, the nearest reference vector is used as the input vector,

[0046]

(Equation 4)

Only keep it away.

Here, a 1-bit addition (subtraction) circuit and a 1-bit absolute value circuit described in Reference 3 will be described.

FIG. 15 shows one-bit addition (subtraction) used in the distance calculation unit 13 and the nearest neighbor reference vector update unit 11.
2 shows a configuration example of a circuit.

As shown in FIG. 15, 1-bit addition is 3 bits.
It comprises an input adder 301, an integrator 302 and a comparator 303. However, “0” in the 1-bit signal is replaced by “−”.
Since it means "1", a general three-input adder cannot be used, and is realized by a combination circuit having a truth table shown in FIG.

The integrator 302 uses an adder and a D-flip-flop, and the most significant bit of the D-flip-flop in the integrator represents a sign. Therefore, this counter also has a role of a comparator, and a subtraction can be realized by feeding back the most significant bit as it is and adding it together with the inputs A and B. However, the output signal needs to invert this most significant bit.

FIG. 17 shows a block diagram of the 1 used in the distance calculation unit 13.
3 shows a configuration example of a bit absolute value circuit. In order to obtain the absolute value of the 1-bit signal, the sign of the signal at each time is obtained, and if it is negative, the signal is inverted. To examine the sign of each time, consider a moving average filter. It is known that in order to obtain an analog value at a certain point in time to obtain an analog value at a certain point in time, a D / A conversion of the Δ-Σ modulated signal may be performed by an average from several tens of points (for example, 64 points) in the past. This is obtained by integrating the value obtained by subtracting the value at 64 points before from the value at the current time, as derived by Expression (3).

[0053]

(Equation 5)

The circuit has a configuration as shown in FIG. Applying this, the sum of the past several points (for example, 64 points) is obtained by an up / down counter, and the sign thereof is determined to determine whether the point of interest is positive or negative. If the result is positive, the original signal is passed as it is, and if the result is negative, the signal is inverted and passed, whereby an absolute value circuit can be realized.

(B) Specific Example of Learning and Identification of Odor / Gas Next, a case where the gas is actually identified using the learning / identification circuit shown in FIG. 3 will be described with a specific example.

The configuration of the learning / identification circuit unit 103 shown in FIG. 3 is changed to VHDL (VHSIC Hardware Desert).
After describing and simulating with the description language (script Language), the FPGA (ALtera F
LEX10k50). This FPGA has a built-in memory, and by using it effectively, the entire circuit can be made into one chip.

It is assumed that odor samples are learned and identified on this chip using response pattern data of odors actually measured.

Here, there are two modes, a learning mode in which the reference vector is updated to the optimum value using the teacher signal, and an identification mode in which the input odor sample is identified using the obtained reference vector. Perform separately. For each category, simulations were performed for two cases, where the number of reference vectors was "1" and when the number was plural.

(B-1) In the case of each category 1 reference vector The response pattern data of the odor sample has three different characteristics.
Types of semiconductor gas sensors (sensor # 1, sensor # 2, sensor # 3 (manufactured by Figaro Giken, TGS8
25, TGS824, TGS822) (Data_1 to Data_6).

The sample odor gases were 100 ppm of acetone, ammonia, and hexane, and each sample was measured six times (Data_1 to Data_6).

In the learning mode, Data_1 was used as the initial value of the reference vector, and Data_2 was used as the teacher signal. FIG. 6 shows the data distribution of the reference vector around the sensor # 1 and the sensor # 3.

In FIG. 6, a white mark indicates a value of a response pattern (measurement data) of the sensor, and a black mark indicates a position of a reference vector obtained as a result of learning.

After learning, odor samples were identified using Data_3 to Data_6. FIG. 7 shows the identification result. Note that categories A, B, and C represent acetone, ammonia, and hexane, respectively.

It can be seen from FIG. 7 that the identification is correctly performed for all the measured data. This is by learning
This is because the obtained reference vectors correctly belong to the respective categories, and a correct nearest neighbor reference vector is detected.

(B-2) Case of each category 2 reference vector A simulation was performed by changing the number of reference vectors of each category to two. The measurement data of the odor sample to be used is the same as the last time, this time, 100 ppm acetone,
Learning and discrimination were performed only for two of the 100 ppm hexanes.

The learning of the reference vector is performed by setting Dat to the initial value.
a_1 and Data_2 and Data_3 as teacher signals.

FIG. 8 shows the data distribution of the reference vector around the sensor # 1 and the sensor # 3. In FIG. 8, a white mark indicates a value of a response pattern (measurement data) of the sensor, and a black mark indicates a position of a reference vector obtained as a result of learning.

After learning, odor samples were identified using Data_4 to Data_6. FIG. 9 shows the identification result. Note that categories A and B represent acetone and hexane, respectively.

In FIG. 8, the response of the sensor # 2 is omitted, the response pattern (measurement data) of the sensor used for learning is outlined, and the reference vector position after learning is indicated by black.

The identification result shown in FIG. 9 was correct in all the measurement data as in the case of one reference vector. In addition, referring to FIG. 8, the reference vectors indicate two points that are appropriately different within each category, and it is considered that the learning was correctly performed.

In the case where the distribution of categories is wide or the distance between categories is short, it is difficult to identify correctly with one reference vector. In such a case, it is necessary to use a plurality of reference vectors for each category.

The measurement data used for the simulation is
Since the distribution is relatively small and organized, even one reference vector in each category could be correctly identified.

FIGS. 6 to 9 show the simulation results. It was found that the data stored in the ROM was read out and the same operation was performed by a circuit mounted on the FPGA.

(B-3) When a Quartz Crystal Resonator Gas Sensor is Used Reference 3 describes a method of Δ-Σ modulation of the output of the frequency change of the crystal resonator gas sensor. In the case of a crystal oscillator gas sensor, since the output is a digital value, it is possible to design all circuits including the sensor interface circuit with a digital circuit, and it is easy to integrate the sensor into one chip. In addition,
Reference 3 did not have a learning function only with an identification circuit.

Now, by using the method described in Reference 3, by using the sensor response normalizing circuit shown in FIG.
The learning / identification circuit unit 103 can recognize the pattern of the crystal oscillator gas sensor array output pattern. That is, in order to handle odors having different concentrations, it is necessary to standardize the response pattern of the sensor array. Not only differences in concentration, but also data actually measured may have errors due to, for example, temperature conditions, environmental conditions such as the habit of the measurer, and the like.Therefore, normalization may be performed to minimize the errors. Required. However, for standardization, a division circuit is required, and a considerably complicated circuit is required.

According to the present invention, as shown in FIG. 10, a peak value detecting circuit 41 is provided. Here, the maximum frequency change among the frequency changes of a plurality of sensors is detected, and the Σ-Δ
The standardization is performed by making the full-scale value of the Δ-Σ modulation equal to the maximum frequency change, which has a feature that can be realized by a simple circuit.

As a sensor, 20 MHz, AT-CUT
Ethyl cellulose, UCON90000, quartz oscillator
Four samples coated with polyferniether and phosphatidylinositol were used, and benzene, butyl acetate, hexane, and 2-hexanone were used as samples.
1: 1, 1: 3, 1: 8 with DO (Octyl Decyl Oil)
Was used.

After placing each sample in the sample bottle, air was passed through the sample headspace for only one second, and the response waveforms of the four sensors (sensors # 1 to # 4) to the odor pulses for eight seconds were measured. FIG. 1 shows a response pattern obtained by time-division multiplexing and standardizing four sensor responses when the dilution ratio is 1: 3.
It is shown in FIG.

Further, learning is performed using data of a dilution ratio of 1: 3, with the number of reference vectors of each sample being “1”.
FIG. 12 shows waveforms of the obtained reference vectors A to D (benzene, butyl acetate, hexane, and 2-hexanone) after learning.

The results are simulation results obtained by describing a circuit in VHDL and using sensor data measured in advance. Although the reference vector is originally 1-bit digital data, FIG. 12 shows the data obtained by passing the data through a low-pass filter to obtain an analog value. Then, as a result of inputting measurement data of the samples having a dilution ratio of 1: 1, 1: 8, it was found that the samples could be correctly identified even if the concentrations were different.

(C) Effect As described above, according to the above-described embodiment, the ASIC, the ASIC, and the pattern recognition and the learning of the reference vector used for the pattern recognition are performed by the 1-bit digital operation.
A digital circuit that can be easily integrated into one chip such as an FPGA can be configured, and a portable sensing system with a discriminating function can be realized. Further, the amount of wiring and the circuit scale can be reduced as compared with the multi-bit operation method.

When the learning / identification circuit shown in FIG. 3 is combined with a sensor (for example, a semiconductor gas sensor array, a semiconductor gas sensor array, etc.), the odor / gas can be recognized with high accuracy and used as an environmental measurement and disaster prevention system. Can also. Further, if the robot is mounted on a robot for detecting the position of the odor source, the position and the type of the odor source can be simultaneously determined. In addition, the recognition target is not limited to smell, gas, etc.
It is also applicable to voice recognition and image recognition.

[0083]

As described above, according to the present invention,
By performing pattern recognition and learning of a reference vector used for pattern recognition by 1-bit digital operation, a pattern recognition device that can be easily configured with a small wiring amount and circuit scale can be provided.

[Brief description of the drawings]

FIG. 1 is a view showing an example of a second-hand configuration of a neuron unit using a 1-bit operation method according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the entire configuration of an odor / gas discriminating apparatus using the neuron unit of FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of a learning / identification circuit unit of the odor / gas identification device in FIG. 2;

FIG. 4 is a diagram showing a configuration example of a nearest neighbor reference vector updating unit.

FIG. 5 is a diagram for explaining the operation of a nearest neighbor reference vector updating unit;

FIG. 6 shows a specific example of odor and gas learning and identification, and shows response patterns (measurement data) of sensors # 1 and # 3 for each category in the learning mode in the case of each category 1 reference vector. FIG. 7 is a diagram showing a position distribution of reference vectors after learning and learning.

FIG. 7 is a diagram showing a specific example of odor / gas learning and identification, and showing a gas identification result in the identification mode in the case of each category 1 reference vector.

FIG. 8 shows another specific example of learning and discriminating odors and gases, in which sensor # 1 and sensor # 3 for each category in the learning mode in the case of each category 2 reference vector.
FIG. 7 is a diagram showing a response pattern (measurement data) and a position distribution of a reference vector after learning.

FIG. 9 is a view showing another specific example of learning and identification of odor / gas, and showing a gas identification result in the identification mode in the case of each category 2 reference vector.

FIG. 10 is a diagram showing a configuration example of a sensor response normalizing circuit when a crystal oscillator gas sensor is used.

FIG. 11 is a diagram showing an example of a sensor response pattern in which four sensor responses are time-division multiplexed and standardized for each of four samples.

FIG. 12 is an example of waveforms of reference vectors A to D (benzene, butyl acetate, hexane, and 2-hexanone, respectively) obtained by learning when the number of reference vectors is “1” for each of four samples. FIG.

FIG. 13 is a diagram illustrating a configuration example of a frequency measurement unit in FIG. 2;

FIG. 14 is a diagram illustrating a configuration example of a Δ-Σ modulation unit.

FIG. 15 is a diagram illustrating a configuration example of a 1-bit addition (subtraction) circuit.

FIG. 16 is a diagram showing a truth table of the adder shown in FIG. 15;

FIG. 17 is a diagram showing a configuration example of a 1-bit absolute value circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Delta-Σ modulation part 2 ... Calculation part 3 ... Synapse load calculation part (FIFO memory) 4 ... Learning circuit 101 ... Sensor cell part 102 ... Frequency measurement part 103 ... Learning / identification circuit part 11 ... Nearest neighbor reference vector update part 12 .... DELTA .-. SIGMA. Modulator 13 ... Distance calculator 14 ... Nearest reference vector detector 21 ... Subtraction circuit 22 ... Absolute circuit 23 ... Integration circuit 24 ... Reference vector FIFO memory 32 ... Subtraction circuit 33 ... Attenuation circuit 34 ... Addition circuit 35 ... Control signal generation circuit

Claims (3)

[Claims] 1. A conversion means for converting an input pattern to be identified into 1-bit time-series data having a predetermined length, and converting between the 1-bit time-series data of the input pattern and the 1-bit time-series data having a predetermined length of a reference pattern. A comparison unit that performs a comparison operation to output an identification result signal for the input pattern; 1-bit time-series data of the input pattern based on the identification result signal and 1-bit of a reference pattern that is closest to the input pattern Learning means for performing an operation with respect to the time-series data to update 1-bit time-series data of the reference pattern. 2. The pattern recognition apparatus according to claim 1, wherein said conversion means converts the input pattern into 1-bit time-series data after normalizing the input pattern. 3. The method according to claim 1, wherein the identifying unit is configured to output one of the input patterns.
2. The pattern recognition apparatus according to claim 1, wherein a comparison operation is performed using a value obtained by integrating an absolute value of a difference between the bit time series data and the 1-bit time series data of the reference pattern.