JP2000267849A - Pipeline processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a pipeline processor capable of shotening the total execution time without reducing the execution time of an instruction having the worst cycle time and performing a fast operation. SOLUTION: The number of clocks necessary to the processing stage of each instruction is set to each instruction, a clock generation circuit 17 generates a clock signal CLK in accordance with a stage needing the longest time among a series of instructions that are subjected to pipeline processing on the basis of the number of clocks supplied from an instruction decoder 15. For this reason, cycle time is not regulated by the worst cycle time, and processing time can be reduced because the cycle of the signal CLK is varied in accordance with a simultaneously executed instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processor capable of processing a plurality of instructions in parallel, for example, by overlapping each step of instruction execution.

[0002]

2. Description of the Related Art FIG. 9 shows the operation of a conventional pipeline processor. This type of pipeline processor has, for example, stages composed of instruction fetch (F), decode (D), execution of operation (E), memory access (M), and writing to a register (W). . The instruction fetch (F) reads an instruction from an instruction memory according to a program counter. The decode (D) decodes the read instruction and calculates an operand address. The execution of the operation (E) is performed by an arithmetic operation unit (ALU) or a floating point operation processing unit according to the decoding result. After this operation, for example, the data cache is accessed in the memory access (M), and the operation result is written in the register in the write stage (W).

[0003]

In the above-mentioned conventional pipeline processor, the cycle time of each stage is defined by the stage requiring the longest processing time in the pipeline stages of all instructions. Therefore, in the case of the example shown in FIG. 9, for example, when the operation execution (E) stage of the instruction 0 takes the longest time in the pipeline stages of all the instructions, the cycle time of the other stages is also the cycle time of this stage. Matched with time.

As described above, in a conventional pipeline processor, for example, a pipeline stage having one instruction is compared with a pipeline stage of another instruction by, for example, 1.
If it takes five times as long, even if the instruction is used very rarely, the cycle time of each stage of the processor is 1.
Must be set to 5 times.

In consideration of the design of a processor,
If the worst cycle time of all instructions and all pipeline stages, that is, the processing time of the pipeline stage with the longest cycle time is not shortened,
Processor performance does not improve. However, instructions with the worst cycle time generally perform complex processing. For this reason, in order to be able to process instructions having the worst cycle time at high speed, it is necessary to simplify complicated processing and reconsider the circuit design and manufacturing process. Therefore, it requires a great deal of labor and increases the production cost, which is not an advantage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the overall execution time without reducing the execution time of an instruction having the worst cycle time. And a pipeline processor capable of high-speed operation.

[0007]

SUMMARY OF THE INVENTION The pipeline of the present invention
In order to solve the above-mentioned problem, a processor is a pipeline processor that has a plurality of stages and a plurality of instructions are simultaneously executed while being shifted by one stage, wherein the different stages of the plurality of instructions that are simultaneously executed are different. Of the time information indicating the time required for the process set in
A selection circuit that selects the maximum time information; and a clock signal generation circuit that generates a clock signal from the time information selected by the selection circuit using a subclock signal having a frequency higher than the operating frequency of the pipeline processor. I have it.

The pipeline processor is configured to store the time information as a command of each instruction as an address, and to read the time information stored in the memory using the read command as an address when reading the instruction. And an additional circuit for reading the read instruction and adding the read instruction to the read instruction.

The pipeline processor stores the time information as a command of each instruction as an address, and decodes the time information stored in the memory using the command of the decoded instruction as an address when decoding the instruction. An additional circuit for reading and adding the instruction to the decoded instruction.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the pipeline processor of the present invention. This pipeline processor 11
Are, for example, an instruction memory 13 connected to the program counter 12, an instruction register 14 connected to the instruction memory 13, an instruction decoder 15 connected to the instruction register 14, a subclock generator 16, and a subclock generator 16. And a clock generation circuit 17 connected to the instruction decoder 15, an arithmetic operation unit (ALU) 18 connected to the clock generation circuit 17, a data cache memory 19, and a register 20.

The program counter 12 controls the order of instruction execution. One instruction stored in the instruction memory 13 is read out according to the output signal of the program counter 12 and loaded into the instruction register 14. The instruction stored in the instruction register 14 is an instruction decoder 15
Is decoded by

The subclock oscillator 16 is composed of, for example, a crystal oscillator, and generates a subclock signal having a frequency several times higher than the operating frequency of the processor. This sub clock signal is supplied to the clock generation circuit 17.
The clock generation circuit 17 controls a sub-clock signal according to a decoding result of the instruction decoder 15 to generate a clock signal.

In this embodiment, the instruction includes, for example, information on the processing time of each stage for processing the instruction in advance corresponding to the number of clocks of the subclock signal (hereinafter simply referred to as the number of clocks). Is set.

FIG. 2 shows an example of the instruction. In this example, the number of clocks 21 required for decoding (D), execution (E), memory access (M), and writing to a register (W) of the instruction 20 is “3”,
“4”, “1”, and “2” are set. As described later, since the fetch cycle of the instruction is the same for each instruction, it is not necessary to set the fetch cycle for each instruction.

The instruction decoder 15 has an instruction 20
And a plurality of shift registers, for example, that hold a clock number group 21 of a plurality of instructions to be sequentially decoded.

FIG. 3 shows a plurality of shift registers R0 to R3 provided in the instruction decoder 15. The shift register R0 holds a group of clock numbers of the first decoded instruction 0, and the shift register R3 holds a group of clock numbers of the last decoded instruction 3. The number of clocks held in each of the shift registers R0 to R3 is shifted according to, for example, a clock signal CLK supplied from the clock generation circuit 17, and output as the pipeline stage progresses. The broken lines shown in FIG. 3 indicate the signals currently output from each of the shift registers R0 to R3 and indicate the current processing stage state of the processor. That is, the instruction 0 indicates a write (W), the instruction 1 indicates a memory access (M), the instruction 2 indicates an execution (E), and the instruction 3 indicates an instruction decode (D). The group of clock numbers output from the shift registers R0 to R3 is supplied to the clock generation circuit 17.

FIG. 4 shows an example of the clock generation circuit 17. The clock generation circuit 17 has, for example, registers 17a, 17b, 17c, 17d, and 17e. The number of clocks of each stage supplied from the instruction decoder 15 is, for example, the registers 17b, 17c, 17d,
17e. That is, the register 17
To b, 17c, 17d, and 17e, the number of clocks in a portion surrounded by a broken line in FIG. 3 is supplied. Since the number of cycles required for the instruction fetch (F) is the same for each instruction as described above, the clock number "2" is set in advance in the register 17a, for example. The register 1
7a to 17e are “000” when the number of clocks is “1”.
"1" is set, and when the number of clocks is "2", "001" is set.
When "1" is set and the number of clocks is "3", "01" is set.
When the number of clocks is "4", "1111" is set.

The signals of the respective bits of the registers 17a to 17e are supplied to OR circuits 17f, 17g, 17h and 17i. The output signals of these OR circuits 17f to 17i are connected to the switches 17m and 17m constituting the switch circuit 17k.
n, 17o, 17p. Further, the switch circuit 17k has a switch 17l. The power supply Vss is supplied to the input terminal of the switch 17l, and the output terminal is connected to the switches 17m, 17n, 17o,
The output terminal 7p and the inverting input terminal of the AND circuit 17q are connected together. The subclock signal output from the subclock oscillator 16 is supplied to the other input terminal of the AND circuit 17q. The switches 17l to 1
7p is composed of, for example, a MOS transistor or a transfer gate. The switches 17l, 17m,
17n, 17o and 17p are the sub-clock oscillators 16
Are sequentially controlled by the sub-clock signal output from. The switch 171 has a function of generating a control signal.

In the above configuration, the switches 17p, 17
o, the signal supplied to the input terminal of 17n, 17m,
For example, if all of them are "1", and the switches 17p, 17o, 17n, and 17m are sequentially turned on in accordance with the subclock signal, the switches 17p, 17o, 17n, and 17m are turned on.
Is at a high level. Therefore, the AND circuit 1
The clock signal CLK output from 7q becomes low level as shown in FIG. Thereafter, the switch 17l is turned on, and when the control signal output from the switch 17l goes low, the AND circuit 17q outputs a high-level clock signal CLK. Hereinafter, the switches 17p, 17o, 17n,
17m and 17l are sequentially turned on.

As described above, the switches 17p, 17o, 1
When the signals supplied to the input terminals of 7n and 17m are all “1”, the cycle of the clock signal CLK is set to the sub-cycle corresponding to the memory access (M) of the instruction 1 which requires the longest time in the current processing. It is set to five times the period of the clock signal. Hereinafter, similarly, the cycle of the clock signal CLK is set corresponding to the stage requiring the longest time among the instructions for each operation cycle of the processor.

The clock signal CLK supplied from the clock generation circuit 17 is supplied to the program counter 12,
Instruction memory 13, instruction register 14, instruction decoder 1
5, the arithmetic operation unit 18, the data cache 19, and the register 20, respectively.
The operation of each stage is executed based on K.

FIG. 6 shows the relationship between instructions 0 to 4 and the processing cycle of the processor. As is apparent from FIG. 6, the processing cycle of the processor changes according to the stage of the instruction executed at the same time. That is, in the case of this embodiment, the time of each cycle is not defined as the worst cycle as in the related art. Therefore, the overall processing time of the processor can be reduced.

In FIG. 6, it is assumed that, for example, cycle 4 requiring the longest time is defined by the execution stage (E) of instruction 1. In this case, the stages (M), (D), and (F) of the other instructions are completed before the processing of the execution stage (E) of the instruction 1 is completed. In FIG. 6, a hatched portion indicates a waiting time to wait for the processing of the instruction 1 to be completed.

According to the above embodiment, the number of clocks required for the processing stage of each instruction is set for each instruction, and the clock generation circuit 17 performs the pipeline based on the number of clocks supplied from the instruction decoder 15. The clock signal CLK is generated according to the stage requiring the longest time in a series of instructions to be processed. For this reason, since the cycle of the clock signal CLK is changed according to the instruction executed at the same time, for example, when the stage of the instruction executed at the same time is constituted only by the stage having a short processing time, this processing cycle can be shortened. Can be terminated. Therefore,
The overall processing time of the processor can be reduced.

When an instruction having the worst time is rarely used, it is not necessary to increase the speed of the instruction. For this reason, it is not necessary to redesign the rarely used instructions in order to increase the speed, and thus it is possible to reduce development effort and development cost.

In the above embodiment, the case where the number of clocks of each stage is set in advance for each instruction has been described.
It is not limited to this.

FIG. 7 shows an example in which the number of clocks is added in the instruction memory 13. In the case of this example, for example, the command of each instruction is
The number of clocks corresponding to each stage of each instruction is stored. A read circuit 54 of the ROM 51 is connected between an instruction cache memory 52 constituting the instruction memory and a main storage device 53 composed of, for example, a dynamic RAM.

In the above configuration, the instruction cache memory 52 is accessed according to the operation of the program counter. At this time, if a miss occurs in the instruction cache memory 52, the main storage device 53 is accessed, and the corresponding instruction is read from the main storage device 53. The read instruction is stored in the instruction cache memory 52.

When an instruction is read from the main storage device 53, the read circuit 54 reads the clock number of the corresponding instruction stored in the ROM 51 using the read instruction command as an address. The read clock number is supplied to the instruction cache memory 52 and added to the read instruction. The following operation is the same as in the above embodiment.

FIG. 8 shows a case where the number of clocks is added between the instruction register 14 and the instruction decoder 15. For example, similarly to the ROM 51, the ROM 61 stores the number of clocks corresponding to each stage of each instruction using the command of each instruction as an address. Instruction register 1
The read circuit 62 of the ROM 61 is connected between the instruction decoder 4 and the instruction decoder 15.

In the above configuration, when an instruction is transferred from the instruction register 14 to the instruction decoder 15, the read circuit 62 reads the clock number of the corresponding instruction stored in the ROM 61 using the transferred instruction command as an address. It is. The read clock number is supplied to the instruction decoder 15, and the clock number is added to the transferred instruction. Subsequent operations are the same as in the above embodiment.

With the configuration shown in FIGS. 7 and 8, the number of clocks is added at the time of reading or transferring an instruction, and the number of clocks is not provided in the instruction itself. Therefore, the configuration of the instruction set can be simplified. Is possible. Further, by setting the number of clocks in the ROMs 51 and 61 after evaluating the speed of the processor to be implemented, there is an advantage that the optimum number of clocks can be set.

In FIGS. 7 and 8, the means for storing the number of clocks is not limited to a ROM.
A memory such as M can be applied.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0036]

As described in detail above, according to the present invention,
The time required for the entire processing can be reduced without reducing the worst cycle time, and a pipeline processor capable of high-speed operation can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an instruction applied to the present invention.

FIG. 3 is a view for explaining an operation of the instruction decoder shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating an example of a clock generation circuit illustrated in FIG. 1;

FIG. 5 is a waveform chart showing the operation of FIG.

FIG. 6 is a view for explaining the operation of FIG. 1;

FIG. 7 is a configuration diagram showing a modified example of the instruction memory shown in FIG. 1;

FIG. 8 is a configuration diagram showing a modification of the instruction decoder shown in FIG. 1;

FIG. 9 is a diagram for explaining the operation of a conventional pipeline processor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Pipeline processor, 12 ... Program counter, 13 ... Instruction memory, 14 ... Instruction register, 15 ... Instruction decoder, 16 ... Subclock oscillator, 17 ... Clock generation circuit, 18 ... ALU, 19 ... Data cache, 20 ... Registers 51, 61 ROM, 54, 62 read circuit.

Claims (3)

[Claims] 1. A method comprising: a plurality of stages;
A pipeline processor which is simultaneously executed while being shifted by stages, wherein the maximum time information among the time information indicating the time required for the processes respectively set in the different stages to be simultaneously executed of the plurality of instructions is set as the maximum time information. A selecting circuit for selecting, and a clock signal generating circuit for generating a clock signal from time information selected by the selecting circuit using a subclock signal having a frequency higher than an operating frequency of the pipeline processor. And a pipeline processor. 2. A memory for storing the time information as a command of each instruction as an address, and at the time of reading the instruction, reading the time information stored in the memory using the command of the read instruction as an address. 2. The pipeline processor according to claim 1, further comprising an additional circuit for adding the issued instruction. 3. A memory for storing the time information as a command of each instruction as an address, and at the time of decoding the instruction, reading the time information stored in the memory with the command of the decoded instruction as an address. 2. The pipeline processor according to claim 1, further comprising an additional circuit for adding an instruction to the instruction.