JP2000266806A - Device and method for inspecting semiconductor device, semiconductor device, and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a device for inspecting semiconductor devices capable of electrically reliably connecting solder bumps to a tester outside a chip without crushing the solder bumps or involving complicated work even in the case of the presence of varieties in the height of bumps on the chip. SOLUTION: An inspecting device 1 is provided with a susceptor 5, a probe substrate 6, a substrate 7, a signal line outlet 8, a container 9, and a pressing mechanism 10. A chip 11 is arranged in such a way that its back surface is in contact with the susceptor 5, and the substrate 6 is pressed against the solder bumps 12 of the chip 11 by the pressing mechanism 10. The probe substrate 6 is provided with a plurality of cantilevers 14 and needles 13. A pair of the cantilevers 14 and needles 13 are opposed to one solder bump 12. In the case that the substrate 6 is pressed toward the chip 11 by the pressing mechanism 10, the cantilevers 14 and the needles 13 are pressed against the solder bumps 12, the cantilevers 14 are bent and deformed, and the needles 13 are moved as scratching surfaces of the solder bumps 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for inspecting a semiconductor integrated circuit device, an inspection method, a semiconductor device inspected thereby, and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a chip generally cut out from a silicon wafer, molded with a resin or ceramic and packaged is heated in a furnace before shipment, and an acceleration called burn-in is performed. Tests were conducted to remove those that deteriorated with time, and shipped good products.

However, recently, due to a change in the package structure, a chip has been shipped as a product with solder bumps attached. For this reason, it has become necessary to perform a burn-in test by bringing a probe into contact with a solder bump.

[0004]

However, in the prior art, the height variation of the solder bump is as large as several tens of microns as compared with the case where the probe is brought into contact with the pad of the semiconductor chip. The reliability at the time of probing for contacting the contact is a problem.

That is, if the height of the solder bumps varies, the solder bumps are crushed or deep scratches are formed at the time of testing, so that the reliability as a product is often impaired.

Therefore, conventionally, the solder bumps are provided with an adhering substance so as to eliminate the height unevenness, or the test is carried out using a solder bump dedicated to the test, and then the bump is replaced with another bump. Attempted. As for this type of technology,
For example, those described in JP-A-4-56244 can be mentioned.

However, the operation of providing a deposit on the solder bump, performing a test using a dedicated solder bump, and then replacing the solder bump with another solder bump is very complicated, and lowers the manufacturing efficiency of the semiconductor device. It will also be.

[0008] An object of the present invention is to provide a method that does not involve complicated operations even when the bumps on a chip have height variations.
In addition, a semiconductor device inspection apparatus, an inspection method, a semiconductor device inspected by the inspection, and a semiconductor using the inspection, which can surely electrically connect the solder bump and the tester outside the chip without crushing the solder bump It is to realize a device manufacturing method.

Another object of the present invention is to provide a semiconductor device inspection apparatus capable of obtaining an electrically reliable connection by breaking an oxide film even when a thick oxide film is formed on a solder bump. To implement a semiconductor device inspected by the inspection, and a method of manufacturing a semiconductor device using the inspection.

[0010]

In order to achieve the above object, cantilever beams which are arranged to face each other may be provided so as to sandwich the side surfaces of the solder bumps. That is, since the cantilever beam is brought into contact with the side surface of the solder bump while being bent, the force exerted on the bump having the height variation in the vertical direction can be reduced.
The test can be performed without crushing with a tall bump.

Further, when the cantilever beam is brought into contact with the bump, it is necessary to remove an oxide film formed on the surface of the bump because the side of the bump is scratched by a needle formed at the tip of the cantilever beam. And highly reliable electrical connection becomes possible.

That is, in order to achieve the above object, the present invention is configured as follows. (1) In a semiconductor device inspection apparatus, a plurality of cantilevers in contact with solder bumps on a wafer to be inspected, a plurality of needles formed on each of the plurality of cantilevers, and pressing of the wafer and the cantilevers. A plurality of cantilevers are formed facing each other, and the needles formed on the cantilevers are connected by wires.

(2) Preferably, in the above (1),
The plurality of cantilevers are formed so as to be axially symmetric with respect to one solder bump.

(3) Preferably, in the above (1) or (2), the cantilever and the needle are made of single crystal silicon.

(4) Preferably, in the above (1) or (2), a plurality of needles are formed for each cantilever.

(5) In a semiconductor device having a solder bump formed on a chip, the solder bump extends vertically on a side surface of the solder bump and has a plurality of flaws symmetrically with respect to the center axis of the solder bump.

(6) In the method for inspecting a semiconductor device, a plurality of needles formed on a plurality of cantilevers may be replaced by
Pressing a solder bump on a wafer to be inspected, a step of inputting a signal for a test to a semiconductor device through the cantilever, the needle and the solder bump, and a step of:
Analyzing the electrical signal returned via the needle and the cantilever to determine the quality of the semiconductor device.

(7) In the method of manufacturing a semiconductor device, a step of forming a semiconductor element, a wiring, and an electrode on a wafer, a step of forming a solder bump on the electrode, and a step of forming a plurality of cantilevers formed on a plurality of cantilevers. A step of pressing a needle against a solder bump on the wafer as an object to be inspected; a step of inputting a signal for a test to a semiconductor device via the cantilever, the needle and the solder bump; and Solder bumps,
Analyzing the electrical signal returned via the needle and the cantilever, and performing a pass / fail determination of the semiconductor device,
Selecting a semiconductor device determined to be good by the quality judgment.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view showing a schematic cross-sectional structure of a semiconductor device inspection apparatus 1 according to a first embodiment of the present invention, and FIG. 2 is a view showing the inspection apparatus 1 shown in FIG.
It is operation | movement explanatory drawing of FIG. FIG. 3 is a top view in which a part of the inspection apparatus 1 shown in FIG. 1 is omitted.

In the first embodiment of the present invention shown in FIG. 1, the inspection apparatus 1 includes a susceptor 5, a probe substrate 6, a substrate 7, a signal line outlet 8, a container 9, and a pressing mechanism 10. The chip 11 is arranged such that the back surface of the chip 11 (the surface opposite to the surface with which the solder bump 12 contacts) is in contact with the susceptor 5, and is formed on the probe substrate 6 and the surface of the chip 11 by the pressing suppression mechanism 10. Solder bump 1
2 is pressed.

The probe substrate 6 is provided with a plurality of cantilevers 14 and needles 13 formed on the surface of the cantilever 14 on the chip 11 side. A pair of cantilevers 14 and needles 13 are provided so as to face one solder bump 12.

When the probe mechanism 6 is pressed in the direction of the chip 11 by the pressing mechanism 10, the cantilever 1
4 and the needle 13 perform the following operation on the solder bump 12.

FIG. 2 shows a state where the cantilever 14 has not yet been pressed against the solder bump 12. In this case, the cantilever 14 has a substantially flat shape, and the cantilever 14 or the needle 13 is
Weak contact with 2.

However, since the height of the solder bumps 12 varies, the cantilever 14 and the solder bumps 12 may not be in contact with each other. Although the opposing cantilevers are not in contact with each other, the clearance between the opposing cantilevers 14 may be small as shown in FIG. FIG. 3 shows the circuit board 7, the signal line outlet 8,
The pressing mechanism 10 is not shown.

Since the needle 13 formed near the tip of the cantilever 14 is located at a position shifted from the rotational symmetry axis of the solder bump 12, the needle 13 comes into contact with the side surface of the solder bump 12. . The cantilevers 14 facing each other are connected by a wiring 15 and are in an electrically conductive state.

Next, when the probe substrate 6 is pressed by the pressing mechanism 10 in the direction of the chip 11, the cantilever 14 is bent and deformed as shown in FIG.
3 moves while scratching the surface of the solder bump 12.

As described above, in the first embodiment of the present invention, the oxide film layer existing on the surface layer of the solder bump 12 can be easily broken as compared with the case where the needle 13 is simply pressed against the solder bump 12. Therefore, there is an advantage that reliable conduction can be obtained.

In the first embodiment, since excessive force does not act on the solder bump 12 as in the case where the needle 13 is simply pressed onto the solder bump 12 from above, the solder bunf 12 does not collapse. There are advantages.

Further, according to the first embodiment, since conduction is established at two places of the solder bump 12, there is an advantage that reliability is increased as compared with the case where conduction is established at one place of the solder bump 12.

That is, in the case where conduction is established between one needle and the cantilever 14 as in the conventional method, the entire probe must be replaced due to damage to the needle.
According to the first embodiment, even if one needle 13 or cantilever 14 is damaged, the other needle 13
The probe can be exchanged with the cantilever 14 so that the probe need not be replaced.

Furthermore, even when the solder bumps 12 have a variation in height, the cantilever 14 can bend and absorb the variation, so that there is an advantage that even the solder bumps 12 having a high height can be easily inspected.

Further, when the solder bump 12 is displaced from the intersection of the cantilevers 14, that is, the position to be the axis center of the solder bump 12, there is an advantage that a force acts to return the solder bump 12 to a predetermined position.

That is, when the solder bumps 12 are misaligned, one cantilever is placed on the opposing cantilevers.
Since the force acting on the roller 4 is biased, a force is generated that pushes the solder bump 12 back to the original axial center position. Therefore, even when the solder bumps 12 are misaligned due to insufficient chip alignment, this can be corrected.

The material of the cantilever 14 can be a metal having heat resistance and corrosion resistance, such as a cobalt alloy, a nickel alloy, and a stainless steel alloy. Further, as the material of the cantilever 14, a material in which a metal is vapor-deposited on the surface of a ceramic may be used. Further, as the material of the cantilever 14, a heat-resistant resin or single-crystal silicon may be used, and a metal on the surface thereof may be deposited.

The material of the needle 13 can be metal or single crystal silicon. When silicon is used as the material of the needle 13, a metal film is formed on the surface of the needle 13 so that the solder bump 12 and the wiring 15 are electrically connected through the needle 13.

FIG. 4 is a partially omitted top view of the second embodiment of the present invention. The second embodiment is an example in which four cantilevers 14 are provided for one solder bump 12.

As shown in FIG. 4, a pair of cantilevers 14 opposed to each other is connected to another pair of cantilevers 14.
They are arranged in directions orthogonal to each other. The wires 15 from the four cantilevers 14 are in an electrically conductive state.

Note that other configurations are the same as those described in the first embodiment.
Since the embodiment is the same as that of the first embodiment, illustration and detailed description thereof are omitted.

The second embodiment has the following advantages in addition to the advantages of the first embodiment.

First, when the solder bump 12 is displaced from the intersection of the four cantilevers 14, that is, the position to be the axis center of the solder bump 12, the solder bump 1
There is an advantage that a force acts to return 2 to a predetermined position.

That is, when the solder bump 12 is displaced, the force acting on the opposing cantilever 14 is deviated, and a force is generated to push the solder bump 12 back to the original axial center position. . Therefore, even when the position of the solder bump 12 is displaced due to insufficient alignment of the chip 11, this can be automatically corrected. Further, since the four cantilevers 14 are in contact with the solder bumps 12, there is an advantage that redundancy is further increased.

Although four cantilevers 14 are provided in the second embodiment, three cantilevers 14 have the same effect as shown in FIG. Alternatively, more cantilevers 14 may be provided.

FIG. 6 is a partially omitted top view of the third embodiment of the present invention. FIG. 7 shows the cantilever 14 having the needle 13 formed therein and the solder bump 1 according to the third embodiment.
2 is an enlarged plan view of FIG. In the third embodiment, one cantilever 14 is provided with two needles 13.

In the third embodiment, the two needles 13 are located at positions separated from each other on one cantilever 14, and can be scratched while sandwiching the side surfaces of the solder bumps 12. There is an advantage that can be easily removed. Furthermore, solder bumps 12
When the solder bump 12 is displaced from a position that should be the axis center of the above, a force acts to return the solder bump 12 to a predetermined position, so that even if the displacement occurs, it can be automatically corrected.

In the third embodiment, two needles 13 are arranged on one cantilever 14, but more needles 13 may be arranged. Note that other configurations are the same as those of the above-described first embodiment, and thus illustration and detailed description thereof are omitted.

FIG. 8 is a view showing a schematic sectional structure of a semiconductor device inspection apparatus 1 according to a fourth embodiment of the present invention. In the fourth embodiment, the cantilever 14 and the needle 13 are formed by processing a silicon substrate.

That is, a silicon substrate is processed using a micro-machining technique of processing by photolithography and etching, and a cantilever 1 having high dimensional accuracy is obtained.
4 and the needle 13 are created.

According to the fourth embodiment, the chip 11
Since the thermal expansion coefficient of the cantilever 14 is equal to that of the cantilever 14, there is an advantage that even when the temperature is increased, the positional relationship between the two does not shift and accurate probing can be performed.

Further, since high-precision processing can be realized as high as the accuracy in manufacturing a semiconductor device, there is an advantage that high-precision probing can be performed.

FIG. 9 is a view showing a schematic sectional structure of a semiconductor device inspection apparatus 1 according to a fifth embodiment of the present invention. In the fifth embodiment, the ends of the cantilevers 14 facing each other in the first embodiment are connected to form a doubly supported beam 16. And beam 1
6, the needles 13 are provided at two places, and these needles 13 come into contact with the side surfaces of the solder bumps 12.

In the above configuration, when the probe substrate 6 is pressed toward the chip 11 by the suppression mechanism 10, the beam 1
6 is deformed by bending, and the needle 13 is connected to the solder bump 1
2 moves while scratching the surface.

Therefore, in the fifth embodiment, the oxide film layer existing on the surface layer of the solder bump 12 can be easily broken as compared with the case where the needle 13 is simply pressed against the solder banff 12, so that reliable conduction can be achieved. There is an advantage that can be taken. In the fifth embodiment, two needles 13 are arranged on the beam 16, but the same effect can be obtained by arranging two or more needles.

FIG. 10 is a partially omitted top view of the sixth embodiment of the present invention. In the sixth embodiment, a plurality of needles 13 for contacting a plurality of solder bumps 12 are formed on a pair of cantilevers 14 facing each other.

In the sixth embodiment, the same effect as in the first embodiment can be obtained.

FIG. 11 is a partially omitted top view of the seventh embodiment of the present invention. In the seventh embodiment, a plurality of needles 13 for contacting a plurality of solder bumps 12 are formed on one doubly supported beam 14. In FIG. 11, the solder bumps 12 are arranged in a portion that cannot be seen by the doubly supported beams 14, but are shown for convenience of explanation.

In the seventh embodiment, the same effect as in the first embodiment can be obtained.

FIG. 12 is a partially omitted top view of the eighth embodiment of the present invention. In the eighth embodiment, a plurality of needles 13 for contacting a plurality of solder bumps 12 are formed on a diaphragm 14A. In FIG. 12, the solder bumps 12 are arranged in a part that cannot be seen by the diaphragm 14A, but are shown for convenience of explanation.

In the eighth embodiment, the same effects as in the first embodiment can be obtained.

FIG. 13 is a schematic flowchart of a method for manufacturing a semiconductor device having a step of performing inspection using the semiconductor device inspection apparatus of the present invention. In step 100 of FIG. 13, elements, wiring, and electrodes are formed on the wafer. Next, in step 101, solder bumps are formed on the electrodes formed in step 100. Then, in step 102, the wafer is mounted in the container 9 of the above-described inspection apparatus 1 according to the present invention.

Next, in step 103, the needle 13 of the cantilever 14 is moved by the pressing mechanism 10 to the solder bump 1.
2 against the side surface to tear (scratch) the oxide film layer.
Then, in step 104, an electric signal for a test is input through the wiring 15 connected to the cantilever 14 and the needle 13.

Subsequently, in step 105, an electric signal is returned from the chip on the wafer via the wiring 15 and the needle 13 connected to the cantilever 14. Then, in step 106, the returned signal is analyzed by the chip inspection device, and the quality of the chip is determined. Next, in step 107, chips are cut out from the wafer by dicing, and non-defective chips are selected.

As described above, according to the present invention, even when the bumps on the chip have a variation in height, there is no need for complicated work and without crushing the solder bumps.
An inspection method using a semiconductor device inspection apparatus capable of reliably electrically connecting a solder bump and a tester outside a chip and a semiconductor device manufacturing method using the inspection method can be realized.

In the semiconductor device manufactured by the above-described manufacturing method or the semiconductor device inspected by the above-described inspection method, a scratch extending in the vertical direction is formed on a side surface of the solder bump.

[0064]

According to the present invention, even when the bumps on the chip have a variation in height, the solder bumps and the tester outside the chip can be reliably connected without complicated work and without crushing the solder bumps. It is possible to realize a semiconductor device inspection apparatus, an inspection method, a semiconductor device inspected by the inspection, and a semiconductor device manufacturing method using the inspection, which can be electrically connected.

In addition, even when an oxide film is formed thick on the solder bump, a semiconductor device inspection apparatus, an inspection method, and an inspection method by which a reliable electrical connection can be obtained by breaking this oxide film. Semiconductor device and a method for manufacturing the semiconductor device using the inspection thereof can be realized.

Further, according to the present invention, an excessive force does not act on the solder bump in the vertical direction as in a case where the needle is simply pressed against the solder bump, so that the solder bump is not broken and the damage to the solder bump is minimized. There is an advantage that can be limited.

Further, according to the present invention, since conduction is performed at two locations, there is an advantage that reliability is increased as compared with the case where conduction is performed by one.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic sectional structure of a semiconductor device inspection apparatus according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory view of the inspection apparatus shown in FIG.

FIG. 3 is a top view in which a part of the inspection apparatus shown in FIG. 1 is omitted.

FIG. 4 is a partially omitted top view of a second embodiment of the present invention.

FIG. 5 is a diagram showing a modification of the second embodiment of the present invention.

FIG. 6 is a partially omitted top view of a third embodiment of the present invention.

FIG. 7 is an enlarged plan view of a cantilever and a solder bump on which a needle according to a third embodiment is formed.

FIG. 8 is a diagram showing a schematic cross-sectional structure of a semiconductor device inspection apparatus according to a fourth embodiment of the present invention.

FIG. 9 is a view showing a schematic cross-sectional structure of a semiconductor device inspection apparatus according to a fifth embodiment of the present invention.

FIG. 10 is a partially omitted top view of a sixth embodiment of the present invention.

FIG. 11 is a partially omitted top view of a seventh embodiment of the present invention.

FIG. 12 is a partially omitted top view of the eighth embodiment of the present invention.

FIG. 13 is a schematic flowchart of a method of manufacturing a semiconductor device having a step of performing inspection using the semiconductor device inspection apparatus of the present invention.

[Explanation of symbols]

 Reference Signs List 1 inspection device 4 signal line 5 susceptor 6 probe substrate 7 substrate 8 signal line outlet 9 container 10 pressing mechanism 11 chip 12 solder bump 13 needle 14 cantilever 14A diaphragm 15 wiring 16 beam

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Miura 502 Kandachi-cho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratories, Hitachi, Ltd. Hitachi, Ltd. Semiconductor Business Headquarters (72) Inventor Naoto Ban 5--20-1, Kamizuhoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Headquarters (72) Inventor Yasuhiro Motoyama Kamimizuhoncho, Kodaira-shi, Tokyo 5-20-1, Hitachi Semiconductor Company Headquarters (72) Inventor Hideyuki Aoki 5-20-1, Kamimizu Honmachi, Kodaira City, Tokyo F-term, Hitachi Semiconductor Company Headquarters F-term (reference) 2G003 AA07 AA10 AC01 AF06 AG03 AG12 AG20 AH07 2G011 AA02 AA16 AB01 AC06 AC14 AE03 AF01 2G032 AA00 AB02 AB13 AF02 AG01 AK01 AL03 4M106 AA01 A D08 AD09 AD26 CA70 DD03 DD09

Claims (7)

[Claims] 1. A semiconductor device inspection apparatus, comprising: a plurality of cantilevers that are in contact with solder bumps on a wafer to be inspected; a plurality of needles formed on each of the plurality of cantilevers; Wherein the plurality of cantilevers are formed so as to face each other, and the needles formed on the cantilevers are connected by wiring. Inspection equipment. 2. A semiconductor device inspection apparatus according to claim 1, wherein said plurality of cantilevers are formed so as to be axially symmetric with respect to one solder bump. 3. The semiconductor device inspection apparatus according to claim 1, wherein the cantilever and the needle are made of single crystal silicon. 4. The apparatus for inspecting a semiconductor device according to claim 1, wherein a plurality of needles are formed for each cantilever. 5. A semiconductor device having a solder bump formed on a chip, wherein the semiconductor device has a plurality of flaws extending in a vertical direction on a side surface of the solder bump and axially symmetric with respect to a center axis of the solder bump. 6. A method for inspecting a semiconductor device, comprising: a step of pressing a plurality of needles formed on a plurality of cantilevers against solder bumps on a wafer to be inspected; and a step of pressing the plurality of needles via the cantilevers, the needles and the solder bumps. Analyzing the electrical signal returned from the semiconductor device via the solder bumps, the stylus and the cantilever, and performing a pass / fail determination of the semiconductor device. A method for inspecting a semiconductor device, comprising: 7. A method of manufacturing a semiconductor device, comprising: a step of forming a semiconductor element, a wiring and an electrode on a wafer; a step of forming a solder bump on the electrode; and a step of forming a plurality of needles formed on a plurality of cantilevers. Pressing a solder bump on the wafer as an object to be inspected; inputting a test signal to a semiconductor device via the cantilever, the needle and the solder bump; and Analyzing the electric signal returned via the stylus and the cantilever and performing a pass / fail judgment on the semiconductor device; and a step of selecting the semiconductor device judged to be good by the pass / fail judgment. A method for manufacturing a semiconductor device.