JP2000260993A - Thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress decrease of on-current by specifying the peak angle of a protrusion on a rough surface present at the interface between a semiconductor film and a gate insulating film to be at least a right angle, or specifying width and height of the protrusion on the rough surface. SOLUTION: The thin-film transistor comprises a semiconductor film 2 and a gate electrode 4 with a gate insulating film 3 between them. Here, an apex angle A of the protrusion of a rough surface 8 present at the interface between the semiconductor film 2 and the gate insulating film 3 satisfies A>90 deg.. Otherwise, a width W and height H of the protrusion of the rough surface 8 satisfy an equation: (W/2)H>tan(90 deg./2). Since the shape of the rough surface 8 does not prevent conduction of carrier, drop of on-current is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor, and more particularly to a thin film transistor having a semiconductor film and a gate electrode, and having a gate insulating film between the semiconductor film and the gate electrode.

[0002]

2. Description of the Related Art In recent years, thin film transistors have been widely used as a means for realizing a lightweight and thin display device represented by a liquid crystal display or an electroluminescence display, or a scanner, a detector or other devices.

FIG. 1 shows a structure of a thin film transistor.
A semiconductor film 2 is formed on a substrate 1 and a gate insulating film is formed thereon.
3 is formed thereon, and a gate electrode 4 is formed thereon. After the interlayer insulating film 5 is formed, the source electrode 6 and the drain electrode 7 are formed and completed. Detailed device structure and process conditions are described in S. Inoue, et al, Asia Display95,
See p339.

In a thin film transistor, a semiconductor film 2
Is formed by depositing on a substrate by any method such as LPCVD, PECVD, and sputtering. Therefore, it is inevitable that the surface has a surface roughness of 8. In particular, when the semiconductor film 2 is crystallized by laser irradiation, the surface roughness 8 is almost always generated. Generally, even after the gate insulating film 3 is formed, the surface roughness 8 exists at the interface between the semiconductor film 2 and the gate insulating film 3.

[0005]

There is a concern that the surface roughness 8 existing at the interface between the semiconductor film 2 and the gate insulating film 3 may hinder carrier conduction of the thin film transistor and reduce the on-current. . Accordingly, an object of the present invention is to suppress the inhibition of carrier conduction and the decrease in on-current due to the surface roughness 8.

[0006]

According to a first aspect of the present invention, there is provided a thin film transistor comprising a semiconductor film and a gate electrode, and a gate insulating film between the semiconductor film and the gate electrode. The thin film transistor is characterized in that the apex angle A of the projection having the surface roughness existing at the interface between the film and the gate insulating film satisfies A> 90 degrees.

[0007] According to this configuration, the surface roughness does not hinder the conduction of carriers, so that the on-current does not decrease.

(2) The present invention according to claim 2 is a thin film transistor comprising a semiconductor film and a gate electrode and a gate insulating film between the semiconductor film and the gate electrode. A width W and a height H of a protrusion having a surface roughness existing at the interface of (1) satisfy (W / 2) / H> tan (90 degrees / 2).

According to this structure, since the surface roughness does not hinder the conduction of the carriers, the on-current does not decrease.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described.

FIG. 2 is a diagram showing the surface roughness existing at the interface between the semiconductor film and the gate insulating film. The apex angle of the protrusion of the surface roughness is A, the width of the protrusion of the surface roughness is W, and the height of the protrusion of the surface roughness is H.

A change in the on-current was obtained by changing W and H by device simulation. The structure of the thin film transistor is as shown in FIGS. n
Channel, self-aligned, channel length 10um, surface roughness
The distance of 8 is 3um. Vd = 8V.Vg = 12V was applied. Here, a polycrystalline thin film transistor crystallized by laser irradiation is assumed. Note that, here, the description is made of the top gate structure, but the same effect can be expected with other structures.

FIG. 3 shows the dependence of the on-current on the apex angle A of the protrusion of the surface roughness. It can be seen that the on-current does not depend on each of the width W and height H of the protrusion of the surface roughness independently, but mainly depends on the vertex angle A of the protrusion of the surface roughness. The on-current rapidly deteriorates when the apex angle A of the protrusion becomes smaller than 90 degrees. Therefore, as set forth in claim 1, by setting A> 90 degrees, a decrease in on-current can be suppressed. This is because the surface roughness 8 has a shape that does not hinder carrier conduction.

In general, the shape of the surface roughness 8 is not sharp as shown in FIG. 2, and it may be difficult to define the apex angle A of the projection. In this case, although mathematically equivalent, (W / 2) / H> tan
(90 degrees / 2), it is possible to suppress a decrease in on-current.

[Brief description of the drawings]

FIG. 1 illustrates a structure of a thin film transistor.

FIG. 2 is a view showing surface roughness existing at an interface between a semiconductor film and a gate insulating film.

FIG. 3 is a diagram showing the dependence of the on-current on the apex angle A of the protrusion of the surface roughness.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor film 3 Gate insulating film 4 Gate electrode 5 Interlayer insulating film 6 Source electrode 7 Drain electrode 8 Surface roughness A Apex angle of projection of surface roughness W Width of projection of surface roughness H Surface roughness Projection height

Claims (2)

[Claims] 1. A thin film transistor comprising: a semiconductor film and a gate electrode; and a gate insulating film between the semiconductor film and the gate electrode; a surface existing at an interface between the semiconductor film and the gate insulating film. A thin film transistor, wherein the apex angle A of the roughness projection satisfies A> 90 degrees. 2. A thin film transistor comprising: a semiconductor film and a gate electrode; and a gate insulating film between the semiconductor film and the gate electrode; a surface existing at an interface between the semiconductor film and the gate insulating film. A thin film transistor characterized in that the width W and the height H of the roughness projection satisfy (W / 2) / H> tan (90 degrees / 2).