JP2000260877A - Layout designing method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a layout designing method, in which by lowering the production cost of a chip to a minimum, the area of a wiring channel is reduced to a minimum, and the chip area of a semiconductor integrated circuit is reduced. SOLUTION: This layout designing method is provided with a step where a dummy pattern is added to a region in which the desired terminal and the desired net of a standard cell constituting a functional circuit block can be connected, a step where information on a connection to the desired terminal and the desired net of the standard cell is added to the dummy pattern a step where a dummy pattern is added when the layout pattern of another net does not exist on the dummy pattern and in which a virtual terminal having information on a connection to the desired net of the functional circuit block is added, a step where when the virtual terminal of the functional circuit block is connected to an interconnection passed on the functional circuit block, a contact cell used to connect the interconnection passed on the functional circuit block to the virtual terminal of the functional circuit block is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 9 is a flow chart of a conventional layout design of a building block system.

In a conventional building block layout, data required for a one-chip layout is input in a data input step 1000, and a floor plan step 1 is executed.
In step 001, the arrangement of the functional circuit blocks and the arrangement positions of the input / output terminals of the functional circuit blocks are determined at the level of one chip. Next, standard cells in a functional block are arranged in a standard cell arranging step 1002, and power supply wiring, schematic wiring, and detailed wiring are performed in a wiring step in a functional circuit block 1003 to complete the layout of the functional block. Next, in a wiring step 1004 between functional circuit blocks, power supply wiring, general wiring and detailed wiring between blocks are performed to complete the layout of one chip, and layout data is output in a data output step 1005.

[0004]

The advantage is that the smaller the layout area of the semiconductor integrated circuit chip, the lower the chip manufacturing cost. In order to reduce the layout area of the chip, it is necessary to minimize the area of the functional circuit block and the wiring channel. In the conventional building block layout, all signal lines, clock lines, power supply lines, and analog lines pass through all or some of the wiring channels between functional circuit blocks before being connected to the terminals of the functional circuit blocks. Even when there are two or more layers that can pass over the block and there is enough space for all the wirings to pass over the block, the wiring remains in the wiring channel.

As shown in the layout of the power supply and ground wiring and the arrangement of the hard block and the soft block according to the conventional method shown in FIG. 8, there is a high possibility that a particularly wide power supply wiring main line remains in all the wiring channels. Since the area cannot be minimized, the layout area of the chip is not minimized.

[0006]

According to the present invention, in a layout design of a semiconductor integrated circuit, a dummy pattern is added to an area where a desired terminal of a standard cell constituting a functional circuit block can be connected to a desired net. Means for adding connection information between a desired terminal of a standard cell and a desired net to the dummy pattern, and the dummy pattern if the layout pattern of another net does not exist on the dummy pattern. Means for adding a virtual terminal as a virtual terminal having connection information with a desired net of a functional circuit block, and connecting a virtual terminal of the functional circuit block and a wiring passing on the functional circuit block A connector for connecting a virtual terminal of the functional circuit block to a wiring passing over the functional circuit block. And means for generating a Takutoseru a layout design method of a semiconductor integrated circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with an example of a power supply wiring which has the greatest influence on a layout area.

FIG. 1 shows a processing flow chart of a layout design method according to an embodiment of the present invention. Data input step 100
Then, physical layout information such as functional circuit blocks and standard cells called hard blocks whose physical layout shape is fixed, physical design rules such as wiring width and wiring interval of each wiring layer, and chip Parameters required for placement and routing, such as specifying the type of wiring layer used in the layout and the wiring direction of each wiring layer, specifying the type of wiring layer used in the functional circuit block and the wiring direction of each wiring layer, A logic-level netlist, which is connection information between equipotential terminals at the chip level and the functional circuit block level of the semiconductor integrated circuit, is input.

In the floor plan step 101, the functional circuit blocks BL1 and BL whose physical shapes are not fixed as shown in the layout diagram of the power supply and ground wiring and the hard and soft blocks according to the present invention in FIG.
The functional circuit blocks BL2, PAD1, PAD2, PAD3, and PAD4 whose physical shapes are fixed to 3 are arranged, and the path of the power supply wiring at the chip level is determined. VDD1 to VDD8 are power supply lines, VSS1 to VSS
8 is a ground wiring.

The paths of the power supply and the ground wiring are BL1, B
Pass any position on L3, BL2, PAD1, PA
D2, PAD3, and PAD4 are set so as to always pass through positions connectable to power supply wiring at the chip level.

In a standard cell arranging step 102, standard cells are arranged according to a netlist of functional circuit blocks and a block size determined by a floor plan.

After arranging the standard cells, a step 103 for adding a dummy pattern is performed in the following procedure. As shown in the path diagram of the power supply and the ground wiring in the functional circuit block according to the present invention in FIG. 3, the power supply wiring defined by the floor plan on the cell of the functional block is indicated by LVDD, and the ground wiring is indicated by LVSS.

In all cells that respectively overlap with LVDD, FIG.
As shown in the virtual terminal arrangement diagram on the VDD terminal on CELL1 added according to the present invention, a vertical and horizontal wiring grid through which the wiring passes through CELL1 is set, and the wiring grid and the VDD are set.
Dummy patterns VDC1 to VDC4 are set at all intersections between D and a wiring pattern having the same potential.

[0014] Similarly, the cells respectively overlapping the LVSS are shown in FIG.
As shown in the virtual terminal arrangement diagram on the VSS terminal on CELL2 added according to the present invention, a vertical and horizontal wiring grid through which wiring passes through CELL2 is set, and the wiring grid and VS
Dummy patterns VSC1 to VSC4 are set at all the intersections between S and the wiring pattern having the same potential.

In step 104 for adding connection information, connection information with VDD is added to the dummy patterns VDC1 to VDC4 to make them virtual terminals of VDD. Similarly, the connection information to VSS is added to the dummy patterns VSC1 to VSC4 to
S is a virtual terminal.

The processing of step 104 is performed in all the cells overlapping the power supply and ground wiring paths.

In the wiring step 105 in the functional circuit block, general wiring and detailed wiring are performed according to the logical net list.
Complete the layout of the functional circuit block.

In the virtual terminal adding step 106, the layout of the completed functional circuit block is searched for the presence or absence of a wiring pattern on the virtual terminal on the standard cell set in 104. Only when no wiring pattern exists on the virtual terminal, the standard The virtual terminal on the cell is a virtual terminal of the functional circuit block. If a wiring pattern exists on the virtual terminal, the virtual terminal on the standard cell is deleted.

VDD on CELL 1 after wiring processing in FIG. 6
The processing method of 106 will be described with reference to the virtual terminal arrangement diagram of FIG. 7 and the virtual terminal arrangement diagram of VSS on CELL 2 after the wiring processing of FIG.

FIG. 6 shows that the vertical lines LV1 and LV2 and the horizontal line LH1 are laid on the cell 1 by the processing of step 105.

VD which is a virtual terminal of VDD of CELL1
When checking for the presence or absence of a wiring pattern on C1 to VDC4, VD
Since no wiring pattern exists only on C2, VDC2 is used as a virtual terminal of VDD of a functional block that can be recognized as a VDD terminal when wiring between functional circuit blocks. VDC1,
Since wiring patterns exist on VDC3 and VDC4, virtual terminals are deleted.

Similarly, FIG.
The vertical wirings LV3 and LV4 and the horizontal wiring LH2 are wired on the second line.

VS which is a virtual terminal of VSS of CELL2
When the presence or absence of a wiring pattern on C1 to VSC4 is checked, VS
Since no wiring pattern exists on C1 and VSC2, V
SC1 and VSC2 are connected to VSS when wiring between functional circuit blocks.
A virtual terminal of VSS of the functional circuit block that can be recognized as a terminal. Since the wiring pattern exists on VSC3 and VSC4, the virtual terminal is deleted.

The processing of 106 is performed in all the cells overlapping the power supply and ground wiring paths.

Next, in connection determination step 107, it is checked whether there is no problem in connection between the functional block, the power supply, and the ground wiring.

When the power supply and ground wiring is connected to the power supply and ground terminals of the functional circuit block, the allowable current amount per contact is determined. Therefore, the allowable current amount is: current allowable amount = allowable amount per contact. It can be obtained by multiplying the current by the number of contacts.

If the amount of current flowing through the power supply and the ground wiring is known, the number of contacts required for the functional circuit block can be obtained by the following formula: number of contacts required for the functional circuit block = current amount / permissible current amount per contact.

If the number of power and ground terminals of the functional circuit block is smaller than the number of contacts required for the functional circuit block, the permissible current per contact <current amount / number of contacts required for the functional circuit block, and one contact As a result, a current exceeding the permissible current flow will flow, and in the worst case, the contact will be broken and electrical connection will be impossible.

If the number of contacts for connecting the power supply and ground wiring to the functional circuit block is sufficiently ensured, step 108 for generating contacts is executed. If the number of contacts for connecting the power supply and ground wiring to the functional circuit block cannot be sufficiently ensured, return to the floor plan and change the block size or the power supply path to 102 to 107
Execute the processing of

In step 108 for generating a contact, a contact enabling connection of the power supply lines VDD1 to VDD8 on the power supply terminals of all the functional circuit blocks overlapping the power supply lines VDD1 to VDD8 shown in FIG. Generate.

Similarly, contacts are formed on the ground terminals and ground virtual terminals of all the functional circuit blocks overlapping with the ground lines VSS1 to VSS8 to enable connection with the ground lines VSS1 to VSS8.

Next, wiring step 10 between functional circuit blocks
At 9, a schematic wiring and a detailed wiring at the chip level are performed to complete the layout of the chip.

When the layout of the chip is completed, the layout result is output in the data output step 110, and the processing ends.

[0034]

As described above, according to the present invention, the wiring of the wiring channel is minimized, and in particular, the area of the wiring channel is minimized by eliminating the main line of the power supply and the ground wiring. As a result, the layout area of the chip is minimized. It is possible to

[Brief description of the drawings]

FIG. 1 is a processing flowchart of a layout design method according to an embodiment of the present invention.

FIG. 2 is a layout diagram of power supply and ground wiring paths, hard blocks, and soft blocks according to the present invention.

FIG. 3 is a path diagram of power supply and ground wiring in a functional block according to the present invention.

FIG. 4 shows VDD on CELL1 added according to the present invention.
Virtual terminal layout on terminals

FIG. 5: VSS on CELL2 added according to the present invention
Virtual terminal layout on terminals

FIG. 6 is a virtual terminal arrangement diagram of VDD on CELL1 after wiring processing;

FIG. 7 is a virtual terminal layout diagram of VSS on CELL2 after wiring processing;

FIG. 8 is a layout diagram of a power supply and a ground wiring, and a hard block and a soft block according to a conventional method

FIG. 9 is a layout diagram of a conventional building block layout design.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 data input step 101 floor plan step 102 standard cell placement step 103 step of adding dummy pattern 104 step of adding connection information 105 wiring step in functional circuit block 106 virtual terminal adding step 107 connection determination step 108 step of generating a contact cell 109 Wiring step between functional circuit blocks 110 Data output step 1000 Data input step 1001 Floor plan step 1002 Standard cell arrangement step 1003 Wiring step within functional circuit block 1004 Wiring step between functional circuit blocks 1005 Data output step PAD1 Physical shape is fixed Functional circuit block PAD2 Functional circuit block PAD with fixed physical shape Functional circuit block with fixed physical shape PAD4 Functional circuit block with fixed physical shape BL1 Functional circuit block with unfixed physical shape BL2 Functional circuit block with fixed physical shape BL3 Physical shape Not fixed VDD1 Chip-level power supply wiring VDD2 Chip-level power supply wiring VDD3 Chip-level power supply wiring VDD4 Chip-level power supply wiring VDD5 Chip-level power supply wiring VDD6 Chip-level power supply wiring VDD7 Chip-level power supply wiring VDD8 Chip-level power supply wiring VSS1 Chip-level ground wiring VSS2 Chip-level ground wiring VSS3 Chip-level ground wiring VSS4 Chip-level ground wiring VSS5 Top-level ground wiring VSS6 Chip-level ground wiring VSS7 Chip-level ground wiring VSS8 Chip-level ground wiring Power supply wiring passing over LVDD BL1 Ground wiring passing over LVSS BL1 CELL 11 Standard cell arranged in functional circuit block Standard cell arranged in CELL 12 function circuit block Standard cell arranged in CELL 13 function circuit block CELL Standard cell arranged in 14 function circuit block CELL Standard cell arranged in 15 function circuit block CELL 16 Standard cell CELL 17 arranged in a functional circuit block Standard cell CELL 21 arranged in a functional circuit block Cell arranged in a functional circuit block 21 Standard cells arranged in a CELL 22 function circuit block Standard cells arranged in a CELL 23 function circuit block Standard cells arranged in a CELL 24 function circuit block Standard cells arranged in a CELL 25 function circuit block Standard cell arranged in CELL 26 function circuit block Standard cell arranged in CELL 27 function circuit block CELL 31 Standard cell arranged in function circuit block CELL 32 Standard cell arranged in function circuit block CELL 33 Standard cell arranged in a functional circuit block CELL 34 Standard cell arranged in a functional circuit block CELL 35 Standard cell arranged in a functional circuit block Standard cell arranged in CELL 36 functional circuit block Standard cell arranged in CELL 37 functional circuit block CELL 41 Standard cell arranged in functional circuit block CELL 42 Standard cell arranged in functional circuit block Standard cell arranged in a functional circuit block CELL 44 Standard cell arranged in a functional circuit block CELL 45 Standard cell arranged in a functional circuit block CELL1 Standard cell having an overlap with LVDD Standard cell having an overlap with LLVSS VDD Standard cell power supply layout pattern VSS Standard cell ground layout pattern IN Standard cell signal input terminal layout pattern OUT OUT Layout pattern of signal output terminal of standard cell VDC1 Virtual terminal of power supply of CELL1 VDC2 Virtual terminal of power supply of CELL1 VDC3 Virtual terminal of power supply of CELL1 VDC4 Virtual terminal of power supply of CELL1 Virtual terminal of power supply of VSC1 CELL2 VSC2 CELL2 of power supply Virtual terminal of power supply Virtual terminal of power supply of VSC3 CELL2 Virtual terminal of power supply of VSC4 CELL2 LH1 Horizontal signal wiring LH2 Horizontal signal wiring LV1 Vertical signal wiring LV2 Vertical signal wiring LV3 Vertical signal wiring LV4 Vertical Direction signal wiring

Claims (2)

[Claims] In a layout design of a semiconductor integrated circuit, a step of adding a dummy pattern to a region in which a desired terminal of a standard cell constituting a functional circuit block can be connected to a desired net; Adding connection information between a desired terminal of the standard cell and a desired net; and, if there is no layout pattern of another net on the dummy pattern, the dummy pattern is connected to a desired net of the functional circuit block. Adding a virtual terminal as a virtual terminal having connection information of the functional circuit block; and connecting a virtual terminal of the functional circuit block to a wiring passing over the functional circuit block. Contact cell for connecting a virtual terminal to a wiring passing over the functional circuit block A layout design method for a semiconductor integrated circuit, comprising the step of generating 2. The layout design of a semiconductor integrated circuit, wherein physical layout information of standard cells and functional circuit blocks constituting the semiconductor integrated circuit, physical design rules, input / output terminals of the functional circuit blocks and standard cells are provided. A data input step of inputting a netlist, which is connection information of input / output terminals of the chip, a floor plan step of determining a layout position and size of chip-level functional circuit blocks and a layout position of input / output terminals, and a standard of functional circuit blocks. A standard cell arranging step of arranging cells; a step of adding a dummy pattern to a region enabling connection between a desired terminal and a desired net of the standard cell constituting the functional circuit block; and Connection information between the desired terminal and the desired net A wiring step in the functional circuit block for wiring in the functional circuit block, and a wiring pattern in the functional circuit block in the functional circuit block. If there is no other net layout pattern on the pattern, the dummy pattern is
Adding a virtual terminal as a virtual terminal having connection information with a desired net of the functional circuit block; wiring of a net passing on the functional circuit block and a virtual terminal of the functional circuit block When overlapped, the connection information of the virtual terminal of the functional circuit block with the net and the connection information of the wiring net are compared, and the virtual terminal of the functional circuit block and the virtual terminal of the functional circuit block pass over the functional circuit block. It is determined whether there is no problem with the connection to the wiring to be connected.If there is a problem with the connection, it is instructed to return to the floor plan step. A connection judging step for connecting the virtual terminal of the functional circuit block to a wiring passing over the functional circuit block. Generating a contact cell for connecting a virtual terminal of the circuit to a wiring passing over the functional circuit block, a wiring step between functional blocks for performing wiring between the functional circuit blocks, and a layout result. A layout design method for a semiconductor integrated circuit having a data output step of outputting.