JP2000259602A - One chip micro computer and its data managing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily investigate the origins of individual chips when a market defect occurs and to realize speedy analysis and response by storing various pieces of information data such as product management information, various information at the time of deciding good products and information peculiar to a machine type in a specified address area allocated to a non-volatile memory. SOLUTION: Various pieces of information data which are referred to at the time of a maintenance processing such as product management information (information on a wafer lot number and a wafer number, for example) on a non-volatile memory 7, various pieces of information (information on the reading current value of a memory cell in a deletion state, which contributes to rewriting, for example) at the time of judging a good product and information peculiar to machine type (information on the reading current of the memory cell in the deletion state for individual purposes, for example) are stored in a specified address area (e) allocated to the non-volatile memory 7. At the time of checking a wafer, information data in the address area (e) is read and therefore the origins of respective chips when the market failure occurs can easily be checked. Then, speedy analysis and response are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer having a built-in non-volatile memory and a data management method thereof, and more particularly to a method for storing various information data such as product management information, various information at the time of non-defective judgment, and model-specific information. By storing the information in a specific address area allocated to the memory, maintenance processing can be facilitated when a failure occurs after the shipment from the market.

[0002]

2. Description of the Related Art A recent one-chip microcomputer shows that, as a nonvolatile memory for storing program data, a nonvolatile memory having a rewriting function such as an EEPROM or a flash EEPROM called a flash memory instead of a mask ROM. The tendency to incorporate is growing. This is an EEPROM or flash EEPROM
This is because a ROM or the like has a feature not found in the mask ROM.
For example, when the function of a one-chip microcomputer is changed, if a mask ROM is used, a new mask must be designed and manufactured. Therefore, there is a problem that a development cost is increased and a development period is lengthened.
In contrast, if an EEPROM or the like is used, new program data can be written using a PROM writer or the like after the old program data is electrically erased, so that development costs can be reduced and the development period can be shortened.

FIG. 2 is a cell structure diagram showing a program state of a general split gate type nonvolatile memory.
1 is a control gate, 2 is a floating gate,
Reference numeral 3 denotes a drain, and 4 denotes a source.

When the nonvolatile memory shown in FIG. 2 is set to the program state, for example, voltages of 2 volts, 0 volt, and 12 volts are applied to the control gate 1, the drain 3, and the source 4, respectively. Then, the capacity between the control gate 1 and the floating gate 2 and the capacity between the floating gate 2 and the source 4 are capacitively coupled (the capacity between the control gate 1 and the floating gate 2 <the capacity between the floating gate 2 and the source 4). Due to the coupling ratio, the floating gate 2 is not actually applied with a voltage, but as a result, is in a state equivalent to receiving a high voltage of, for example, 11 volts.

As a result, a channel through which electrons continue is formed between the drain 3 and the source 4, and hot electrons in the channel are injected into the floating gate 2 via an insulating film (not shown). Is in a negatively charged state. This is the program state of the nonvolatile memory cell.

FIG. 3 is a cell structure diagram showing a read state of a nonvolatile memory in a programmed state, and FIG. 4 is a cell structure diagram showing a read state of a nonvolatile memory which is not in a programmed state (erase state).

When both the nonvolatile memories of FIGS. 3 and 4 are set to the read state, for example, 5 volts, 2 volts are applied to the control gate 1, the drain 3 and the source 4 respectively.
Apply 0 volts. In the case of FIG. 3, since electrons are injected into the floating gate 2, no channel is formed between the drain 3 and the source 4, and the nonvolatile memory cell is turned off. On the other hand, in the case of FIG. 4, since no electrons exist in the floating gate 2, a channel is formed between the drain 3 and the source 4, and the nonvolatile memory cell is turned on.

FIG. 5 is a cell structure diagram showing an erased state of the nonvolatile memory.
0 volt is applied to volts, drain 3 and source 4. Then, the electrons injected into the floating gate 2 move to the control gate 1 via the insulating film. However, since the drain 3 and the source 4 have the same potential, no channel is formed. This is the erased state of the nonvolatile memory cell.

FIG. 6 shows a nonvolatile memory cell (2 as an example).
FIG. 5 is a block diagram for outputting a logical value “0” or “1” according to a program state of (a bit), 5 is a nonvolatile memory cell, 6 is a sense amplifier, and 6 is a sense amplifier.
Is a voltage value of 0 volt (logical value “0”) or a voltage value of 5 volt (logical value “1”) according to the comparison result between the output current (read current) of the nonvolatile memory cell 5 and the reference current Iref.
Is output.

When the nonvolatile memory cell 5 is in the programmed state as shown in FIG. 3, the sense amplifier 6 sets the output current (read current) of the nonvolatile memory cell 5 to the reference current Iref.
When it is smaller, a logical value “0” is output. On the other hand, when the nonvolatile memory cell 5 is not in the programmed state as shown in FIG. 4, the sense amplifier 6 sets the output current (read current) of the nonvolatile memory cell 5 to the reference current Ir.
It detects that it is larger than ef and outputs a logical value “1”. Conventionally, when the memory cell 5 is not in the programmed state (erased state), the reference current is equal to the initial value of 100 μm.
At the time point when the voltage drops to 30 μA, which is 30% of A, the operating life of the memory cell was determined as the limit point of the number of times of data rewriting.

As described above, a fixed voltage is applied to the control gate 1, the drain 3, and the source 4 for a fixed time according to the program state, the read state, and the erase state of the nonvolatile memory.

FIG. 7 is a diagram showing a layout of the one-chip microcomputer. Reference numeral 20 denotes a microcomputer-side core circuit block, and reference numeral 21 denotes a nonvolatile memory-side core circuit block. A large number of pads 22 are arranged on four sides of a peripheral portion surrounding the core circuit block 20 on the microcomputer side and the core circuit block 21 on the non-volatile memory side.

Hereinafter, the wafer check by the LSI tester in the inspection before shipment of the one-chip microcomputer will be described. Since the wafer check process is performed by a conventionally well-known procedure, it will be briefly described.

First, in a first measurement step, data determination in a nonvolatile memory is performed using a logic tester. Subsequently, after passing through a baking step for a data retention accelerated test,
In the measurement step, the data holding state of the above-described nonvolatile memory is determined using a logic tester, and the function of the microcomputer is determined.

[0015]

The above-mentioned one-chip microcomputer is selected in a wafer state as described above.
The test is performed once or twice and in a finished product state about once or three times.
Basically, work is performed on a wafer lot basis.

However, as described above, since work is performed on a wafer lot basis, it is not possible to quickly respond to maintenance processing when a defect occurs after shipment from the market or analysis for a decrease in yield. That is, in the conventional method, only information from which wafer lot can be determined, and parameters and work history in the previous process can be analyzed only in wafer lot units. It was taking time. Furthermore, failures in the wafer surface could not be analyzed.

In particular, rewriting (data writing / writing)
In applications where the number of times of erasure is required, sampling determination is performed because rewriting cannot be checked for all numbers. However, for example, the result of one or two wafers is used to determine the mother body. There was also waste such as discarding even individual products.

Furthermore, when shipping chip products for card applications, which are expected to increase in the market in the future, it is expected that it will be very difficult to analyze the lot history and characteristics when the market failure occurs. .

In addition, basic data on yield / yield improvement activities in the production line could not be sufficiently collected.

Accordingly, an object of the present invention is to provide a one-chip microcomputer and a data management method for the same which facilitate maintenance processing when a market failure occurs.

[0021]

Therefore, according to the present invention, various information data E such as product management information, various information at the time of non-defective product determination, and model-specific information are stored in a specific address area e allocated to the nonvolatile memory 7. In this case, it is easy to investigate the chip characteristics when a defect occurs after shipment from the market, and it is possible to perform a quick maintenance process.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a one-chip microcomputer and a data management method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main configuration of a one-chip microcomputer according to the present invention.

In FIG. 1, reference numeral 7 denotes a nonvolatile memory (for example, a flash EEPROM, also called an EEPROM or a flash memory), which can electrically erase data and repeatedly write and read data, and controls the operation of a one-chip microcomputer. Is mainly stored.

Memory cell 5 constituting nonvolatile memory 7
In general, data writing, reading, and erasing are performed in the states shown in FIGS. Control data A for controlling the magnitude or time of the write voltage of the nonvolatile memory 7 and the erase voltage of the nonvolatile memory 7 are respectively stored in the specific address areas a, b, c, d, and e of the nonvolatile memory 7. Control data B for controlling the magnitude or time of the read voltage, control data C for controlling the magnitude or time of the read voltage, and the reference voltage Vref (reference current Iref Control data D for controlling the size of (corresponding to) and various information data E described later are written in advance.

The feature of the one-chip microcomputer of the present invention is that the nonvolatile memory 7 stores product management information (for example, various information such as a wafer lot number, a wafer number, and coordinates of the chip) on the nonvolatile memory 7. ) And various information at the time of non-defective judgment (for example, various information such as a read current value of a memory cell in an erased state which contributes to rewriting and the like).
And model-specific information (for example, various information such as a read current value of a memory cell in an erased state for various applications (applications requiring the number of rewrites or applications not requiring the number of rewrites))
Various information data E referred to during maintenance processing such as
Is allocated to the non-volatile memory for storing the specific address area e. By storing the information data E in the address area e at the time of the wafer check, it becomes possible to quickly cope with a maintenance process at the time of occurrence of a defect after shipment from the market and an analysis at the time of a decrease in yield. That is, conventionally, since work was performed on a wafer lot basis, only information from which wafer lot was discriminated could be determined. However, according to the present invention, the feature investigation of each chip is easy, and quick analysis and response are possible.

In particular, rewriting (data writing / writing)
Even in applications where erasures are required, based on data that correlates to the ability to write and erase data,
Shipment determination can be made in chip units instead of wafer lot determination as in the conventional case, and waste such as discarding non-defective products can be eliminated.

Reference numeral 8 denotes a program counter, which addresses the nonvolatile memory 7. An instruction register 9 holds data read from the nonvolatile memory 7. An instruction decoder 10 decodes the data held in the instruction register 9 and outputs control signals for executing various operations of the one-chip microcomputer. 11A, 11B, and 11C are registers, and the addresses a, b, and
The control data A, B, and C of FIG. The address d of the nonvolatile memory 7
Is control data for reference at the time of reading, and the control data D is directly connected to the reference voltage section of the sense amplifier 6, and the reference voltage Vref is set at the same time when the one-chip microcomputer is initialized. It has become. The erasing operation of the non-volatile memory 7 is performed in units of one page (for example, 128 bytes), and the control data A, B, and C of the specific address areas a, b, c, d, and e are controlled.
There is no inconvenience that C and D and various information data E are collectively erased simultaneously with the erasing operation.

As described above, according to the present invention, in the nonvolatile memory 7, various information data to be referred to during maintenance processing such as product management information relating to the nonvolatile memory 7, various information at the time of non-defective product determination, and model-specific information. By allocating the specific address area e for storing E to the non-volatile memory, maintenance processing at the time of failure occurrence after market shipment and analysis at the time of a decrease in yield can be performed more quickly than before. become.

In particular, rewriting (data writing / writing)
In applications where the number of times of erasure is required, it is possible to make a shipment determination in chip units based on data correlating to the ability to write and erase data, and it is possible to reduce waste such as discarding non-defective products as in the past. .

Further, when shipping chip products for card use, which is expected to increase in the market in the future, it becomes very easy to analyze the lot history and characteristics when a market failure occurs.

In addition, it becomes possible to collect basic data of a yield / yield improvement activity in a production line.

Further, since the chip storing the above various information is a good product, it is written in the specific address area e at the first time of the wafer check, which is performed twice by the conventional one-chip microcomputer. By checking the specific address area e at the beginning of the second measurement, the measurement time for the entire wafer can be reduced.

The present invention is not limited to the above-described embodiment, but can be modified in various ways. For example, a specific address area e for storing various information data E in the nonvolatile memory 7 can be used. For example, various settings may be made in accordance with the specifications of each model, such as for each memory cell array, for each byte, for each page, and for each sector (for example, 256 bytes).

[0035]

According to the present invention, various kinds of information data such as product management information related to a nonvolatile memory, various kinds of information at the time of non-defective judgment and model-specific information are stored in a specific area allocated to the nonvolatile memory. By doing so, it becomes easy to investigate the characteristics of each chip when a market failure occurs, and quick analysis and response can be made.

Also, based on data correlating to the ability to write / erase data, it is possible to make a shipment decision in chip units instead of a wafer lot decision as in the prior art, and to eliminate waste such as discarding non-defective products. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a one-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is a cell structure diagram showing a programmed state of a nonvolatile memory.

FIG. 3 is a cell structure diagram showing a read state of the nonvolatile memory in a programmed state.

FIG. 4 is a cell structure diagram showing a read state of a nonvolatile memory which is not in a program state.

FIG. 5 is a cell structure diagram showing an erased state of a nonvolatile memory.

FIG. 6 is a block diagram showing a sense amplifier portion of the nonvolatile memory.

FIG. 7 is a diagram showing a layout of a one-chip microcomputer.

[Explanation of symbols]

 7 Non-volatile memory e Specific address area 8 Program counter 9 Instruction register 10 Instruction decoder 11A register 11B register 11C register 13 Data bus

Claims (4)

[Claims] 1. A one-chip microcomputer having a built-in nonvolatile memory, wherein a specific address area for storing various information data related to the nonvolatile memory is assigned to the nonvolatile memory. . 2. The one-chip microcomputer according to claim 1, wherein the various information data is product management information, various information at the time of non-defective product determination, and model-specific information. 3. A data management method for a one-chip microcomputer having a built-in nonvolatile memory, wherein various information data relating to the nonvolatile memory is stored in a specific address area assigned to the nonvolatile memory. A data management method for a one-chip microcomputer. 4. The data management method for a one-chip microcomputer according to claim 3, wherein the various information data is product management information, various information at the time of non-defective judgment, and model-specific information.