JP2000259596A - Multiprocessor system and consistency maintaining method for data for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of message by reducing the latency of load access in a loosely coupled multiprocessor system. SOLUTION: Concerning the multiprocessor system composed of plural nodes PE0 to PEn-1 mutually connected through a mutual coupling network, plural nodes PE0 to PEn-1 are respectively provided with a main memory 30 for storing data, a cache memory 21 capable of access at higher speed than the main memory 30 for storing one part of data stored in the main memory 30 provided in any one of plural nodes PE0- to PEn-1, a processor 20 for issuing the access request of data and a consistency maintenance control part 16 for holding node information stored in the cache memory 21 concerning the state and copy of data stored in the main memory 30 and investigating the presence/absence of the effective copy concerning the data of a relevant address in the cache memory 21 when load and store access is performed from the processor 20 to the data of the prescribed address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loosely-coupled multiprocessor system, and more particularly to a multiprocessor system for maintaining data coherency between a main memory and a cache memory in such a multiprocessor system. The present invention relates to a method for maintaining data consistency in a multiprocessor system.

[0002]

2. Description of the Related Art A technique for maintaining data consistency between a cache memory and a main memory in a conventional loosely-coupled multiprocessor system is described in “The Director.
y-Based Cache Coherence Protocol for the DAS
H Multiprocessor ”, Daniel Lenoski, James Laudo
n, Kourosh Gharachorloo, Anoop Gupta and Joh
n Hennessy, In Proceedings of 17th Internatio
nal Symposium on Computer Architecture, p148-15
9, 1990).

[0003] Loose coupling refers to coupling having a small coupling coefficient. On the other hand, a coupling having a large coupling coefficient is called a tight coupling.

FIG. 15 is a block diagram showing a configuration of such a conventional multiprocessor system 1 '.

As shown in FIG. 15, this multiprocessor system 1 'includes a plurality of nodes PE0 to PEn-1.
And an interconnection network 10 'for connecting each node.

Each node (only PEi is shown in FIG. 15) is provided with a processor 2 for performing operations, memory access, and the like.
0 ', a main memory 30' for holding data, a cache memory 21 'that can be accessed faster than the main memory 30' for which the processor 20 'temporarily holds data,
A consistency maintaining control unit 55 'for maintaining data consistency between the main memory 30' and the cache memory 21 '(including those of other nodes).

FIG. 16A is a diagram showing a state in which a copy of data exists in the main memory 30 'of a plurality of nodes. FIG. 16B shows a state in which data is copied only in the main memory 30' of one node. FIG. 11 is a diagram showing a state in which a copy exists.

The coherency control unit 55 'holds the contents of the cache memory 21', and the cache memory 21 'stores the status of data stored in the main memory 30' and a copy of the data in the cache memory 21 '. Holds the node information (hereinafter referred to as holding node information). The state of the data is "C",
There are two "M". "C" indicates a state in which data copies exist in the cache memories 21 'of a plurality of nodes, as shown in FIG. At this time, the copy of the cache memory 21 'and the data value of the main memory 30' are the same. “M” is 1 as shown in FIG.
This represents a state in which only one node's cache memory 21 'holds a copy of data. At this time, the value of the copy in the cache memory 21 'is different from the value of the data in the main memory 30', and the value of the copy in the cache memory 21 'is the latest value.

FIG. 17A is a diagram showing a state in which valid data in which consistency is maintained does not exist in the cache memories 21 'of a plurality of nodes. FIG. 17B shows a valid copy of data. FIG. 17C shows a state where there is a possibility that valid data may also exist in the cache memory 21 ′ of another node. FIG. 17C shows that a valid copy of data is stored only in one node. It is a diagram showing a state in which a valid copy does not exist in the cache memory 21 'of another node, and the data of the main memory 30' and the data of the cache memory 21 'are different.

[0010] The coherence maintenance control unit 55 'holds the state of data stored in the cache memory 21' and the tag address of the data. There are three data states, "I", "S", and "D". "I" refers to Figure 1
As shown in FIG. 7 (a), there is no valid copy of data in which consistency is maintained. "S" is shown in FIG.
As shown in (b), a valid copy of the data exists,
In addition, there is a possibility that a valid copy may exist in the cache memory 21 'of another node. “D” indicates that, as shown in FIG. 17C, valid copies of data exist in only one node in the cache memories 21 ′ of a plurality of nodes, and valid copies exist in the cache memories 21 ′ of other nodes. There is no copy and the data value is different from the data value in the main memory 30 '.

Here, the tag address indicates which address data is.

The interconnection network 10 'is a network for delivering messages exchanged between nodes.

Hereinafter, when the processor 20 'loads or stores data at a predetermined address, the data consistency between the main memory 30' and the cache memory 21 'in the multiprocessor system 1' will be described. The operation for maintaining will be described with reference to FIG.

First, the processor 20 'of the node PE1
The operation when load access is performed will be described.

The coherence controller 55 'checks whether a valid copy of the data at the corresponding address also exists in the cache memory 21'. If a valid copy exists in the cache memory 21 ', that is, if the state is "S" or "D", the consistency control unit 55'
Responds to the processor by passing the data read from the cache memory 21 'to the processor 50', and ends the process.

On the other hand, if there is no valid copy in the cache memory 21 ', that is, if the state is "I", the node holding the data at the corresponding address,
For example, the data read request message is transmitted to the node PEh via the interconnection network 10 '.

Node P receiving read request message
The Eh consistency maintenance control unit 55 ′ stores the latest value of the data at the corresponding address in the main memory 3 of the node PEh.
Check if it is at 0 '. If the latest value of the data at the corresponding address exists in the main memory 30 ', that is, if the state is "C", the node P
The data stored in the main memory 30 'is transmitted to E1 via the interconnection network 10' via the interconnection network 10 ', and the node PE1 is added to the holding node information.

The consistency maintaining control unit 55 'of the node PE1 receiving the data from the node PEh
The received data is passed to 0 ', and the data is copied to the cache memory 21'. Further, the state of the data in the cache memory 21 ′ is “S”.

On the other hand, in the node PEh receiving the read request message, if the latest value of the data of the corresponding address does not exist in the main memory 30 ', that is, if the state is "M", the holding node information , A read request message is sent to the node holding the latest data, for example, the node PEr, to the interconnection network 10 ′.
To send over.

Node P receiving read request message
The Er consistency maintenance control unit 55 ′
It is checked whether or not there is data whose state is "D" in 1 '. When the data having the state “D” exists in the cache memory 21 ′, the data stored in the cache memory 21 ′ is transferred to the node PE1 via the interconnection network 10 ′.
And a write-back request message to which the data stored in the cache memory 21 'is added to the node PEh via the interconnection network 10'. Further, the state of the data in the cache memory 21 'is changed to "S".
Update to

Node P receiving the write back request message
The Eh consistency maintenance control unit 55 'updates the data in the main memory 30' with the data added to the write-back request message. Further, the state of the data in the main memory 30 'is updated to "C", and the node P is added to the holding node information.
Add E1.

On the other hand, in the node PEr that has received the read request message, if there is no data with the state “D” in the cache memory 21 ′, a Nak (negative acknowledgment) message is sent to the node PEr via the interconnection network 10 ′. PE
Send to 1.

Node PE receiving Nak message
The one consistency maintenance control unit 55 'transmits a read request message to the node PEh again. Hereinafter, the node PE1
Is transmitted to the processor PE2 of the node PE1.
The same process is repeated until data is passed to 0 '.

Next, the processor 50 'of the node PE1
However, the operation when a store access is performed will be described.

The coherence controller 55 'checks whether the only copy in the system for the data at the corresponding address exists in the cache memory 21'.
If a valid copy exists in the cache memory 21 ', that is, if the state is "D", the data in the cache memory 21' is updated, the access completion is notified to the processor 50 ', and the processing is terminated.

When the only copy does not exist in the cache memory 21 ', that is, when the state is "I" or "S", the consistency maintaining control unit 55' of the node PE1 holds the data of the corresponding address. The exclusive read request message is transmitted to the current node, for example, the node PEh, via the interconnection network 10 '.

The consistency maintaining control unit 55 'of the node PEh receiving the exclusive read request message checks whether or not the latest value of the data of the corresponding address exists in the main memory 30' of the node PEh. If the latest value of the data at the corresponding address exists in the main memory 30 ', that is, if the state is "C", the node PE
1 transmits data stored in the main memory 30 'via the interconnection network 10' via the interconnection network 10 '.

When a node other than the node PE1 holds a copy of the data in the cache memory 21 ', all nodes other than the node PE1 where the copy of the data exists (hereinafter referred to as node PEk) are invalidated. The request message is transmitted via the interconnection network 10 '. Further, the state of the data in the main memory 30 'is updated to "M", and the holding node information is set to only the node PE1. In addition,
The number of nodes PEk that transmitted the invalidation request message is added to the data transmitted to the node PE1.

Node PEk receiving invalidation request message
Of the cache memory 21 ′
Is updated to "I", and an Ack (acknowledge) message is transmitted to the node PE via the interconnection network 10 '.
Send to 1.

The consistency maintaining control unit 55 'of the node PE1 receiving the data from the node PEh copies the data to the cache memory 21'. It also waits for reception of Ack messages for the number of nodes PEk added to the data. When the Ack messages for the number of the nodes PEk are received, the cache memory 2
1 'is updated to the data of the store access performed by the processor 20'. Further, the state of the data in the cache memory 21 is updated to “D”, the access completion is notified to the processor 20 ′, and the processing is terminated.

On the other hand, in the node PEh receiving the exclusive read request message, if the latest value of the data at the corresponding address does not exist in the main memory 30 ', that is, if the state is "M", the holding node information , The node holding the latest data, for example, the node P
An exclusive read request message is transmitted to Er via the interconnection network 10.

The consistency maintenance control unit 55 'of the node PEr that has received the exclusive read request message checks whether or not the data having the state "D" exists in the cache memory 21'. If there is no data in the state “D” in the cache memory 21 ′,
Send k messages.

Node PE receiving Nak message
The one consistency maintenance control unit 55 ′ transmits an exclusive read request message to the node PEh again. Or later,
A similar process is repeated.

On the other hand, in the node PEr that has received the exclusive read request message, if data having the state “D” exists in the cache memory 21 ′, the data stored in the cache memory 21 is transferred to the interconnection network 10 ′. To the node PE1. In addition, the holding node update request message is transmitted to the node
At the same time, the state of the data in the cache memory 21 ′ is updated to “I”.

The consistency maintaining control unit 55 'of the node PEh that has received the holding node update request message
Assuming that only the node PE1 holds the data of 0 ', the holding node information is updated, and the Ack message is transmitted to the node PE1 via the interconnection network 10'.

The consistency maintaining control unit 55 of the node PE1 receiving the data from the node PEr copies the data to the cache memory 21 '. Also, the node PEh
Wait for receiving the Ack message from. Node P
Upon receiving the Ack message from Eh, the data in the cache memory 21 'is updated to the data of the store access performed by the processor 20'. Further, the state of the data in the cache memory 21 'is updated to "D",
The process is terminated by responding to the processor 20 'with the completion of the access.

[0037]

However, the conventional multiprocessor system 1 'has a processor 20'.
Cache memory 21 'accessed by reading
However, when a cache miss occurs in which no data exists, it takes a long time until data is responded to the processor 20 from the cache memory 21 '. Also, when the latest data does not exist in the main memory 30 ', it is necessary to transfer the request to the node holding the latest data, and as compared with the case where the latest data exists in the main memory 30', Processor 20 '
However, there is a problem that the time from when a request is issued to when data is received becomes long.

The present invention has been made in consideration of the above-described problems of the conventional technology, and has been made in consideration of the above-described problems, and has been made in consideration of the above-described problems. An object of the present invention is to provide a multiprocessor system that provides a control method and a method for maintaining data consistency in the multiprocessor system.

[0039]

According to the present invention, there is provided a multiprocessor system comprising a plurality of nodes connected to each other via an interconnection network. The nodes each store a main memory in which data is stored, and a part of the data stored in the main memory included in any of the plurality of nodes.
A cache memory that can be accessed faster than the main memory, a processor that issues data access requests, manages the state of data in the main memory in the system, and manages the copy state of data in the cache memory When the processor performs load and store access to data at a predetermined address, the processor exchanges messages between the nodes PEi according to the memory access, and changes the state of the messages and transfers data. A consistency maintenance control unit, wherein the consistency maintenance control unit stores a tag memory in which a state of data stored in the cache memory is stored and a state of data stored in the main memory. Directory memory, access request from processor, home access control unit provided for multiple nodes A local access control unit that receives requests and responses to be issued, performs necessary processing for maintaining consistency in cache memory and tag memory, and responds to access requests to processors, and multiple nodes Home access control unit that receives requests and responses issued by the local access control unit, performs necessary processing on the main memory and directory memory to maintain consistency, and issues requests and responses to the local access control unit. And a request management table having entries corresponding to the maximum number of memory accesses that can be issued simultaneously by the processor, and a write-back that writes to a shared block and stores the block occupied in the cache memory And a block selecting means.

Further, the write-back block selection means is stored in the address registration means for registering the address designated by the local access means, the address holding means for holding a plurality of addresses registered by the address registration means, and the address storage means. A write-back requesting means for selecting one of the plurality of addresses and outputting the selected address to the local access control unit, and requesting a data write-back; and an entry selected by the write-back requesting means according to the instruction of the local access control unit. And an address deleting unit for deleting the address.

Further, the local access control unit reads the block stored in the write-back block selection means from the cache memory, issues a write-back request to the data to the home access control unit, and outputs the data issued by the local access control unit. Receiving a write-back request writes the data back to the main memory.

Further, the local access control unit receives the data write request access to the processor, issues a write request to the home access control unit, receives the write request, and determines whether the data is shared by a plurality of nodes. Judge whether the data is in the shared state from the state of the data held in the directory memory indicating
The result of the determination is added to the response issued to the local access control unit, and a response is returned to the local access control unit. Upon receiving the response, the local access control unit determines whether or not the plurality of nodes are in a shared state based on the information. It is characterized in that the presence or absence of registration in the block is determined by the write-back block selecting means.

Also, the home access control unit has a threshold value for limiting the number of write-backs allowed, and when a write request is received from the local access control unit, the home access control unit actually shares blocks based on the information. It is characterized by judging whether or not there is.

Further, the home access control unit has a threshold value for limiting the number of write-backs allowed, and upon receiving a write request from the local access control unit, based on the threshold value and the information held in the directory memory. It is characterized in that it is determined whether or not a block is actually in a shared state.

In addition, the directory memory has the number of times of rewriting and the information which can specify the node if there is only one node actually holding the block even if the data is in a shared state. It is characterized by the following.

A multiprocessor system comprising a plurality of nodes connected to each other via an interconnection network, wherein each of the plurality of nodes includes a main memory for storing data and one of the plurality of nodes A cache memory in which part of the data stored in the main memory is stored, and which can be accessed at a higher speed than the main memory, a processor that issues a data access request, and the data in the main memory are It determines what state it is in, manages the state of copying data in the cache memory, and when the processor performs load and store access to data at a predetermined address, the node PEi Consistency with the ability to exchange messages, change their state, and transfer data And a coherence control unit, wherein the tag memory in which the state of data stored in the cache memory is stored, an access request from the processor, and a home access control unit provided in a plurality of nodes. A local access control unit that receives requests and responses to be issued, performs necessary processing for maintaining consistency in cache memory and tag memory, and responds to access requests to processors, and multiple nodes Home access control unit that receives requests and responses issued by the local access control unit, performs necessary processing on the main memory and directory memory to maintain consistency, and issues requests and responses to the local access control unit. And a request management table having entries corresponding to the maximum number of memory accesses that can be issued simultaneously by the processor. When, characterized by comprising a write-back block selecting means for storing the blocks had to be dedicated to the cache memory writes to blocks that share.

Further, the local access control unit and the home access control unit included in the consistency maintenance control unit are realized by a processor executing a processing program stored in a main memory.

The local access control unit and the home access control unit included in the coherence maintenance control unit are realized by a dedicated sub-processor provided separately from the processor executing a program stored in the main memory. It is characterized by being performed.

The local access control unit and the home access control unit included in the coherence maintaining control unit are each provided with dedicated hardware configured according to dedicated logic for realizing the function of the module. It is characterized by.

By adopting the above-described configuration, even if the processor of the node writes data to the block of the main memory of the shared node and occupies the cache memory of the node, the writing of the node can be performed. The return block selecting means and the local access control unit operate to write back the exclusive block to the main memory of the node. Accordingly, when a processor of a node other than the node performs load access and there is no block in the cache memory, the block can be read from the main memory of the node, so that the load access latency can be reduced.

The directory memory has information indicating whether or not it is shared, and whether or not the response message transmitted by the home access control unit, which has received the write request, to the node which has issued the request does not have to be shared. Since the write-back block selecting means determines whether or not the block is to be the target of the write-back block selected by the write-back block selecting means, the write-back is not performed for the blocks not shared.

Further, in the case where the number of times of rewriting has been received and the number of nodes that actually hold the block is one even in the state indicating that the block is shared, information that can specify the node is stored in the directory memory. And a threshold value that determines how many times the home access control unit allows write-back, so that the home access control unit that has received the write request confirms that the state of the block is shared. However, if only the node that issued the write request holds the block and the threshold matches the number of times that the write-back has been performed, it is shared in the response message sent to the node that issued the request. This is done by having information indicating that there is no data, and excluding it from the target of the write-back block selecting means. As a result, it is detected that the block that has been shared is no longer shared with the passage of time, and unnecessary writing back is prevented, so that it is possible to prevent an increase in messages due to writing back.

[0053]

Next, embodiments of the present invention will be described with reference to the drawings.

In a multiprocessor system having a cache memory, when a load / store access request to the main memory is issued from a processor of a certain node, the cache memory is first referred to and the requested data exists in the cache memory. The data is immediately transferred to the processor. If the data does not exist in the cache memory, an appropriately sized block containing the requested data is read (loaded) from the main memory and stored in the cache memory.

On the other hand, when the request of the processor is a write (store), if the data exists in the cache memory, not only the contents of the cache memory but also the main memory is rewritten at the same time, and the main memory and the cache are rewritten. The store-through method (or write-through or store-immediate method), which always stores the latest data in both memories, and the temporary rewrite of only the contents of the cache memory, and the main memory when reassigning the blocks of the cache memory Store back (or write back, swap method).

When the latter store-back method is adopted,
Since only the contents of the cache memory are rewritten and then written back to the main memory, the contents of the main memory do not match the contents of the cache memory, and coherency (maintaining data consistency) may not be maintained. is there. This embodiment is intended to maintain the consistency of the data in the main memory and the cache memory.

FIG. 1 is a block diagram showing the configuration of a loosely-coupled multiprocessor system 1 according to the first embodiment of the present invention.

As shown in FIG. 1, the multiprocessor system 1 of this embodiment has a plurality of nodes PE0 to PEn-1.
And an interconnection network 10 that connects the nodes and distributes messages exchanged between the nodes. In this embodiment, the number of nodes is set to n = 1024.

FIG. 2 shows a node PEi (i = i = n) shown in FIG.
FIG. 2 is a block diagram showing an internal configuration of 0-n-1).

As shown in FIG. 2, the nodes PEi (i = 0
To n-1) are the processor 20 and the main memory 3 respectively.
0, the cache memory 21, and the coherence control unit 16
And

When a memory access is performed, the processor 20 outputs information on the memory access, in this case, information such as the type of access (load or store), address, data, and the like. The processor 20 confirms that the memory access has been processed outside the processor 20 by receiving data if the memory access is a load access and receiving a completion signal if the memory access is a store access. Processor 20 may issue the next memory access before confirming that the previous memory access was processed externally. Therefore, an id is added to each memory access, and the id is output together with the type of access, the address, the data, and the type of the cache algorithm. This id is also added to the response to the processor 20 to identify which memory access the response is to.

Incidentally, the load means the cache memory 2
The reading of data from No. 1 and the storing are writing of data to the cache memory 21.

Here, the type of access is represented by 1 bit, "0" represents load, and "1" represents store access. The address is 40 bits and the data is 6 bits.
It is assumed that it is composed of 4 bits. The processor 20
It is assumed that a maximum of four memory accesses can be issued simultaneously and are distinguished by a 2-bit id. In the following description, the least significant bit of the address is the 0th bit,
The most significant bit is the 39th bit. The main memory 3
0 is assumed to be 64 bits width × 2M entries = 512 Mbytes (1M = 1024 × 1024).

The address output by the processor 20 indicates which node PEi is the data stored in the main memory 30 by its upper bits, and the offset in the main memory 30 by its lower bits. Here, processor 2
0 of the 40 bits of the output address, the upper 10 bits from the 39th bit to the 30th bit are which node P
It indicates whether the data is Ei data of the main memory 30, and the lower 30 bits from the 29th bit to the 0th bit are offsets in each main memory 30.

The cache memory 21 is composed of a smaller but faster memory than the main memory 30. Thereby, when the data exists in the cache memory 21,
It is possible to quickly respond to the memory access of the processor 20 and shorten the time required for the memory access. The cache memory 21 has a 64-bit width ×
It is assumed that 128K entries = 1 Mbytes (1K = 1024). Also, the cache memory 21 and the main memory 30
Is transferred in a fixed size called a block (hereinafter, referred to as 128 bytes).

In the multiprocessor system 1, a copy of data in the main memory 30 is transferred to a plurality of nodes PEi.
May exist in the cache memory 21. For this reason, control for maintaining data consistency between the copy and the data in the main memory 30 is required. The coherence maintenance control unit 16 controls such coherence maintenance, and manages a copy state of data in the cache memory 21 and a state of data in the main memory in the system. The consistency maintaining control unit 16 has a function of exchanging messages between the nodes PEi according to memory access, changing their states, and transferring data. The configuration of the consistency maintaining control unit 16 will be described later in more detail.

The interconnection network 10 shown in FIG. 1 has a node PEi based on routing information contained in a message.
Has the function of delivering a message from a certain node PEi. Here, it is assumed that the destination node number is necessary and sufficient information as the routing information. It is assumed that there is one path from a certain node to a certain node, and no overtaking occurs between messages passing through the same path. However, if either the transmitting node or the receiving node is different, the order of arrival between messages is not guaranteed.

Next, the node PE is connected via the interconnection network 10.
The message exchanged between i will be described.

FIG. 3A is a diagram showing a request message transmitted from the node PEi having accessed the memory to the node PEi holding the data in the main memory 30.
FIG. 3B shows that a copy of the data is transferred from the node PEi holding the data in the main memory 30 to the cache memory 21.
FIG. 3C shows a request message transmitted to the node PEi holding the data in the cache memory 21 to the node PEi holding the data in the main memory 30. FIG. 3D is a diagram showing a report message to be sent.
It is a figure which shows the memory access completion message transmitted from the node PEi holding data to 0 to the node PEi which performed memory access.

The messages include “BlkRdSh” and “BlkRdSh”.
lkRdEx ”,“ Upgrade ”,“ BlkW
r, RpBack, Ack, AckDat
a "," IntvSh "," IntvEx "," In
v "," CmpDatSh "," CmpDatEx ",
15 of "CmpSh", "CmpEx", "NCmp"
There are different types of messages. These messages are a group of block sharing / exclusive read / write messages.

Of these, "BlkRdSh" and "BlkRdSh"
RdEx "," Upgrade "," BlkWr ",
The five types of messages of “RpBack” are shown in FIG.
As shown in FIG.
Is a request message transmitted to the node PEi that holds data in the main memory 30.

The BlkRdSh message is a block sharing read request message, the BlkRdEx message is a block exclusive read message, the Upgrade message is an ownership acquisition request message, and the BlkW message.
The r and RpBack messages are block write request messages.

"IntvSh", "IntvEx",
As shown in FIG. 3B, the three types of messages of “Inv” are stored in the node PEi that holds data in the main memory 30.
Is a request message transmitted to the node PEi that holds a copy of the data in the cache memory 21 from the server.
These messages are BlkRdSh, BlkRdE
x, a request message to the cache memory 21 of another node PEi derived from the Upgrade message.

The IntvSh message is a shared read request message, the IntvEx message is an exclusive read request message, and the Inv is an invalidation request message.

As shown in FIG. 3C, two types of messages “Ack” and “AckData” hold data in the main memory 30 from the node PEi that holds a copy of the data in the main memory in the cache memory 21. Node P
This is a report message sent to Ei. Ack, Ac
The kData message is IntvSh, IntvE
This is a response message to the x, Inv message.

The Ack message is a response, AckData
The message is a response message with data.

"CmpDatSh", "CmpDatE"
x ”,“ CmpSh ”,“ CmpEx ”,“ NCmp ”
As shown in FIG. 3D, the five types of messages are memory access completion response messages transmitted from the node PEi that holds data in the main memory 30 to the node PEi that has performed the memory access.

The CmpDatSh message is BlkRD
Shared response message for Sh message, CmpD
The atEx message is an exclusive response message to the BlkRdEx message, and the NCmp message is a BlkR
This is an incomplete response message to the DSh message and the BlkRdEx message.

FIG. 5 (a) shows the structure of a message with block data, and FIG. 5 (b) shows the structure of a basic message.

Next, the structure of each message described above will be described with reference to FIGS. 3 (a), (b), (c), (d) and FIG.
This will be described with reference to FIGS.

Messages are classified into basic messages and messages with block data. "BlkRdS
h "," BlkRdEx "," Upgrade "," A
ck "," IntvSh "," IntvEx "," Inv
v "," CmpSh "," CmpEx "," NCmp "
Are the basic messages.
"BlkWr", "RpBack", "AckDat
The five types of messages “a”, “CmpDatSh”, and “CmpDatEx” are messages with block data.

As shown in FIG. 5A, the basic message is composed of a destination node number (10 bits), a code representing the type of the message (4 bits because there are 15 messages in total), and a request source node number (10 bits). , Mid (2 bits) and an address (40 bits), for a total of 66 bits.

The message with block data is shown in FIG.
As shown in (b), the destination node number (10 bits),
In addition to the code (4 bits) representing the type of the message, the requesting node number (10 bits), the mid (2 bits), and the address (40 bits), a total of 66 bits + 128 bytes of block size data (128 bytes) Be composed.

Hereinafter, the consistency maintaining control unit 16 shown in FIG.
Will be described in more detail. Consistency maintenance control unit 1
6 is a tag memory 22 and a request management table 24
, A local access control unit 25, a write-back block selecting unit 26, a home access control unit 27, a directory memory 31, a message transmitting unit 35, and a message receiving unit 36.

The directory memory 31 stores the main memory 30
For the data stored in each block,
Information indicating the state is stored. The information of each block stored in the directory memory 31 includes a state of the block, information of a node holding a copy in the cache memory 21 (hereinafter, referred to as holding node information), a format of the holding node information, and the number of times of writing back. It is.

The block states are "C", "M", "R"
SP ”,“ REP ”, or“ UP ”. For example,“ C ”is“ 000 ”and“ M ”is
“001”, “RSP” is coded with “100”, “REP” is coded with “101”, and “UP” is coded with 3 bits, such as “110”.

“C” as a block state indicates a state in which a copy of data exists in the cache memory 21 of a plurality of nodes PEi of 0 or more. At this time, the value of the copy in the cache memory 21 and the value of the data in the main memory 30 are the same. “M” indicates a state in which only the cache memory 21 of one node PEi holds a copy of data. At this time, the value of the copy in the cache memory 21 differs from the value of the data in the main memory 30, and the value of the copy may be the latest value. "RSP", "REP", "U
"P" indicates that a consistency maintenance process request message derived from a certain memory access has been received, and the consistency maintenance process is being performed in response to the request message.

The holding node information according to the present embodiment takes the following three forms.

(1) A pointer format for holding one node number (represented by 10 bits) specifying a node PEi.

(2) Course vector format (8 bits here).

(3) A counter format for managing the number of nodes holding copies in the cache memory 21 (represented by 10 bits and counting from 0 to 1023).

In the course vector format, the holding nodes are managed as follows.

The node PEi is divided into several groups, and the holders (nodes) are managed by the bits of the number of groups. Whether or not to set each bit depends on whether the node PEi that holds at least one copy in the group corresponding to each bit.
Is determined by whether or not exists. here,
This is represented by 8 bits, where the 0th bit is the node PE0 to the node PE127, the first bit is the node PE128 to the node PE255,. . . . . , The seventh bit is the node P
E896 corresponds to the node PE1023.

When the state is "M" or "RSP", the holding node is managed in a pointer format. In the case of “REP” or “UP”, the holding node is managed in a counter format. In the case of “C”, the pointer format and the course vector format are switched according to the number of nodes held. Therefore, the directory memory 31 also has two bits (for example, "00" for a course vector format, "01" for a pointer format, and "10" for a counter format) indicating which format is currently managed for each block. Will be retained.

The number of times of rewriting records the number of times of rewriting. Here, it is assumed that it is composed of one bit, and that the number from “0” to “1” can be counted.

In the case of this configuration, the directory memory 31
Is 16 bits (3 bits for status, 10 bits for holding node information, 2 bits for holding format, 1 bit for rewriting)
It is a memory that holds data of 4M (main memory size / block size) entries. The initial value of each entry stored in the directory memory 31 is “C” for the state and “0x000” for the holding node information (0x is 16).
Hexadecimal notation), the holding format is the course vector format, and the number of times of rewriting is “0”.

The tag memory 22 is a cache memory 21
Holds information indicating the state of the data stored in each block. The information of each block stored in the tag memory 22 is the state of the block and the tag address. Referring to FIG. 6 again, the state of each block is represented by any one of four states “I”, “S”, “E”, and “D”, and indicates the state of the corresponding block. . For example, the state of a block is coded with two bits, such as "00" for "I", "01" for "S", "10" for "E", and "11" for "D".

"I" as a block state indicates a state where there is no valid copy of data in which consistency is maintained. “S” indicates a state in which a valid copy of the data exists and there is a possibility that a valid copy also exists in the cache memory 21 of another node. “E” indicates that a valid copy of the data exists, no valid copy exists in the cache memory 21 of another node, and the state is the same as the value of the data in the main memory 30. "D"
This indicates a state in which a valid copy of the data exists, no valid copy exists in the cache memory 21 of another node, and a value different from the data value of the main memory 30.

The tag address indicates which address data the corresponding block has. Here, the cache memory 21 is controlled by a direct map method in which a block of the cache memory 21 at which data at a certain address is stored is uniquely determined. in this case,
Since the size of the cache memory 21 is 1 Mbyte, the 39th bit to the 20th
The upper 20 bits up to the bit become the tag address.

In the case of this configuration, the tag memory 22 is a memory that holds data for a 22-bit width 8K (= cache memory size / block size) entries. The initial value of each entry stored in the tag memory 22 is “I” for the state and 0x00000 for the tag address.

FIG. 6 is a diagram showing the state of the directory memory 31, the tag memory 22, and the memory blocks.

The message transmitting unit 35 and the message receiving unit 36 are connected to the interconnection network 10 and transmit a message from the node PEi to the interconnection network 10 and receive a message from the interconnection network 10. .

The message transmitting unit 35 is connected to the two modules of the local access control unit 25 and the home access control unit 27, arbitrates and outputs messages output by each module.

The message receiving unit 36 is connected to two modules, the local access control unit 25 and the home access control unit 27, and outputs a message to the two modules according to the type of the message received from the interconnection network 10. . The type of the received message is "Blk
RdSh "," BlkRdEx "," Upgrad
e "," BlkWr "," RpBack "," Ac
In the case of “k” and “AckData”, the output destination of the message is the home access control unit 27. "IntvS
h "," IntvEx "," Inv "," CmpDat
Sh "," CmpDatEx "," CmpSh "," C
In the case of "mpEx" or "NCmp", the output destination of the message is the local access control unit 25.

The request management table 24 is a table composed of four entries corresponding to the maximum number of memory accesses that can be issued simultaneously by the processor 20 (here, four). Each entry includes a valid bit (1 bit) indicating whether the entry is valid, an access type (1 bit), an address (40 bits), and data (64 bits).
It consists of 06 bits.

The request management table 24 has the following functions.

(A) A function of writing the setting data (106 bits) output from the local access control unit 25 to an entry designated by the local access control unit 25 in accordance with an instruction from the local access control unit 25.

(B) Function of outputting the contents of the entry specified by the local access control unit 25 to the local access control unit 25.

Local access control section 25 arbitrates and selects a memory access output from processor 20, a message output from home access control section 27 and a message output from message receiving section 36, and performs processing for maintaining data consistency. Having. The processing performed by the local access control unit 25 to maintain data consistency includes access to the tag memory 22, access to the cache memory 21, access to the request management table 24, access to the write-back block selection unit 26, There is a response to the processor 20 and a message output to the message transmission unit 35 or the home access control unit 27.

FIG. 4 is a diagram showing the internal configuration of the write-back block control means 26.

The write-back block selection means 26 includes an address registration means 110 for registering an address designated by the local access control unit 25, an address holding means 111 for holding a plurality of registered addresses, and an address storage means. A write-back requesting unit 112 that selects one from a plurality of addresses and outputs it to the local access control unit 25 to request a write-back, and an entry selected by the write-back requesting unit according to the instruction of the local access control unit 25 Address deleting means 113 for deleting.

Here, the address holding means 111 comprises a FIFO (First In First Out) storing two entries. The retained address is 33 bits from the 39th bit to the 7th bit. Address registration means 110
Compares the entries of the address holding unit 111 with the 39th to 7th bits of the address specified by the local access control unit 25, and if there is no matching entry, registers the entry in the address holding unit 111. Write-back request means 1
Numeral 12 outputs the address of the first entry of the FIFO to the local access control unit 25 when the FIFO is full, and requests a write-back. At this time, the 6th to 0th bits of the address are complemented with 0 and output. When the address deletion unit 113 receives an entry deletion instruction, it deletes the first entry of the FIFO.

Home access control section 27 has a function of receiving messages output from local access control section 25 and message receiving section 36 and performing processing for maintaining data consistency. The process for maintaining data consistency performed by the home access control unit 27 includes the directory memory 3
1, an access to the main memory 30, and a message output to the local access control unit 25 or the message transmission unit 33.

The home access control unit 27 holds a threshold for limiting the number of times of writing back. This threshold,
It has the same number of bits (here, 1 bit) as the number of times of writing back stored in the directory memory 31. Here, the threshold may be set by the processor 20 or may be fixed. Here, it is assumed that the value “1” is fixedly written.

FIG. 7 is a diagram showing the state transition of the node PEi 40 of this embodiment and the main memory 41 and cache memory 42 which are the constituent elements.

FIG. 7 is a diagram showing the state transition of the node PEi 40 of this embodiment and the main memory 41 and cache memory 42 which are the constituent elements.

As shown in FIG. 7, when there is a memory access to the node PEi 40, the node PEi 40 having received the memory access issues a request message to the main memory 41. The main memory 41 further issues a request to the cache memory 42 and, if desired data exists in the cache memory 42, notifies the main memory 41 of the desired data by a report message. Then, from the main memory 41, the node PEi
A completion message is returned to 40.

The operation of local access control unit 25 will be described below with reference to FIGS. This embodiment basically operates according to the flow shown in FIG.

FIG. 8A shows a local access control unit 25 receiving a memory access output from the processor 20.
FIG. 8 is a flowchart showing the processing executed by FIG.
9 is a table showing the relationship between the processing type, the type of message, the next state of the block, and the like in the processing of FIG. 8A. The local access control unit 25 stores a table showing the relationship shown in FIG.

At this time, the local access control unit 25
Is the type of access (1 bit) from the processor 20,
Information of address (40 bits), id (2 bits), and data (64 bits) is received.

First, in step S111, the local access control unit 25 accesses the tag memory 22 and reads out data (state and tag address) of the corresponding block. Here, of the 8K (1K = 1024) entries, the 1st of the 7th bit to the 19th bit of the address are set.
The data of the entry specified by 3 bits is read. Access type, status and address from bit 39 to bit 2
From the three pieces of information on whether the upper 20 bits up to 0 bits match the tag address (20 bits), it is determined which of the processing types “AA” to “AD” will be described later. From these three information, if the processing type is "AA" or "AB", the process proceeds to step S
113 and types of messages output in S115,
And the state of the block to be updated in step S118 (the tag address is always updated to the upper 20 bits of the address).

If the processing type determined in step S112 is "AA", the flow advances to step S113.

In step S113, a message to be generated is determined according to the table shown in FIG. The destination node number (10 bits) of the message contains the upper 10 bits from the 39th bit to the 30th bit of the address, and the requesting node number (10 bits) contains the node number (10 bits) of the node PEi. , Respectively. The id and the address obtained from the processor 20 are used for the mid and the address, respectively. At this time, the generated message is output to the message transmitting unit 35,
Alternatively, whether to output to the home access control unit 27 is determined as follows. Destination node number and corresponding node PE
i is compared with the node number of i, and if the result is inconsistent, the message is output to the message transmitting unit 35; At the same time, registration in the request management table 24 is also performed. The local access control unit 25 sets the valid bit to “1”, outputs the type, address, and data of the access added to the received memory access to the request management table 24 as setting data, and adds it to the received memory access. It is set to the entry (0-3) indicated by the id-th. When the process in step S113 ends, the process proceeds to step S118.

If the processing type determined in step S112 is "AB", the flow advances to step S114.

In step S114, a total of 16 entries designated by 17 bits obtained by adding 4 bits varying from 0x0 to 0xf to 13 bits from the 19th bit to the 7th bit of the address obtained from the processor 20, The block data of 128 bytes is read from the cache memory 21 (128K entries × 64 bits width), and a “BlkWr” message to which the block data is added is generated (step S114). This "Blk
The upper 10 bits from the 19th bit to the 10th bit of the tag address are used as the destination node number of the “Wr” message, and the corresponding node PEi is used as the request source node number.
Is used. The address is such that the tag address (20 bits) is the upper 20 bits and the lower 20 bits.
Bit 19 of the address obtained from processor 20
20 bits from the bit to the 0th bit are used.
Also, mid may be any value. The generated message is sent to the message transmitting unit 35 and the home access control unit 2
7 is determined based on the result of comparison between the destination node number and the node number, as in step S113. When the process in step S114 ends, the process proceeds to step S115.

The processing executed in step S115 is the same as the processing in step S113, and a description thereof will be omitted. Upon completion of the process in the step S115, the process proceeds to the step S115.
Proceed to 118.

If the processing type determined in step S112 is "AC", the flow advances to step S116.

In the step S116, the 1-th to the 19th to the third bits of the address obtained from the processor 20 are set.
64-bit data corresponding to the entry specified by 7 bits is read from the cache memory 21, and the read data is returned to the processor 20. At this time,
The id obtained from the processor 20 is also
To indicate that the response is to the memory access of the id. Upon completion of the process in the step S116, the process proceeds to a step S118.

If the processing type determined in step S112 is "AD", the flow advances to step S117.

In the step S117, the 1-th to the 19th to the third bits of the address obtained from the processor 20 are set.
The 64-bit data obtained from the processor 20 is written into the entry of the cache memory 21 specified by 7 bits. Further, it outputs an id to the processor 20 and notifies the completion of the memory access. Thereby, the id
Is notified to the processor that the processing for the memory access has been completed. When the processing of step S117 ends,
Proceed to step S118.

At step S118, processing for updating the tag memory 22 is performed. The entry to be updated is the entry accessed in step S111, the state is the next state of the block shown in FIG. 8B, and the tag address is the higher order from the 39th bit to the 20th bit of the address obtained from the processor 20. Update to 20 bits. When the process in step S118 ends, the process related to the memory access ends.

FIG. 9A shows the home access control unit 27.
Alternatively, FIG. 9B is a flowchart illustrating a process executed by the local access control unit 25 when three types of messages, IntvSh, IntvEx, and Upgrade, among messages output by the message receiving unit 36 are received. 10 is a table showing a relationship between a process type, a message type, a next state of a block, and the like in the process of FIG. The local access control unit 25 stores a table indicating the relationship shown in FIG. First,
In step S121, read access is performed to the tag memory 22 using the address value included in the message.
The entry of the tag memory 22 to be accessed is specified by 13 bits from the 19th bit to the 7th bit of the address. As a result, the state of the corresponding block and the tag address are read. Message type, status,
From the three information indicating whether the tag address matches the upper 20 bits from the 39th bit to the 20th bit of the address added to the message, which processing type of “BA” and “BB” to be described later Is determined. Also, from the above three information, step S123
Of message to be output in step S125
Also determines the state of the block to be updated (the value of the tag address is not changed). In addition, the above three information and processing type,
The relationship between the type of message and the next state of the block is shown in FIG.
The result is as shown in FIG. Local access control unit 25
Stores a table indicating this relationship.

If the processing type determined in step S122 is "BA", the flow advances to step S123.

In step S123, a message to be generated is determined according to the table shown in FIG. When a message is generated, the requesting node number, address, mi
For d, the one of the received message is used as it is.
The upper 10 bits from the 39th bit to the 30th bit of the address of the received message are used as the destination node number. Whether to output the generated message to the message transmission unit 35 or the home access control unit 27 is determined based on the comparison result between the destination node number and the node number, as in the case of step S113 in FIG. 8A. I do. When the process of step S123 ends,
Proceed to step S125.

If the processing type determined in step S122 is "BB", the flow advances to step S124.

In the step S124, a total of 16 entries specified by 17 bits obtained by adding 4 bits changing from 0x0 to 0xf to 13 bits from the 19th bit to the 7th bit of the address of the received message,
Read 128 bytes of block data. FIG. 9B
The message to be generated is determined in accordance with the table described above, the read block data is added to the generated message, and the message is transmitted via the transmission unit 35. When a message is generated, the requesting node number, address, and mid are the same as those of the received message. As the destination node number, the upper 10 bits from the 39th bit to the 30th bit of the address of the received message are used. The local access control unit 25 determines whether to output the generated message to the message transmission unit 38 or the home access control unit 27 based on the comparison result between the destination node number and the node number, as in the case of step S113. decide. When the process of step S124 ends,
Proceed to step S125.

In the step S125, the tag memory 22 is updated. The entry to be updated is the entry accessed in step S121, the state is the next state of the block shown in FIG.
The tag address is updated to the tag address read in step 1. When the processing in step S125 ends, the processing related to the received message ends.

FIGS. 10 and 11 (a) show the messages "CmpDatSh" and "CmpDamp" output from the home access control unit 27 or the message receiving unit 36.
DatEx ”,“ CmpSh ”,“ CmpEx ”,“ N
FIG. 11B is a flowchart illustrating a process executed by the local access control unit 25 when five types of messages “Cmp” are received.
3 is a table showing the relationship between the processing type, the type of message, the next state of the block, and the like in the processing of FIG. The local access control unit 25 stores a table showing the relationship shown in FIG.

First, in step S131, the mid included in the message is output to the request management table 24, and the information of the mid-th entry is read. As a result, from the request management table 24, information on valid bits, access types, addresses, and data (64 bits) is obtained. When the process in step S131 ends, the process proceeds to step S132.

In step S132, it is determined whether the received message has data, that is, "CmpDatSh" or "CmpDatEx", or whether the received message is a "CmpSh", "CmpEx", or "NCmp" message without data (step S132). Step S132). If it is determined that the message is not a message with data, the process proceeds to step S133. On the other hand, if it is determined that the message has data, the process proceeds to step S135.

In the step S133, it is determined whether or not the received message is "NCmp". "NCm
If not "p", the flow proceeds to step S137. "NCm
In the case of "p", it is determined that the type of access, address, and data obtained from the request management table 24 have been output by the processor 20, and the process proceeds to step S111.
(Step S133).

In the step S134, the block data (128 bytes) attached to the message is written to the corresponding block in the cache memory 21. The entry to be written is designated by a 17-bit index signal in which 13 bits from the 19th bit to the 7th bit of the address obtained from the request management table 24 and 4 bits that change from 0x0 to 0xf are added to the lower order.
There are six entries, each of which is written in order of 64 bits. Upon completion of the process in the step S134, the process proceeds to a step S135.

In step S135, it is checked whether the type of access obtained from the request management table 24 is load or store. If the access type is store, the process proceeds to step S136. On the other hand, if the access type is load, the process proceeds to step S138.

In the step S136, the data (64 bits) obtained from the request management table 24 is written to the corresponding entry in the cache memory 21. The entry to be written is specified by 17 bits from the 19th bit to the 3rd bit of the address obtained from the request management table 24. Further, data in which the valid bit is set to “0” is output to the request management table 24,
Write to the entry specified by mid of the message that received the value. As a result, the corresponding entry is deleted from the request management table 24. Further, a process for updating the tag memory 22 is also performed. The entry to be updated is specified by 13 bits from the 19th bit to the 7th bit of the address obtained from the request management table 24. The data to be updated is the state of the block and the tag address. For the state of the block, see FIG.
According to the table of 1 (b), it is determined by the type of access (here, store) and the type of received message. In the tag address, the request management table 24
The upper 20 bits from the 39th bit to the 20th bit of the address read from are used. Further, a completion notification is sent to the processor 20. At this time, the mid added to the message is output to the processor 20 to notify which memory access has been completed. When the process in step S136 ends, the process proceeds to step S137.

In the step S137, it is determined whether or not the received message is "CmpSh" or "CmpDatSh". In the case of “Yes”, the process proceeds to step S141, where a write-back process is performed. If “No”, the processing of the received message is ended.

In step S138, 64-bit data of an entry in the cache memory 21 specified by 17 bits from the 19th bit to the 3rd bit of the address obtained from the request management table 24 is read. The read 64-bit data is passed to the processor 20 together with the mid. Request management table 2
4 and the tag memory 22 are also updated. All of these processes are the same as the respective processes in step S136, and a description thereof will be omitted. Step S138
Is completed, the processing of the received message ends.

In step S141, it is checked whether or not the write-back block selecting means 26 requests a write-back. If a write-back has been requested, step S142
Proceed to. If not, the process proceeds to step S146.

In the step S142, the tag memory 22 specified by 13 bits from the 19th bit to the 7th bit of the address output from the write-back block selecting means 26
Is read, and the tag address and status are obtained.

In the step S143, the tag address 20
It is determined whether write-back is necessary based on whether the bits match the upper 20 bits of the address output from the write-back block selecting means 26 and whether the state is "D". If both are “Yes”, it is determined that rewriting is necessary, and the process proceeds to step S144. If either is “No”, the process proceeds to step S145.

In step S144, the address obtained from the write-back block selecting means 26 is designated by 17 bits obtained by adding 4 bits varying from 0x0 to 0xf to 13 bits from the 19th bit to the 7th bit. The block data of a total of 16 entries and 128 bytes is read from the cache memory 21, and an “RpBack” message to which the block data is added is generated.
As the destination node number of the “RpBack” message, the upper 10 bits of the address obtained from the write-back block selecting means 26 are used, and as the request source node number, the node number of the node PEi is used. As the address, the address obtained from the write-back block selecting means 26 is used. Also, mid may be any value. Whether the generated message is to be output to the message transmitting unit 35 or the home access control unit 27 is determined based on the comparison result between the destination node number and the node number, as in the case of step S113 in FIG. 8A. . Also, the tag memory 22 is updated. The entry to be updated is the entry specified in step S142, and the state is updated to “S”, and the tag address is updated to the tag address read in step S142. Upon completion of the process in the step S144, the process proceeds to a step S145.

In the step S145, the address of the request received from the write-back block selecting means 26 is deleted. Upon completion of the process in the step S145, the process proceeds to a step S146.

In step S146, the address added to the received message ("CmpSh" or "CmpDatSh") is written back to the block selecting means 26.
Register with. When this process ends, the process of the received message ends.

Hereinafter, FIGS. 12A and 12B and FIG.
The operation of the home access control unit 27 will be described with reference to FIG.

FIG. 12A shows the home access control unit 2.
7 is a flowchart showing a process to be executed, and FIG.
2 (b) and FIG. 13 show uncached information, writing, received from the type of received message, state of block read from directory memory, holding format and holding node information used in the processing of the flowchart of FIG. 12 (a). 6 is a table showing four pieces of information indicating whether or not the number of reversions matches a threshold, states of blocks stored in the directory memory, operations on holding node information, operations on the number of times of rewriting, processing types, and types of messages.

In the processing of the flowchart in FIG. 12A, the home access control unit 27 determines the type of the received message, the state of the block read from the directory memory 31, the holding format, and the uncached (Uncached) obtained from the holding node information. ) Based on the information, the four information of whether the number of rewrites and the threshold value match,
In step S152, the state of the block stored in the directory memory 31, the operation on the holding node information and the holding format, the operation on the number of times of writing back, the operation in step S15
3, the processing type, step S154, step S15
5. Determine the type of message to be output in step S156.

The home access control unit 27 is configured as shown in FIG.
(B), the table shown in FIG. 13 is stored. In addition,
In FIGS. 12B and 13, “−−” indicates that any value is acceptable.

The uncached information shown in FIGS. 12 (b) and 13 is used for the other nodes PE except the requesting node PEi.
This is to determine whether i holds a copy. How to obtain the uncached information differs depending on the format of the holding node information.

In the case where the holding node information is in the pointer format, if the requesting node number of the received message and the holding node information match, the uncached information becomes "Yes" and does not match. In this case, the result is “No”.

When the holding node information is in the course vector format, the uncached information becomes "Yes" when the course vector is "0" for all 8 bits, and when the "1" is set even for one bit. Is “No”.

When the holding node information is in a counter format,
When the value obtained by subtracting 1 from the number of holding nodes becomes “0”, the uncached information becomes “Yes” and “0”
Otherwise, "No".

Next, an operation on the holding node information shown in FIGS. 12 (a) and 13 ("holding node operation" in the figure)
Will be described. Operations on the holding node information include “set”, “add”, “count”,
There are six operations of "dec", "clean", and "none".

"Set" sets the requesting node number of the received message as a holding node number, and is held in a pointer format. At this time, the holding format is also set to “01” indicating the pointer format.

"Add" is an operation performed on the holding node number format and the course vector format. In the case of the holding node number format, eight bits obtained by decoding the upper three bits of the read holding node number are decoded. In the case of the course vector format, the same eight bits are decoded. This is set to a value obtained by taking a logical sum with the obtained 8 bits. "Ad
By performing the operation "d", the holding format becomes the course vector format. Accordingly, the holding format is also set to “00” indicating the course vector format.

"Count" is an operation performed on the holding node number format or the course vector format.
This is an operation for determining how many nodes PEi are to hold a copy from the read holding node information except for the requesting node number. “Count” is set to “1” in the case of the pointer format. In the case of the course vector format, the number of bits with 1 in 8 bits and 1
It is obtained by multiplying the number of nodes PEi represented by the bit by 128. However, if the bit corresponding to the requesting node number is 1, a value obtained by subtracting 1 from the number obtained above is set. As a result, the holding format also indicates “1” indicating the counter format.
0 "is set.

"Dec" is an operation performed on the counter format. This is set to a value obtained by subtracting 1 from the read number of holding nodes.

"Clean" is for setting all 10 bits to "0". In this case, the holding format is set to “00” indicating the course vector format.

"None" is set without any operation on the read value. The value of the retention format is also maintained.

Next, the number of times of rewriting shown in FIGS. 12B and 13 will be described. Operations related to the number of times of rewriting include an operation of initializing the value to “0” and an operation of adding the current value plus 1 to the next value. "0",
“+1” corresponds to each. If there is no description, it indicates that the same value as the current value is set as the next value.

The processing of the flowchart shown in FIG. 12A will be described below.

First, in step S151, the home access control unit 27 reads the data (state, holding node information, holding format, number of times of rewriting) of the corresponding directory memory entry (step S151). The entry to be read is the 28th address of the received message.
This is data of the directory memory 31 indexed by 22 bits from the bit to the seventh bit. Upon completion of the process in the step S151, the process proceeds to a step S152.

In step S152, step S151
Updates the value of the entry of the directory memory 31 read in step. The state is determined according to the tables shown in FIGS. The holding node information is shown in FIG.
(B) The operation shown in FIG. 13 is performed on the holding node information read in step S131, and is obtained. The holding node format is also determined by the operation as described above. The number of times of writing back is obtained by performing the operations shown in FIGS. The entry updated in step S152 is the same entry as the entry accessed in step S151. If the message has data, the process of writing block data to the main memory 30 is also performed. The entry in the main memory 30 into which the block data is written is a total of 26 bits specified by adding the lower 4 bits varying from 0x0 to 0xf to 22 bits from the 28th bit to the 7th bit of the address of the received message. There are 16 entries (128 bytes). Upon completion of the process in the step S152, the process proceeds to a step S153.

In step S153, the type of the received message, the state of the block read from the directory memory 31, the uncached information obtained from the holding format and the holding node information, and the comparison result of the number of times of writing back and the threshold value are calculated.
It is determined whether the processing type is any of “CA” to “CC” from the two pieces of information. If it is determined that the processing type is “CA”, the process proceeds to step S154. If it is determined in step S153 that the processing type is “CB”, the process proceeds to step S155. If it is determined in step S153 that the processing type is “CC”, the processing of the received message is terminated.

In step S154, if necessary, a plurality of messages are generated and output. The output destination is either the local access control unit 25 or the message transmission unit 35. The output destination is determined based on the comparison result between the destination node number of the generated message and the node number. If they match, the local access control unit 25 is used.
It becomes 5. Message to be output (destination node number, message type, address, mid, requesting node number)
Is generated as follows. The message type is
The determination is made according to FIGS. Address, m
The id and the requesting node number are the address, the mid and the requesting node number of the received message, respectively. The destination node number differs depending on the type of message to be generated.
The following shows how to determine the destination node number according to the type of message.

“CmpDatSh”, “CmpDatE”
x ”,“ CmpSh ”,“ CmpEx ”,“ NCmp ”
In the case of, the request source node number of the received message becomes the destination node number. "IntvSh", "IntvEx"
In the case of, the format of the holding node information read from the directory memory 31 in step S141 is a pointer format, and the value is used as it is. In the case of the above messages, only one message is generated.

In the case of "Inv", a plurality of messages differing only in the destination node number are generated and transmitted. This destination node number is generated according to the holding node information.
The holding node information is in a pointer format or a course vector format. In the case of the pointer format, the above-mentioned “IntvSh”
As in the case of (1), the holding node information is used as it is, and only one message is generated. In the case of the course vector format, the same message having a different destination is generated and output to a plurality of nodes PEi (excluding the requesting node) represented in this format. For example, the holding node information is “00110100” and the requesting node number is “0”.
010010110 ", the destination node is PE256
To 383, PE512 to PE807, and the “Inv” message is transmitted to these 384 nodes. Further, for example, the holding node information is “11001011” and the requesting node number is “00”.
10010110 ", the destination nodes are PE0-PE
149, PE151 to PE255, PE384 to PE5
11, a total of 679 nodes of PE 808 to PE 1023, and an “Inv” message is transmitted to these 679 nodes.

In step S154, when the generation and output of the message are completed, the processing of the received message is completed.

In the step S155, the main memory 30 (6
The corresponding block data (128 bytes) is read from 4M entries × 64 bits width. The block data to be read includes 0x0 to 0x in 22 bits from the 28th bit to the 7th bit of the address of the received message.
Data of a total of 16 entries designated by 26 bits obtained by adding 4 bits changing to f to the lower order, and is composed of 128 bytes. This block data is added to the generated message and output. The output destination is either the local access control unit 25 or the message transmission unit 35. Which output is to be made is determined in the same manner as in step S154. The same applies to generation of a message. When the processing in step S155 ends, the processing of the received message ends.

The preceding is an explanation of the operation of the first embodiment of the present invention. Next, in order to facilitate understanding of the present embodiment, a specific example of the operation of the present embodiment will be described with reference to FIGS. 1 to 3 and divided into phases 1 to 5B.

Here, the phase 1 is an operation from the time when the processor 20 of the node PE1 performs the load access to the data of the main memory 30 of the node PE1 until the completion thereof.

In the phase 2, after the phase 1, the node P
This is an operation from the time when the processor 20 of E2 performs the load access to the data of the same block as the data of the main memory 30 of the node PE1 accessed by the node PE1 in the phase 1 until the completion thereof.

In phase 3, after phase 2, node P
This is an operation from the time when the processor 20 of E2 performs a store access to data in the same block as the data in the main memory 30 of the node PE1 accessed in the phase 2 until the process is completed.

In phase 4, after phase 3, node P
As a result of the write-back processing performed in E2, "RpBac
k "message is sent and processed until it is processed.

The phase 5A is an operation from the time when the processor 20 of the node PE1 performs the load access to the data of the block written back in the phase 4 after the phase 4 until the completion thereof.

The phase 5B is an operation from the time when the processor 20 of the node PE2 performs the store access to the data of the block written back in the phase 4 after the phase 4 until the completion of the store access.

1. Phase 1 (1) Load Access Processing The processor 20 of the node PE1 receives the address “0x004”.
It is assumed that load access is performed to id 00300000 with id = "0".

The local access control unit 25 having received the memory access performed by the processor 20 operates as follows according to the flowchart of FIG.

First, in step S111, the tag memory 2
2 address “0x0600” (the 19th bit to the address “0x0040030000” obtained from the processor 20)
The data of the seventh bit (13 bits) is read. Since the initial state is “I”, the processing type is “AA”, the message to be issued is “BlkRdSh” from FIG.
The next state of the block is determined to be "I". Upon completion of the above processing, the process advances to step S112.

In step S112, if the processing type is "A
A ”, the flow proceeds to step S113.

In step S113, a message is generated and output and registered in the request management table 24. The destination node number of the message to be generated and output is "0
x001 ”(10 bits from the 39th bit to the 30th bit of the address“ 0x0040030000 ”), the message type is“ BlkRdSh ”, and the address is“ 0x00 ”.
4030000 ", the mid is" 0 "(= id), and the request source node number is" 0x001 ". Further, both the destination node number and the node number of the node PE1 are “0”.
x001 ”, the output destination is the node PE1.
Of the home access control unit 27. In addition, the valid bit is set to "1", the access type is loaded, and the address is set to "0x00400300000" in the "0" (= id) entry of the request management table. Upon completion of the above processing, the flow advances to step S118.

In the step S118, 0x of the tag memory is
The data of the entry at address 0600, the state is "I",
The tag address is “0x00400” (address “0x0
040030000 ”(20 bits from the 39th bit to the 20th bit).

As described above, the local access control unit 25 of the node PE1 ends the load access processing.

(2) Processing of BlkRdSh Message The above “BlkRdSh” message (the destination node number is “0x001” and the message type is “BlkRdS
h ", the address is" 0x0040030000 ", mi
(d is “0” and the requesting node number is “0x001”).
The operation is performed as follows according to the flowchart of FIG.

First, in step S151, the address "0x000600" (22 bits from the 28th bit to the 7th bit of the address "0x0040030000" added to the message) in the directory memory 31 is accessed, and the data such as the state is read. . The read state, the holding node information, the holding format, and the number of times of rewriting are “C”, “0x000”, “00” (course vector format), and “0” in the initial state, respectively. The type of message received is "B
lkRdSh ”, the read state is“ C ”, the holding format is the course vector format, and the holding node information is“ 0x00 ”.
0 "and uncached, the processing type is" CB ", the next state of the block is" M ", the holding node operation is" set ", the number of write-backs is unchanged, and the type of message to be output is" CmpDatEx ". (See FIGS. 12A and 13). Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000600” of the directory memory 31 is stored in the state “M” and the holding node information is “0x000600”.
“001”, the holding format is updated to “01” (pointer format), and the number of times of writing back is updated to “0”. Since the message is not a message with data, writing of block data to the main memory 30 is not performed. Upon completion of the above processing, the process advances to step S153.

In step S153, if the processing type is “C
B ”, the flow proceeds to step S155.

In step S155, the addresses “0x0006000” to “0x000600f” of the main memory 30 are set.
The block data of 64 bits × 16 entries = 128 bytes up to the address is read, added to the message to be generated, and output. This message indicates that the destination node number is "0".
x001 ”and the message type as“ CmpDatE
x ", address" 0x00400300000 ", mi
This is a message in which d is “0”, the request source node number is “0x001”, and the block data is the block data read in step S145. The output destination of this message is that the destination node number and the node number are both “0”.
x001 ", it becomes the local access control unit 25 of the node.

With the above, the home access control unit 27 of the node PE1 ends the processing of the “BlkRdSh” message.

(3) Processing of CmpDatEx Message The above “CmpDatEx” message (the destination node number is “0x001”, and the message type is “CmpDatEx”
Ex ”, the address is“ 0x0040030000 ”, m
(id is “0” and the requesting node number is “0x001”).
The operation is performed as follows according to the flowcharts of FIG. 10 and FIG.

First, in step S131, the information of the "0" (= mid) entry of the request management table 24 is read, and the type of access is loaded, and the information of the address "0x0 040030000" is obtained. Upon completion of the above processing, the process advances to step S132.

In step S132, since the message is a message with block data, the flow advances to step S135.

In the step S135, from the address "0x06000" of the cache memory 21 to the address "0x0600f"
Write the block data added to the message at the address. When the above processing is completed, step S136
Proceed to.

In step S136, since the access type is load, the flow advances to step S139.

In step S139, 64-bit data at the address "0x06000" is read from the cache memory 21 and passed to the processor 20 as response data to the memory access with id = "0". This completes the memory access. In addition, data with the valid bit set to “0” is written to the “0” entry of the request management table 24, and the entry is deleted. Also, the state of the address “0x0600” and the tag address of the tag memory are updated to “E” and “0x00400”, respectively (see FIG. 11B).

Thus, the local access control unit 25 of the node PE1 ends the processing of the received “CmpDatEx” message.

At this stage, “0x0040030000”
Up to the address “0x004003007f”, the latest data exists in the main memory 30 of the node PE1 and the cache memory 21 of the node PE1.

2. Phase 2 (1) Processing of Load Access Next, at the node PE2, the load access is set to id =
It is assumed that the processing is performed on the address “0x00400300000” at “2”.

The memory access performed by the processor 20 (the access type is load and the address is “0x0040”
030000 ”, id =“ 2 ”), the local access control unit 25 operates as follows according to the flowchart of FIG.

First, in step S111, the tag memory 2
The data at the address "0x0600" is read out (step S111). Since the initial state is “I”, FIG.
From (b), the processing type is determined as "AA", the message to be issued is determined as "BlkRdSh", and the next state of the block is determined as "I". Upon completion of the above processing, the process advances to step S112.

In step S112, if the processing type is "A
A ”, the flow proceeds to step S113.

In step S113, a message is generated and output and registered in the request management table 24. The destination node number of the message to be generated and output is "0
x001 ”(10 bits from the 39th bit to the 30th bit of the address“ 0x0040030000 ”), the message type is“ BlkRdSh ”, and the address is“ 0x00 ”.
4030000 ", the mid is" 2 ", and the requesting node number is" 0x002 ". Since the destination node number and the node number of the node PE2 are different, the output destination is the message transmitting unit 35. At this time, the valid bit is “1”, the access type is load, and the address is “0” in the “2” (= id) entry of the request management table.
x0040030000 "is written. Upon completion of the above processing, the process advances to step S118.

In step S118, “0” in the tag memory
The data of the entry at the address "x0600" and the state is "I"
The tag address is “0x00400” (address “0
x0040030000 ”(20 bits from the 39th bit to the 20th bit) (step S118).

As described above, the local access control unit 25 of the node PE2 ends the load access processing.

(2) Processing of BlkRdSh Message The “BlkRdSh” message is sent to the message transmitting unit 35 of the node PE2, the interconnection network 10, and the node PE1.
Is sent to the home access control unit 27 of the node PE1 via the message receiving unit 36 of

The “BlkRdSh” message (the destination node number is “0x001” and the message type is “BlkRdSh”
lkRdSh ”and the address is“ 0x004003000 ”
0, mid is “2”, and the requesting node number is “0x00”
2 ”), the home access control unit 27
The operation is performed as follows according to the flowchart of FIG.

First, in step S151, the address of "0x000600" (22 bits of the 28th to 7th bits of the address "0x0040030000" added to the message) in the directory memory 31 is accessed, and data such as the state is read. . In Phase 1,
The state, the holding node information, the holding format, and the number of times of rewriting have been updated to “M”, “0x001”, “01”, and “0”, respectively, and the values are read. The type of the received message is "BlkRdSh", the read state is "M", the holding format is the pointer format, the holding node information is "0x001", and it is not uncached. CA ", the next state of the block is" RSP ", and the holding node operation is" non ".
e ", the number of write-backs is" 0 ", and the type of message to be output is determined to be" IntvSh ". . Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000600” of the directory memory 31 is stored in the state “RSP”, the holding node information is “0x001”, the holding format is “01”, Is updated to “0”. Here, since the message is not a message with data, writing of block data to the main memory 30 is not performed. Upon completion of the above processing, the process advances to step S153.

In step S153, if the processing type is “C
A ”, the flow proceeds to step S154.

In step S154, the destination no. Number is “0x001” and the message type is “IntvS
h ", the address is" 0x0040030000 ", mi
A message in which d is “2” and the requesting node number is “0x002” is generated. The output destination of the message is the local access control unit 25 because the destination node number matches the node number of the node PE1 (step S144).

[0219] As described above, the home access control unit 27 of the node PE1 ends the processing of the "BlkRdSh" message.

(3) Processing of IntvSh message The above “IntvSh” message (the destination node number is “0x001”, and the message type is “IntvSh”
h ", the address is" 0x0040030000 ", mi
The local access control unit 25 of the node PE1 which has received d is “2” and the request source node number is “0x002”) operates as follows according to the flowchart of FIG.

First, in step S121, the tag memory 2
2, the data at the address "0x0600" is read out. In phase 1, the state and the tag address have been updated to "E" and "0x00400", respectively, and these values are read. The received message is "IntvS
h ", the tag addresses match, and the state is" E ", the processing type is" B "according to FIG.
"A", the type of message to be output is "Ack", and the next state of the block is "S".

At step S122, if the processing type is "B
A ”, the flow proceeds to step S123.

At step S123, an "Ack" message is generated. The destination node number of the “Ack” message is “0x001”, and the message type is “Ac”.
k, the address is “0x0040030000”, the requesting node number is “0x002”, and the mid is “2”. Since the destination node number matches the node number of the node PE1 with “0x001”, the output destination is the home access control unit 27. Upon completion of the above processing, the process advances to step S125.

In the step S125, “0” of the tag memory
The status and tag address of the address “x0600” are updated to “S” and “0x00400”, respectively.

Thus, the local access control unit 25 of the node PE1 ends the processing of the “IntvSh” message.

(4) Processing of Ack message The above “Ack” message (the destination node number is “0x0
01 ", the message type is" Ack ", the address is" 0x0040030000 ", the mid is" 2 ", and the requesting node number is" 0x002 "). The home access control unit 27 receives the following in accordance with FIG. Works like that.

First, in step S151, the address "0x000600" (the 28th bit to the 7th bit 22 bits of the address "0x0040030000" added to the message) in the directory memory 31 is accessed, and the data such as the state is read. . The read state, the holding node information, the holding format, and the number of rewrites have been updated to “RSP”, “0x001”, “01” (pointer format), and “0” in Phase 2, respectively, and the values are read. Since the type of the received message is “Ack” and the read state is “RSP”, the processing type is “CB”, the next state of the block is “C”, and the number of write-backs is The holding node operation is “add”, and the type of message to be output is “CmpDa”.
tSh ”. Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000600” in the directory memory 31 is stored in the state “C” and the holding node information is “0x000600”.
001 ”, holding format is“ 00 ”(course vector format),
The rewrite count is updated to “0”. Since the “Ack” message is not a message with block data, data is not written to the main memory 30. However, the latest data exists in the main memory 30. Upon completion of the above processing, the process advances to step S153.

At step S153, when the processing type is “C
B ”, the flow proceeds to step S155.

In step S155, addresses “0x0006000” to “0x000600f” of the main memory 30 are set.
The block data of 64 bits × 16 entries = 128 bytes up to the address is read, added to the message to be generated, and output. This message indicates that the destination node number is "0".
x002 ”and the type of message is“ CmpDatS
h ", the address is" 0x0040030000 ", mi
This is a message in which d is “2”, the requesting node number is “0x002”, and the block data is the block data read in step S145. The output destination of this message is the destination node number “0x002” and the node P
Since the node number “0x001” of E1 does not match, the message transmission unit 35 is used.

Thus, the home access control unit 27 of the node PE1 ends the processing of the “Ack” message.

(5) Processing of CmpDatSh message The “CmpDatSh” message is transmitted to the node PE1
Message transmission unit 35, interconnection network 10, node PE
The message is output to the local access control unit 25 of the node PE2 via the second message receiving unit 36.

The “CmpDatSh” message (the destination node number is “0x002”, the message type is “CmpDatSh”, and the address is “0x004003”
0000 ", mid is" 2 ", and the requesting node number is" 0 "
x002 ”and the local access control unit 25 of the node PE2 receiving the block data (the latest data)
According to the flowchart of FIG.

First, in step S131, the information of the “2” (= mid) entry of the request management table 24 is read, and the access type is load and the address is “0”.
x0040030000 "is obtained. Upon completion of the above processing, the process advances to step S132.

In step S132, since the message is a message with block data, the flow advances to step S135.

In the step S135, from the address “0x06000” of the cache memory 21 to the address “0x0600f”
Write the block data added to the message at the address. When the above processing is completed, step S136
Proceed to.

In step S136, since the access type is load, the flow advances to step S139.

In step S139, 64-bit data at the address "0x06000" is read from the cache memory 21 and passed to the processor 20 as response data to the memory access with id = "2". This completes the memory access. In addition, data with the valid bit set to “0” is written to the “2” entry of the request management table 24, and the entry is deleted. Further, the state of the address “0x0600” and the tag address of the tag memory are changed to “S” and “0”, respectively, according to FIG.
x00400 ”(step S139).

[0239] Thus, the local access control unit 25 of the node PE2 ends the processing of the received "CmpDatSh" message.

At this stage, “0x0040030000”
Up to the address “0x004003007f”, the latest data is stored in the cache memory 21 of the node PE1, the main memory 30 of the node PE1, and the cache memory 21 of the node PE2.

[0241] 3. Phase 3 (1) Processing of Store Access Next, at the node PE2, the store access is set to id =
It is assumed that the processing is performed at the address “0x0040030010” with “1”.

The local access control unit 25 of the node PE2 that has received the memory access performed by the processor 20
The operation is performed as follows according to the flowchart of FIG.

First, in step S111, the tag memory 2
2, the data at the address "0x0600" is read. In phase 2, the state is “S” and the tag address is “0x00”.
400 ", and its value is read. The access type is store, and the tag address is "0x0
0400 "and the state is" S ".
According to (b), the processing type is determined to be "AA", the type of message to be output is determined to be "Upgrade", and the next state of the block is determined to be "S". When the above processing is completed, step S
Proceed to 112.

In step S112, when the processing type is "A
A ”, the flow proceeds to step S113.

In step S113, a message is generated and output and registered in the request management table 24. The destination node number of the message to be generated and output is "0
x001 "(10 bits from the 39th bit to the 30th bit of the address" 0x0040030010 "), the message type is" Upgrade ", and the address is" 0x00 ".
40030010 ", the mid is" 1 ", and the requesting node number is" 0x002 ". Since the destination node number and the node number of the node PE2 are different, the output destination is the message transmitting unit 35. At this time, the valid bit is “1”, the access type is store, and the address is “0” in the entry “1” (= id) of the request management table.
x0040030010 "and store data. Upon completion of the above processing, the process advances to step S118.

At step S118, “0” in the tag memory
The data of the entry at the address “x0600” and the state is “S”
The tag address is “0x00400” (address “0
x0040030010 ”(20 bits from the 39th bit to the 20th bit).

Thus, the local access control unit 25 of the node PE2 ends the store access processing.

(2) Processing of the Upgrade message The “Upgrade” message is sent to the message transmitting unit 35 of the node PE2, the interconnection network 10, and the node PE1.
Is sent to the home access control unit 27 of the node PE1 via the message receiving unit 36 of

The above "Upgrade" message (the destination node number is "0x001", and the message type is "U
pgrade "and the address is" 0x004003001
0, mid is “1”, and the requesting node number is “0x00”
2 "), the home access control unit 2 of the node PE1
7 operates as follows according to the flowchart of FIG.

First, in step S151, the address of “0x000600” (the 22nd bit of the 28th to 7th bits of the address “0x0040030010” added to the message) in the directory memory 31 is accessed, and the data such as the state is read. . In Phase 2,
The state, the holding node information, the holding format, and the number of times of rewriting are updated to “C”, “0x001”, “00” (course vector format), and “0”, respectively, and the values are read. Since the type of the received message is “Upgrade”, the read state is “C”, the holding format is the course vector format, the holding node information is “0x001”, and it is not uncached, FIG. ), The processing type is “CA”, and the next state of the block is “U”.
P, the holding node operation is “count”, the number of write-back updates is unchanged, and the type of message to be output is “In”.
v ”. When the above processing is completed, step S1
Go to 52.

In step S152, based on these information, the data at the address “0x000006” in the directory memory 31 is stored in the state “UP” and the holding node information is “0”.
x07f ”, the holding format is updated to“ 10 ”(counter format), and the number of write-backs is updated to“ 0 ”. Since the message being processed is not a message with block data, writing to the main memory 30 is not performed. Upon completion of the above processing, the process advances to step S153.

In the step S153, the processing type is “C
A ”, the flow proceeds to step S154.

In step S154, a plurality of “Inv” messages that differ only in the destination node number are generated and output. The “Inv” message has a message type “Inv” and an address “0x0040030001”.
0, mid is “1”, and the requesting node number is “0x00”
2 ". The destination node number is “0x0” excluding the request source node number “0x002”.
00 ”to“ 0x07f ”. With the above processing, 127
Messages are generated. The output destination of each message is determined based on the result of comparison between the destination node number and the node number. The message with the destination node number “0x001” is the node number “0x001” of the node PE1.
Is output to the local access control unit 25. Other messages whose destination node number is not “0x001” do not match the node number of the node PE1, and are output to the message transmitting unit 35.

With the above, the home access control unit 27 of the node PE2 ends the processing of the “Upgrade” message.

(3) Processing of Inv message These "Inv" messages are sent to the message transmitting unit 35 of the node PE1, the interconnection network, and the nodes PE0 to PE1.
The message is output to the local access control unit 25 of each node via the message receiving unit 36 (excluding PE1 and PE2). The “Inv” message to the node PE1 is output directly to the local access control unit 25 as described above.

The above-mentioned “Inv” message (the destination node number is the node number of the receiving node PEi, the message type is “Inv”, and the address is “0x004030001”
0, mid is “1”, and the requesting node number is “0x00”
2 "), each node PEi (i = 0, 1, 3,...)
· 127) of the local access control unit 25 shown in FIG.
The operation is performed as follows according to the flowchart of FIG.

First, in step S 121, the local access control unit 25 that has received the “Inv” message reads data at the address “0x0600” in the tag memory 22. Depending on whether the read tag address matches “0x00400” and what the state is, the processing type, the type of message to be output, and the next state of the block of the tag memory 22 are determined according to the table in FIG. Is determined. Upon completion of the above processing, the process advances to step S122.

In step S122, since the processing type when the "Inv" message is received is "BA", the flow advances to step S123.

At step S123, an "Ack" message is generated. This "Ack" message is
The destination node number is “0x001”, the message type is “Ack”, and the address is “0x0040030001”.
0, mid is “1”, and the requesting node number is “0x00”
2 ". The output destination is determined based on a comparison result between the destination node number “0x001” and the node number. Node P
If E1, they match, so the home access control unit 27
Output to If it is another node, it does not match and outputs it to the message transmitting unit 35. After completing the above processing,
Proceed to step S125.

At step S125, the tag memory is updated. The entry to be updated is the entry at the address “0x0600” read out in step 121, the state is updated to the next state “I” of the block obtained from FIG. 8, and the tag address is the value read from the tag memory 22 as it is. Is written (step S12
5).

As described above, each node PEi (i = 0, 1, 3, 3)
, 127), the "In"
v "message processing ends.

(4) Processing of Ack Message Nodes PE0, PE3 to PE127 each transmit the “Ack” message to node PE1. The “Ack” message is sent to the message transmitting unit 35 of each node, the interconnection network 10, the node PE1
Is output to the home access control unit 27 of the node PE1 via the message receiving unit 36.

On the other hand, in the node PE 1, the “Ack” message is output from the local access control unit 25 to the home access control unit 27.

Home access control unit 27 of node PE1
Receives a total of 127 identical “Ack” messages (the destination node is “0x001”, the type is “Ack”, the address is “0x0040030010”, the mid is “1”, and the requesting node number is “0x002”). FIG.
Processing is performed according to the flowchart of FIG. When the home access control unit 27 of the node PE1 receives the first “Ack” message, it operates as follows.

First, in step S151, the address of “0x000600” (22 bits from the 28th bit to the 7th bit of the address “0x0040030010” added to the message) in the directory memory 31 is accessed, and data such as the state is read. . The read state, the holding node information, the holding format, and the number of rewrites have been updated to “UP”, “0x07f”, “10” (counter format), and “0” in Phase 3, respectively, and their values are read. Since the type of the received message is “Ack”, the read state is “UP”, the holding node type is the counter format, the holding node information is 0x07f, and it is not uncached, the processing type is determined according to the table in FIG. Is “CC”, the next state of the block is “UP”, the holding node operation is “dec”, the number of write-back updates is unchanged,
No message to be output. Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000006” in the directory memory 31 is stored in the state “UP” and the holding node information is “0”.
x07e ", the holding format is" 10 ", and the rewrite update count is updated to" 0 ". Since the message being processed is not a message with block data, writing to the main memory 30 is not performed. Upon completion of the above processing, the process advances to step S153.

In the step S153, the processing type is “C
C ", the process ends.

[0268] Thus, the home access control unit 27 of the node PE1 ends the processing of the "Ack" message.

The home access control unit 27 controls each node P
The "Ack" message from Ei is processed in the same manner as described above, and the process of reading the value of the directory memory 31 and updating it to a value obtained by subtracting "1" from the holding node information is performed. This process is continued until the value obtained by subtracting “1” from the read holding node information is not “0x000”, that is, not uncached. However, when it becomes uncached, that is, when it receives the last 127 “Ack” message, it operates as follows.

First, in step S151, the address of “0x000600” (22 bits of the 28th to 7th bits of the address “0x0040030010” added to the message) in the directory memory 31 is accessed, and the data such as the state is read. . The read state, the holding node information, the holding format, and the number of write-backs are each "U
P "," 0x001 "," 10 "(counter format),
It has been updated to "0" and its value is read. Since the type of the received message is “Ack”, the read state is “UP”, the holding format is the counter format, the holding node information is “0x001”, and the data is uncached, the processing is performed according to the table in FIG. Type is "C
"A", the next state of the block is "M", the holding node operation is "set", the number of write-back updates is unchanged, and the type of message to be output is determined to be "CmpSh". Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000600” in the directory memory 31 is stored in the state “M” and the holding node information is “0x000600”.
002 ”, the storage format is updated to“ 01 ”(pointer format), and the number of write-backs is updated to“ 0 ”. Since the message being processed is not a message with block data, writing to the main memory 30 is not performed. Upon completion of the above processing, the process advances to step S153.

In the step S153, the processing type is “C
A ”, the flow proceeds to step S144.

[0273] In step S154, a "CmpSh" message is generated. The “CmpSh” message has a destination node number “0x002”, a message type “CmpSh”, and an address “0x0040030”.
010 ", mid is" 1 ", and the requesting node number is" 0 ".
x002 ”(step S144). The output destination of this message is the destination node number "0x00
Since the node number “2” does not match the node number “0x001” of the node PE1, the message transmission unit 35 is used.

The home access control unit 27 of the node PE1 ends the processing of the “Ack” message.

(5) Processing of CmpSh Message The “CmpSh” message is sent to the local access control unit 25 of the node PE2 via the message transmitting unit 35 of the node PE1, the interconnection network 10, and the message receiving unit 36 of the node PE2. Is output.

The “CmpSh” message (the destination node number is “0x002” and the message type is “CmpSh”
Sh ”, the address is“ 0x0040030010 ”, m
The local access control unit 25 of the node PE2 receiving the id “1” and the request source node number “0x002”)
The operation is performed as follows according to the flowchart of FIG. First, in step S131, the request management table 24
The information of the entry “1” (= mid) is read, the access type is store, and the address is “0x004003”.
0010 ", and store data. Upon completion of the above processing, the process advances to step S132.

In step S132, since the message is not a message with block data, the flow advances to step S133.

In step S133, since the message is not the “Ncmp” message, the flow advances to step S137.

[0279] In step S137, 64 bits of data at the address "0x06002" in the cache memory 21 are converted into
A process for updating to the store data obtained from the request management table 24 is performed. Also, the request management table 24
The effective bit to "0" in the "1" (= mid) entry of
Is written, and the entry is deleted. Also,
According to the table of FIG. 11B, the data of the address “0x0600” in the tag memory 22 is “D”, the tag address is “0x00400” (the 39th to 20th bits of the address 0x0040030010 obtained from the request management table). 20 bits). Also, it outputs mid to the processor and notifies that the memory access of id = "1" has been completed. After completing the above processing,
Proceed to step S138.

In step S138, since the received message is “CmpSh” (step S138), the local access control unit 25 proceeds to step S161 in the flowchart of FIG. 11A, and starts a write-back process.

In the step S141, it is checked whether or not a write-back is requested from the write-back selecting means 26 (step S161). In the initial state, the address holding means 111 (two-entry FIFO
In O), nothing is registered, and the write-back request unit 112 has not issued a request. Therefore, the process proceeds to step S146.

In step S146, the local access control unit 25 sends the address “0x0040030001” to the address registration unit 110 of the write-back block selection unit.
Request registration of "0". The address registration unit 110 that has received the request registers the upper 33 bits of the address in the address holding unit 111. Thus, the address holding means 1
11 is in a state where one “0x000800600” is registered.

[0283] Thus, the local access control unit 25 ends the processing of the received "CmpSh" message.

[0284] At this stage, "0x0040030000"
Up to the address “0x40003007f”, the latest data is in a state where it exists only in the cache memory 21 of the node PE2.

[0285] 4. Phase 4 The processor 20 of the node PE1 receives the address “0x004
When load access is performed to “0040000”, the same processing as the operation shown in phase 1 is performed. Next, the processor 20 of the node PE2 sends the address “0x0”.
When the load access is performed for “0400400000”, the same processing as the operation shown in phase 2 is performed.
Next, the processor 20 of the node PE2 outputs the address “0”.
When a store access is made to “x0040040010”, the same processing as the operation shown in phase 3 is performed. Thus, the address “0” is stored in the address holding unit 111 of the write-back block selecting unit 26 of the node PE2.
x0000800 "(address" 0x0040
030010) and 0x8000
0800 ”(the upper 33 bits of the address“ 0x0040040000 ”).

The same processing as described above is performed at another address (for example, “0x0040050000”), a “CmpSh” message is generated from the store access performed by the node PE2, and the local access control unit 25 of the node PE2 executes the process shown in FIG. It is assumed that the processing is performed according to the flowchart of FIG. At this time, two addresses are registered in the address holding means 111 of the write-back selection means 26,
In full condition. Therefore, the write-back request unit 112
Indicates to the local access control unit 25 the address “0x
0040030000 "(" 0x000800600 "
(40 bits in which 7 bits “0” are added to the lower part of 33 bits).

(1) Processing of CmpSh Message The local access control unit 25 receives and processes the “CmpSh” message, and proceeds to step S141.

In step S141, the write-back requesting means 112 of the write-back selecting means 26 has requested write-back, so that the flow advances to step S142.

In the step S142, the address “0x004003000” output from the write-back requesting means 112 is output.
The tag memory 22 uses 13 bits (0x0600) from the 19th bit to the 7th bit of "0" as an index.
To obtain the status and the tag address (step S162). In the phase 3, the state and the tag address are updated to "D" and "0x00400", respectively, and the values are read. Upon completion of the above processing, the process advances to step S143.

In step S 143, the status is “D”, and the tag address and the upper 20 bits of the address “0x0040030000” output by the write-back requesting means 112.
Since the bits match, it is determined that write-back is necessary, and the flow advances to step S144.

In step S144, the data of the corresponding block is read from the cache memory 21 in order to perform write back. The block data to be read is “0x06
It is 64 bits × 16 entries = 128 bytes from the address “000” to the address “0x0600f”. The read block data is added to the generated “RpBack” message. The generated “RpBack” message has a destination node number of “0x001” (the upper 10 bits of the address output by the write-back block request unit 112).
G), the message type is “RpBack”, the address is “0x0040030000”, the requesting node number is “0x002”, the mid is an arbitrary value, and the block data is the block data read from the cache memory 21 earlier. The output destination of the “RpBack” message is the message transmitting unit 35 because the destination node number “0x001” and the node number “0x002” of the node PE2 are different. Further, the data of the address “0x0600” in the tag memory 22 is updated to the state “S” and the tag address to the tag address read in step S142. Upon completion of the above processing, the process advances to step S145.

In step S145, a request is made to the address deletion means 113 of the write-back block selection means 26 to delete the address requested by the current write-back request means 112. Upon receiving the request, the write-back request means 112
From the address holding means 111, the address “0x8000
0600 ”is deleted. As a result, one address “0x8000800” is registered in the address holding unit 111. Upon completion of the above processing, the process advances to step S146.

[0293] In step S146, the local access control unit 25 causes the address registration unit 110 of the write-back block selection unit 26 to send the message "C
It is requested to register the address “0x0040050000” of “mpSh”. Upon receiving the request, the address registration unit 110 stores the address “0” in the address holding unit 111.
x0040050000 "upper 33 bits" 0x00
0800A00 ”is registered. As a result, the address holding unit 111 stores “0x000800800” and “0
x000800A00 "is registered (step S166).

[0294] Thus, the local access control unit 25 of the node PE2 ends the processing of the "CmpSh" message.

(2) Processing of RpBack Message The “RpBack” message output from the local access control unit 25 of the node PE2 to the message transmitting unit 35 is passed to the message receiving unit 36 of the node PE1 through the interconnection network 10. It is. The message receiving unit 36
When receiving the “RpBack” message, it outputs it to the home access control unit 27.

The above “RpBack” message (the destination node number is “0x001”, and the message type is “RpBack”
Back "and the address is" 0x004003000 "
The home access control unit 27 of the node PE1 that has received “0”, the request source node number “0x002”, and the block data) operates as follows according to the flowchart of FIG.

First, in step S151, the address of “0x000600” (22 bits from the 28th bit to the 7th bit of the address “0x0040030000” added to the message) in the directory memory 31 is accessed, and the data such as the state is read. . In phase 3, the status, the holding node information, the holding format, and the number of times of rewriting are updated to “M”, “0x002”, “01” (pointer format), and “0”, respectively, and the values are read. Since the type of the received message is “RpBack” and the read state is “M”, according to the table in FIG. 13, the processing type is “CC”, the next state of the block is “C”, and the holding node operation is “C”. none ", and the number of rewrites is determined to be" +1 ". When the above process is completed,
Proceed to step S152.

In step S152, based on these information, the data at the address “0x000600” in the directory memory 31 is stored in the state “C” and the holding node information is “0x000600”.
002 ”, the holding format is“ 01 ”(pointer format), and the number of write-backs is updated to“ 1 ”. Here, since the message is a message with data, “0x000600” in the main memory is used.
The block data added to the message is written from address “0” to address “0x00000600f”. As a result, a state is established in which the latest data also exists in the main memory 30 of the node PE1. When the above processing ends, the flow advances to step S153.

[0299] In step S153, the processing type is "CC".

[0300] Thus, the home access control unit 27 of the node PE1 ends the processing of the "RpBack" message.

At this stage, “0x0040030000”
Up to the address “0x004003007f”, the latest data exists in the main memory 30 of the node PE1 in addition to the cache memory 21 of the node PE2.

[0302] In the subsequent operation, the node PE1 returns "0x" again.
The explanation will be made separately for the case where the load access is made to the address “0040030000” and the case where the load access is not made. First, the operation when performing load access will be described.

[0303] 5. Phase 5A (1) Processing of Load Access The processor 20 of the node PE1 receives the address “0x004”.
It is assumed that load access is performed to id 00300000 with id = "0".

The local access control unit 25 having received the memory access performed by the processor 20 operates as follows according to the flowchart of FIG.

First, in step S111, the tag memory 2
2 address “0x0600” (the 19th bit to the address “0x0040030000” obtained from the processor 20)
The data of the seventh bit (13 bits) is read. The status and tag address are "I" and "0x0"
0400 ”and the value is read. From this value, the processing type is “AA”, the message to be issued is “BlkRdSh” according to the table in FIG.
The next state of the block is determined to be "I". Upon completion of the above processing, the process advances to step S112.

In step S112, if the processing type is "A
A ”, the flow proceeds to step S113.

In step S113, a message is generated and output and registered in the request management table 24. The destination node number of the message to be generated and output is "0
x001 ”(10 bits from the 39th bit to the 30th bit of the address“ 0x0040030000 ”), the message type is“ BlkRdSh ”, and the address is“ 0x00 ”.
4030000 ", the mid is" 0 "(= id), and the request source node number is" 0x001 ". Further, both the destination node number and the node number of the node PE1 are “0”.
x001 ”, the output destination is the node PE1.
Of the home access control unit 27. In addition, the valid bit is set to “1”, the access type is loaded, and the address is set to “0x00400300000” in the “0” (= id) entry of the request management table 24. Upon completion of the above processing, the process advances to step S118.

At step S118, "0" in the tag memory
The data of the entry at the address "x0600" and the state is "I"
The tag address is 0x00400 (address 0x00
Bits 40030000 from bit 39 to bit 20
Bit).

With the above, the local access control unit 25 of the node PE1 ends the received load access processing.

(2) Transmission of BlkRdSh message The above “BlkRdSh” message (the destination node number is “0x001”, and the message type is “BlkRdS”
h ", the address is" 0x0040030000 ", mi
(d is “0” and the requesting node number is “0x001”).
The operation is performed as follows according to the flowchart of FIG.

First, in step S151, an address of “0x000600” (22 bits of the 28th to 7th bits of the address “0x00400300000” added to the message) in the directory memory 31 is accessed, and data such as a state is read. . The read state, the holding node information, the holding format, and the number of times of rewriting have been updated to “C”, “0x002”, “01” (pointer type), and “1” in phase 4, respectively, and their values are read.
The type of the received message is "BlkRdSh",
Since the read state is “C”, the holding format is the pointer format, the holding node information is “0x002”, and it is not uncached, the processing type is “CB” and the next state of the block is “C” according to the table in FIG. , The holding node operation is “add”, the number of write-backs is “0”, and the type of message to be output is “CmpDatSh”. Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000600” of the directory memory 31 is stored in the state “C” and the holding node information is “0x000600”.
“001”, the holding format is “00” (course vector), and the number of rewrites is updated to “0”. Upon completion of the above processing, the process advances to step S153.

In step S153, if the processing type is “C
B ”, the flow proceeds to step S155.

In the step S155, the addresses “0x0006000” to “0x000600f” of the main memory 30 are set.
The block data of 64 bits × 16 entries = 128 bytes up to the address is read, added to the message to be generated, and output. This message indicates that the destination node number is "0".
x001 ”and the type of message is“ CmpDatS
h ", the address is" 0x0040030000 ", mi
d is “0”, the requesting node number is “0x001”, and the block data is the block data read out in step S155 (step S14).
5). The output destination of this message is the local access control unit 25 of the node, since the destination node number matches the node number of the node PE1.

As described above, the home access control unit 27
The processing of the “BlkRdSh” message ends.

(3) Processing of CmpdatSh Message The above “CmpDatSh” message (the destination node number is “0x001”, and the message type is “CmpDatSh”
Sh ”, the address is“ 0x0040030000 ”, m
(id is “0” and the requesting node number is “0x001”).
Operates as follows according to the flowchart of FIG.

First, in step S131, the information of the entry “0” (= mid) of the request management table 24 is read, and the access type is load and the address is “0”.
x0040030000 "is obtained. Upon completion of the above processing, the process advances to step S132.

[0318] In step S132, since the message is a message with block data, the flow advances to step S135.

In the step S153, the address “0x0600f” from the address “0x06000” of the cache memory 21 is obtained.
The block data added to the message is written at the address. Upon completion of the above processing, the process advances to step S136.

In step S136, since the access type is load, in step S139, 64-bit data of the address "0x06000" is read from the cache memory 21 and id =
It is passed as response data to the memory access of “0”. This completes the memory access. Further, data with the valid bit set to “0” is written to the “0” -th entry of the request management table, and the entry is deleted.
In addition, the state of the address “0x0600” and the tag address of the tag memory are updated to “S” and “0x00400” according to the table of FIG.

[0321] Thus, the local access control unit 25 of the node PE1 ends the processing of the received "CmpDatSh" message.

At this stage, “0x0040030000”
Up to the address “0x004003007f”, the latest data is stored in the cache memory 21 and the main memory 30 of the node PE1, and the cache memory 21 of the node PE2.
Is present.

By writing back the block from the cache memory 21 of the node PE2 to the main memory 30 of the node PE1, a load access from a node other than the node PE2 (here, the node PE1) already holding data can be performed. Data can be read directly from the main memory 30 of the node PE1 and a response can be made. If the write-back is not performed, the node PE2 is passed through the node PE1.
Is requested to write back the data, and the data is returned after receiving the write back.

As is apparent from the above, the multiprocessor system according to the first embodiment of the present invention has the effect of reducing the load access latency.

Next, an operation in the case where a node other than the node PE2 does not access the block including the address "0x0040030000" and only the node PE2 repeatedly accesses the block will be described.

[0326] 6. Phase 5B (1) Processing of Store Access The processor 20 of the node PE2 re-addresses the address “0x”.
The operation when store access is performed with id = “1” in “0040030020” will be described.

The local access control unit 25 having received the memory access performed by the processor 20 operates as follows according to the flowchart of FIG.

First, in step S111, the tag memory 2
2, the data at the address "0x0600" is read. In phase 4, the state is “S” and the tag address is “0x00”.
400 ", and its value is read. The access type is store, and the tag address is "0x0
0400 "and the state is" S ".
According to the table of (b), the processing type is determined to be "AA", the type of message to be output is determined to be "Upgrade", and the next state of the block is determined to be "S". Upon completion of the above processing, the process advances to step S112.

At step S112, if the processing type is "A
A ”, the flow proceeds to step S113.

[0330] In step S113, a message is generated and output and registered in the request management table 24. The destination node number of the message to be generated and output is "0
x001 ”(10 bits from the 39th bit to the 30th bit of the address“ 0x0040030020 ”), the message type is“ Upgrade ”, and the address is“ 0x00 ”.
40030020 ", the mid is" 1 ", and the requesting node number is" 0x002 ". Since the destination node number and the node number of the node PE2 are different, the output destination is the message transmitting unit 35. At this time, the valid bit is "1", the access type is store, the address is "0x0040030020", and the store data are written in the "1" (= id) number entry of the request management table 24. Upon completion of the above processing, the process advances to step S118.

At step S118, "0" in the tag memory
The data of the entry at the address “x0600” and the state is “S”
The tag address is “0x00400” (address “0
x0040030020 "(20 bits from the 39th bit to the 20th bit).

With the above, the local access control unit 25 of the node PE2 ends the store access processing.

(2) Processing of Upgrade Message The above “Upgrade” message is sent to the message transmission unit 35 of the node PE2, the interconnection network 10, and the node PE1.
Is sent to the home access control unit 27 of the node PE1 via the message receiving unit 36 of

The above "Upgrade" message (the destination node number is "0x001", and the message type is "U
pgrade "and the address is" 0x0040030002 "
0, mid is “1”, and the requesting node number is “0x00”
2 "), the home access control unit 2 of the node PE1
7 operates as follows.

First, in step S151, the address “0x000600” (22 bits of the 28th to 7th bits of the address “0x0040030020” added to the message) in the directory memory 31 is accessed, and data such as the state is read. . In Phase 4,
The status, the holding node information, the holding format, and the number of times of rewriting have been updated to “C”, “0x002”, “01” (pointer format), and “1”, respectively, and the values are read. The type of message I received was "Upgrade"
Since the read state is “C”, the holding format is the pointer format, the holding node information is “0x002”, the cache is uncached, and the number of write-backs matches the threshold “1”. ), The processing type is “CA”, the next state of the block is “M”, the holding node operation is “none”, the number of write-back updates is unchanged, and the type of message to be output is determined to be “CmpEx”.
Upon completion of the above processing, the process advances to step S152.

In step S152, based on these information, the data at the address “0x000600” of the directory memory 31 is stored in the state “M” and the holding node information is “0x000600”.
002 ”, the holding format is“ 01 ”(pointer format), and the number of write-backs is updated to“ 1 ”. Since the message being processed is not a message with block data, writing to the main memory 30 is not performed. Upon completion of the above processing, the process advances to step S153.

In the step S153, the processing type is “C
A ”, the flow proceeds to step S154.

In step S154, a “CmpEx” message is generated. The “CmpEx” message has a destination node number of “0x002”, a message type of “CmpEx”, and an address of “0x0040030”.
020 ", mid is" 1 ", and the requesting node number is" 0x
002 ”(step S144). The output destination of this message is the destination node number “0x002”
And the node number “0x001” of the node PE1 does not match. As described above, the home access control unit 27 of the node PE1
The processing of the “pgrade” message ends.

(3) Processing of CmpEx Message The “CmpEx” message is sent to the local access control unit 25 of the node PE2 via the message transmitting unit 35 of the node PE1, the interconnection network 10, and the message receiving unit 36 of the node PE2. Is output.

The above “CmpEx” message (the destination node number is “0x002” and the message type is “CmpEx”
Ex ”, address is“ 0x0040030020 ”, m
The local access control unit 25 of the node PE2 receiving the id “1” and the request source node number “0x002”)
The operation is performed as follows according to the flowchart of FIG. First, in step S131, the request management table 24
The information of the entry 1 (= mid) is read, the type of access is store, and the address is “0x00400300”.
20 ", and store data. Upon completion of the above processing, the process advances to step S132.

In step S132, since the message is not a message with block data, the flow advances to step S133.

In step S133, since the message is not an NCmp message, the flow advances to step S137.

In the step S137, “0x06004” of the cache memory 21 (address “0x00400”
17 from the 19th bit to the 3rd bit of “30020”
A process is performed to update the 64-bit data of the address (bit) to the store data obtained from the request management table 24. Also, “1” (= mi) in the request management table
d) Write data with the valid bit set to "0" in the number entry and delete the entry. Further, the data at the address “0x0600” of the tag memory 22 is stored in the state “D” according to the table of FIG. 11B and the tag address is “0x004”.
00 ”(bits 39 to 20 of the address“ 0x0040030020 ”obtained from the request management table 24)
20 bits). Also, it outputs mid to the processor and notifies that the memory access of id = "1" has been completed. Upon completion of the above processing, the process advances to step S138.

The message received in step S138 is neither "CmpSh" nor "CmpDatSh".

Thus, the local access control unit 25 of the node PE2 ends the processing of the received “CmpEx” message.

At this stage, “0x0040030000”
Up to the address “0x40003007f”, the latest data is in a state where it exists only in the cache memory 21 of the node PE2.

When the threshold value is set to “1”,
If there is no access from another node between receiving the write-back from the same node PEi (here, the node PE2) once and writing to the next node PE2, the main memory 30 of the node PE1 Data has not been rewritten and has been removed from the target block.

Also, by setting the threshold value, it is possible to change how many times the write-back is received and whether the write-back block is excluded from the target.

As described above, according to the present embodiment, it is possible to prevent unnecessary writing back to the main memory 30 from occurring.

The present invention is not limited to what has been described in the first embodiment, and various modifications are possible.

Next, a second embodiment of the present invention will be described.

FIG. 14 is a block diagram showing the configuration of a loosely-coupled multiprocessor system 1 'according to the second embodiment of the present invention.

In this embodiment, a multiprocessor system having no directory memory 31 can be constructed. In this case, the information stored in the directory memory 31 may be stored in a certain area (directory area) of the main memory 30. The access performed by the home access control unit 27 to the directory memory 31 is realized by accessing the directory area of the main memory 30.

Since the remaining structure is the same as that of the first embodiment shown in FIG. 1, the same reference numerals as those in FIG. 1 are used.

The types and structures of the messages in the first and second embodiments can be modified in various ways as long as the messages can correctly transmit the processing request and response between the nodes PEi. In particular, for a request (access request, etc.) between the same nodes, a predetermined signal is transmitted via a signal line provided in the node without taking the form of a message, and the request is transmitted. Is also good.

In the first and second embodiments, the functions of the local access control unit 25 and home access control unit 27 included in the consistency maintenance control unit 16 are as follows.
Each may be realized by any of the following.

(A) Main memory 30 by processor 20
Execution of the processing program stored in the instruction cache (or the program stored in the instruction cache).

(B) Processor 20 and main memory 30
(Or instruction cache)
Execution of a processing program stored in a dedicated memory by a dedicated subprocessor.

(C) Dedicated hardware configured according to logic for realizing the function of each module.

The multiprocessor system shown in the first and second embodiments has 1024 nodes PE0 to PE10 connected to each other via one interconnection network 10.
23. However, in this embodiment, the number of nodes is arbitrary. Further, a redundant configuration having a plurality of interconnection networks may be adopted. In this case, the plurality of interconnected networks can be used for system failure countermeasures.

As described above, according to this embodiment, not only can the device configuration be simplified, but at the same time, the main memory 30
Unnecessary writing back to the server can be prevented.

Although the embodiments of the present invention have been described above, it is needless to say that the present invention is not limited to the above embodiments, and that various modifications are possible.

[0363]

As described above, according to the present invention,
The following remarkable effects are obtained.

(1) When the processor writes data to the shared block, the cache memory of the node is occupied. Such a block is written back to the main memory by the write-back block selecting means and the local access control unit of the node. With this function, when a processor of another node performs load access to the block, the block can be read from the main memory instead of the cache memory of the occupied node, so that the load access latency can be reduced.

(2) The directory memory has information indicating whether it is shared or not. Based on that information,
A response message transmitted by the home access control unit that has received the write request to the node that has issued the request has information indicating whether or not the request was shared. The local access control unit that has received the response message determines whether or not to be the target of the block for performing write-back selected by the write-back block selecting means, depending on whether or not the block has been shared. With the above function, it is possible to prevent the writing back from being performed on the blocks that are not shared.

(3) In the directory memory, if the number of times of rewriting has been received and the number of nodes actually holding the block is one even if the node indicates that the block is shared, information that can specify that node To have. Also, the home access control unit is provided with a threshold value that determines how many times the write back is allowed. Based on this information, even if the home access control unit that received the write request indicates that the state of the block is shared, only the node that issued the request holds the block. If the threshold value and the number of times of rewriting are the same, the response message is provided with information indicating that it is not shared, and is excluded from the target of the rewriting block selecting means. With the above function, it is possible to detect that the shared block is no longer shared with the passage of time, to prevent useless writing back, and to prevent an increase in messages due to writing back.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a loosely-coupled multiprocessor system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a node shown in FIG.

3A is a diagram illustrating a request message transmitted from a node that has performed a memory access to a node that holds data in a main memory, and FIG. 3B is a diagram illustrating a node that holds data in a main memory. FIG. 7C is a diagram showing a request message transmitted from a node that holds a copy of the data in the cache memory to a node that holds a copy of the data in the cache memory from the node that holds the copy of the data in the cache memory. It is a figure which shows the report message transmitted, and (d) is a figure which shows the memory access completion message transmitted to the node which performed memory access from the node which holds data in the main memory.

FIG. 4 is a diagram showing an internal configuration of a write-back block control unit. .

5A is a diagram illustrating a configuration of a message with block data, and FIG. 5B is a diagram illustrating a configuration of a basic message.

FIG. 6 is a diagram showing a state of a directory memory, a tag memory, and the memory block.

FIG. 7 is a diagram showing a state transition of a node according to the present embodiment and its constituent elements, a main memory and a cache memory.

FIG. 8A is a flowchart illustrating a process executed by a local access control unit in response to a memory access output by a processor, and FIG. 8B is a flowchart illustrating a process type and a message type in the process of FIG. , A table showing the relationship of the next state of the block, etc.

FIG. 9A is a diagram showing IntvS out of messages output by the home access control unit or the message receiving unit;
9 is a flowchart showing processing executed by the local access control unit when three types of messages, h, IntvEx, and Upgrade, are received. (b) is a processing type, a message type, and a block type in the processing of (a). It is a table which shows the relationship of the next state etc.

FIG. 10 shows messages output by the home access control unit or the message receiving unit, CmpDatSh,
CmpDatEx, CmpSh, CmpEx, NCmp
10 is a flowchart illustrating a process executed by the local access control unit when the five types of messages are received.

FIG. 11 (a) shows a message output from the home access control unit or the message receiving unit, wherein CmpD
atSh, CmpDatEx, CmpSh, CmpE
If you receive five types of messages, x and NCmp,
Flow showing processing executed by local access control unit
FIG. 10B is a chart, and FIG. 10B and FIG.
3 is a table showing the relationship between the processing type, the type of message, the next state of the block, and the like in the processing of FIG.

12A is a flowchart illustrating a process executed by a home access control unit, and FIG. 12B illustrates a relationship between a process type, a message type, a next state of a block, and the like in the process of FIG. It is a table.

FIG. 13 is a flowchart showing the process of the flowchart of FIG. 12 (a). 4 is a table showing four pieces of information indicating whether or not they match, a state of a block stored in a directory memory, an operation on holding node information, an operation on the number of times of writing back, a processing type, and a message type.

FIG. 14 is a block diagram showing a configuration of a loosely coupled multiprocessor system according to a second embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a conventional multiprocessor system.

FIG. 16A is a diagram illustrating a state in which data copies exist in main memories of a plurality of nodes, and FIG.
FIG. 14 is a diagram illustrating a state in which a copy of data exists only in the main memory of one node.

FIG. 17A is a diagram illustrating a state where valid data in which consistency is maintained does not exist in cache memories of a plurality of nodes; FIG. 17B illustrates a state where a valid copy of data exists and FIG. 9C is a diagram illustrating a state in which valid data may possibly exist in the cache memory of another node; FIG.
Is a diagram showing a state in which a valid copy of data exists only in one node, no valid copy exists in the cache memory of another node, and the data of the main memory and the data of the cache memory are different. .

[Explanation of symbols]

 PE0-PEn-1, PE0'-PEn-1 'node 10 interconnection network 16 consistency maintenance control unit 20 processor 21, 42 cache memory 22 tag memory 24 request management table 25 local access control unit 26 write-back block selection means 27 Home access control unit 30, 41 Main memory 31 Directory memory 35 Message transmission unit 36 Message reception unit 40 Node PEi 55 Consistency control unit 110 Address registration unit 111 Address holding unit 112 Write-back request unit 113 Address deletion unit 1

Claims (11)

[Claims] 1. A multiprocessor system comprising a plurality of nodes connected to each other via an interconnection network, wherein each of the plurality of nodes includes a main memory for storing data, and any one of the plurality of nodes. A cache memory in which a part of data stored in a main memory included in the cache memory is stored and which can be accessed at a higher speed than the main memory; a processor that issues a data access request; Within the cache memory, manages the copy state of the data in the cache memory, and when the processor performs load and store access to the data at a predetermined address, the node according to the memory access. A function to exchange messages between PEi, change their status, and transfer data Has a coherence maintenance control unit having, a,
A tag memory in which a state of data stored in the cache memory is stored; a directory memory in which a state of data stored in the main memory is stored; An access request, a request or a response issued by a home access control unit included in the plurality of nodes is received, and a process necessary for maintaining consistency is performed on the cache memory and the tag memory. A local access control unit that responds to an access request; and a request or response issued by the local access control unit included in the plurality of nodes. A home access control unit that performs processing and issues a request or response to the local access control unit; A request management table having an entry corresponding to the maximum number of memory accesses that can be issued simultaneously by the processor; and a write-back that writes to a shared block and stores the block occupied by the cache memory. A multiprocessor system comprising: a block selecting unit. 2. The multiprocessor system according to claim 1, wherein said write-back block selecting means registers an address specified by said local access means, and an address registered by said address registering means. Address holding means for holding a plurality of addresses, selecting one from a plurality of addresses stored in the address holding means and outputting the selected address to the local access control unit,
A multi-function device comprising: a write-back request unit for requesting data write-back; and an address deletion unit for deleting an entry selected by the write-back request unit in accordance with an instruction from the local access control unit. Processor system. 3. The multiprocessor system according to claim 1, wherein said local access control unit reads a block stored in said write-back block selecting means from said cache memory and issues a write-back request to data to said home access. A multiprocessor system which issues the data to the main memory in response to a data writeback request issued to the control unit and issued by the local access control unit. 4. The multiprocessor system according to claim 3, wherein the local access control unit receives a data write request access to the processor, issues a write request to the home access control unit, and issues the write request. Receiving, from the state of the data held in the directory memory indicating whether the data is shared by a plurality of nodes, determine whether the data is in a shared state,
The determination result is added to a response issued to the local access control unit, a response is returned to the local access control unit, and the local access control unit receives the response and determines whether the plurality of nodes are in a shared state. A multi-processor system which determines whether or not there is registration in the block in the write-back block selecting means based on the following. 5. The multiprocessor system according to claim 4, wherein the home access control unit has a threshold value for limiting the number of times of write-back permitted, and when receiving a write request from the local access control unit, A multiprocessor system characterized by determining whether a block is actually shared based on the information. 6. The multiprocessor system according to claim 5, wherein the home access control unit has a threshold for limiting a permitted number of times of write-back, and receives a write request from the local access control unit. A multiprocessor system, which determines whether or not a block is actually in a shared state based on the threshold value and information held in the directory memory. 7. The multiprocessor system according to claim 6, wherein the directory memory includes a node that actually holds a block even if the number of times of writing back and the data are in a shared state are one node. A multiprocessor system characterized by having information capable of identifying a multiprocessor. 8. A multiprocessor system comprising a plurality of nodes connected to each other via an interconnection network, wherein each of the plurality of nodes includes: a main memory for storing data; A cache memory in which a part of the data stored in the main memory included in any of them is stored, which can be accessed at a higher speed than the main memory; a processor that issues a data access request; and data in the main memory. In the system, manages the copy state of the data in the cache memory, and when the processor performs load and store access to data at a predetermined address, Exchange messages between the nodes PEi to change their state or transfer data. A coherence maintaining controller having a function, wherein the coherence maintaining controller includes: a tag memory in which a state of data stored in the cache memory is stored; an access request from the processor; Receiving a request or response issued by the home access control unit of the node, performs processing necessary for maintaining consistency in the cache memory or the tag memory, and sends a response to the access request to the processor. A local access control unit to perform, upon receiving a request or a response issued by the local access control unit included in the plurality of nodes, performs a process necessary for maintaining consistency in the main memory or the directory memory, A home access control unit for issuing a request or a response to the local access control unit; A request management table having an entry corresponding to the maximum number of memory accesses, and a write-back block selecting means for writing the shared block and storing the block occupied by the cache memory. A multiprocessor system. 9. The multiprocessor system according to claim 1, wherein the local access control unit and the home access control unit included in the coherence maintaining control unit include a processing program in which the processor is stored in the main memory. The multiprocessor system is realized by executing the following. 10. The multiprocessor system according to claim 1, wherein the local access control unit and the home access control unit included in the consistency maintaining control unit are dedicated sub-processors provided separately from the processor. Is realized by executing a program stored in the main memory. 11. The multiprocessor system according to claim 1, wherein the local access control unit and the home access control unit included in the coherence maintaining control unit each have a dedicated logic for realizing a function of a module. A multiprocessor system comprising dedicated hardware configured according to the following.