JP2000252998A - Method and system for converting address - Google Patents

Abstract

PROBLEM TO BE SOLVED: To identify a message even in a protocol layer where the message cannot substantially be identified. SOLUTION: In the address conversion method where a transmission-side transmitter supporting a prescribed protocol layer decides a conversion destination address in a state of an address field of an output protocol unit signal corresponding to an input protocol unit signal on the basis of a conversion source address in a state of an address field used for selection of a transmission path of the input protocol unit signal, only part of the address field set in the protocol unit signal for selecting the transmission path is converted as transmission path selection data, and the other part is converted into message identification data used to identify a message transmitted between the transmission-side transmitter and a receiver-side transmitter connected to the former transmitter and the conversion destination address is composed of the transmission path selection data and the message identification data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation method and apparatus, for example, an ATM (Asynchronous Transfer).
r Mode: Asynchronous transfer mode) This mode can be applied to a case where cell routing information is converted for each network node transmitting the ATM cell.

[0002]

2. Description of the Related Art Conventionally, as this type of address translation method and apparatus, there are those described in the following documents 1 and 2.

Reference 1: "ATM Internetworking" (Nikkei BP Publishing Center) Translated by Anthony Alles Tsunemi Shitara Reference 2: "Communication Protocol Encyclopedia" (ASCII) Supervised by Eimatsu Kasano Multimedia Communication Study Group As described in FIG. 2, the ATM network is composed of a group of ATM switches. These ATM switches are interconnected by point-to-point ATM links or ATM interfaces.

The ATM switch supports two types of interfaces, a user network interface (UNI) and a network node interface (NNI), depending on the location on the network.

In an ATM network, it is necessary to prepare a virtual circuit (virtual circuit) on the ATM network prior to data transfer.

[0006] The ATM circuit includes a virtual path identified by a virtual path identifier (VPI),
There are two types of virtual channels identified by a set of VPI and virtual channel identifier (VCI).

[0007] A virtual path (VP) is a virtual path.
Channels (VC), each of which is a common V
Transparently exchanged over ATM networks based on PI. However, both VPIs and VCIs have only local implications on particular links, ie, between particular switches on an ATM network.

Therefore, in each switch, VC
The I and VPI routing bits are converted for convenience.

[0009] In order to perform such local address translation, the ATM switch usually has its own local translation table (LT table).

[0010] Although various forms can be considered for the configuration of the LT table, at least the recognized VCI or VP is recognized.
It has a function of searching for a connection value on the output side based on the connection value on the input side of the cell received on the I-link. The connection value on the output side specifies the output port of the connection and the VC on the output side, so that the ATM switch sends out the cell in response to this.

As a method of using the LT table, PVC is used.
(Permanent Virtual Connections: fixed destination connection) and SVC (Switched Virtual Connections: selected destination connection).

In general, PVC is a setting for a connection used for a medium to long term such as a dedicated line, and all ATMs existing on a transmission path between a source ATM system and a destination ATM system are used. Done for switches. Normally, PVC requires an external setting operation manually by a network administrator.

[0013] In the PVC, once the setting is made, the path (the ATM switch to be transmitted) cannot be automatically selected again unless a new setting operation is performed.

On the other hand, SVC is a connection automatically established by a signaling protocol.
There is no need for manual operation at the time of establishment such as PVC, and when not in use, the connection can be released or the route can be selected again according to the state of the network.

In both cases, 16-bit VCs can be operated for each VP in principle.

For example, VPI is 8 in case of UNI.
Bit, NNI is represented by a 12-bit numerical value,
CI is represented by a 16-bit numerical value. Therefore one V
P can accommodate up to 65,536 VCs.

[0017]

However, in a system using the entire resource area of the VCI consisting of 16 bits for each VPI as described above, the resource allocation of the VCI must be managed for each VP. There is a problem that the amount becomes large.

For example, in the case of UNI, the 8-bit V
PI and the 16-bit 24-bit routing bits LT table handle equally all made of VCI, since the input bit pattern of 2 ²⁴ kinds must accommodate, that becomes hardware large That is.

In such a large-scale hardware, 2
^{Although 24} types of packets can be identified, this is excessive in the actual state of the network, and it is rare that a combination of a large number of identifiers is necessary in an actual system. Often wasted.

Also, the number of bits that can be used for the VCI is limited depending on the device to be connected.
There is also a problem that this restriction needs to be taken into account when assigning data.

The above-mentioned packet means a message which is a set of a series of ATM cells transmitted in time series, and one connection is occupied on the link during a period in which one packet is transmitted. .

[0022]

According to a first aspect of the present invention, there is provided an address field used for selecting a transmission path of an input protocol unit signal by a transmitting side transmitting apparatus supporting a predetermined protocol layer. In the address translation method for determining a destination address which is a state of an address field of an output protocol unit signal corresponding to the input protocol unit signal based on a source address which is in a state of the protocol unit signal, the protocol unit signal is selected for the transmission path selection. Only part of the address field set above is converted as transmission path selection data, and the other part is transmitted between the transmitting side transmitting apparatus and the receiving side transmitting apparatus connected thereto. The message is converted as message identification data used to identify the message In a di-identification data, and wherein the configuring the destination address.

Further, according to a second aspect of the present invention, the transmitting-side transmitting apparatus supporting a predetermined protocol layer is configured such that a transmitting-side transmitting apparatus, based on a translation source address which is a state of an address field used for selecting a transmission path of an input protocol unit signal, In an address translation device for determining a translation destination address which is a state of an address field of an output protocol unit signal corresponding to the input protocol unit signal, the address translation device sets the address field set on the protocol unit signal for selecting the transmission path. , Only part of the data is converted as transmission path selection data, and the other part is used as message identification data used for identifying a message transmitted between the transmitting side transmitting apparatus and the receiving side transmitting apparatus connected thereto. After conversion, the transmission path selection data and the message identification data
It is characterized by comprising an address processing means constituting the translation destination address.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION (A) Embodiment Hereinafter, an address translation method and apparatus
An embodiment will be described with an example in which the present invention is applied to L (ATM Adaptation Layer) 5.

In AAL3 / 4, MID (Message ID)
AAL connection identification (CS
Message identification), but in AAL5, A
There is no MID for AL3 / 4.

Therefore, the following first to first corresponding to AAL5
In the fourth embodiment, the source and destination user terminals are identified (transmission path selection) using only the VPI, for example, by software, and the VCI is assigned for each packet (that is, for each connection). A function corresponding to the MID is provided.

The VPI processing by the software is as follows:
It may be 1 VPI per subscriber (1 ATM terminal).

(A-1) Configuration of the First Embodiment FIG. 2 shows the address converter 10 of the present embodiment. The address conversion unit 10 is mounted in an ATM switching device such as a CLS (connectionless server) or ATM switches 11 and 13 shown in FIG. 4 and functions as a VC management mechanism.

The edge nodes 14 and 15 in FIG. 4 are UNI devices corresponding to, for example, a private branch exchange (PBX) and a router, and have a multiplexing / demultiplexing function and an exchange function for ATM cells. Then, switching (exchange) of ATM cells, that is, address conversion, is performed along with overhead reconfiguration such as selection and distribution of overhead of the SDH frame in the UNI device.

Therefore, each of the ATM terminals 16 and 17 accommodated in the edge nodes 14 and 15 may be plural.

In this case, the address conversion unit 10 can be mounted on the edge nodes 14 and 15 as well. these,
The edge nodes 14 and 15, the CLSs 11 and 12,
The ATM switch 13 and the like are collectively called a transmission device.

In FIG. 2, the address conversion unit 10
CI management unit 21, VCI management RAM 22, free VC
It comprises an I-head register 23 and an empty VCI end register 24.

The VCI management unit 21 has a VCI management RAM 2
2. A control device that manages VCI resources by controlling the free VCI start register 23 and the free VCI end register 24.

The VCI resource is a VCI accommodated by the address conversion unit 10.

The management of VCI resources depends on the set VC
There is an aspect similar to bandwidth management in that packets are transmitted above and occupy the link bandwidth (link transmission capacity),
This is a concept different from bandwidth management in that a bandwidth is not occupied during a period in which an ATM cell constituting the packet is not transmitted even during a period in which a certain VC is set.

The VCI management RAM 22 is a temporary table corresponding to the LT table, the details of which are shown in FIG.

The temporary table is a PDU (Protocol)
When transferring a Data Unit, it is generally used to temporarily hold information necessary to assemble a PDU from a cell and to add the information to the cell.

In FIG. 3, the RAM (random access memory) 22 displays a 32-bit address (hexadecimal notation) in total, but the upper 16 bits (corresponding to VPI, all "0") Is processed by the above-mentioned software, and is not processed by the address conversion unit 10, so that it has a 16-bit address space of only the lower 16 bits (corresponding to the VCI of the UNI and NNI). become.

Each memory address has a VCI of 1
16-bit data is stored corresponding to 6 bits. The 16 bits correspond to the maximum available VCI.

In the initial setting of this embodiment, the address and the data are associated with each other by setting the data of each address to a value obtained by adding "+1" to the corresponding address.

The free VCI head register 23 is a 32-bit register, and its lower 16 bits are bits processed by the address conversion unit 10 of the present embodiment. The value of the lower 16 bits stored in this register corresponds to the VCI of the connection (message) set next.

The free VCI final register 24 is also a 32-bit register, the lower 16 bits of which are processed by the address conversion unit 10. The value of the lower 16 bits stored in this register is the V of the released connection.
Corresponds to CI.

The operation of this embodiment having the above configuration will be described below. (A-2) Operation of First Embodiment First, as described above, the VCI management RA
A value obtained by adding 1 to the corresponding address is stored in each address in M22. However, the final address 0000 FF
Nothing is written to FF (H). FIG. 3 is a memory map in this initial state.

The initial value of the empty VCI head register 23 is 0000 0000 (H), and the initial value of the empty VCI final register 24 is 0000 FFFF (H) (VC
(The last address of the I management RAM 22).

The operation of the address converter 10 is shown in the flowchart of FIG. FIG. 1A shows an operation of allocating a VCI (setting a connection), and FIG.
The operation of releasing I (release of connection) is shown.

In FIG. 1 (A), V
When the CI assignment processing is instructed, first, the VCI management unit 2
1 reads out the free VCI start register 23 and the free VCI last register 24 (601) and compares them (6).
02).

If they match, it is determined that there is no space,
Error processing is performed (606).

When error processing is performed, no VCI is allocated, so that the packet is transmitted to the ATM switch 13 having the address translator 10 and the CLS 1
It will not be transmitted beyond 1, 12, etc.

However, this match not only occurs in hardware when all 16 bits of the VCI are actually in use, but may also exist due to, for example, a loss of the VCI in the first cell of the packet or a transmission error. Not VP
When the reception of I (VCI) or the recognition of congestion, etc., the software may operate to make them coincide.

In some cases, the software may be used to limit the number of VCIs used.

The VCI management unit 21 assigns the value recorded in the free VCI head register 23 as an output VCI to an area corresponding to the VCI of the routing field of each ATM cell constituting the packet whose transmission has started. (Write) (603).

The contents of the processing performed in step 603 are notified to the above-mentioned software managing the VPI as necessary. This is because it is usually more reasonable to have the authority to determine the final routing field in relatively slow but sophisticated software.

Next, the VCI management unit 21 reads the address of the VCI management RAM 22 corresponding to the value recorded in the free VCI head register 23 (604), and rewrites the free VCI head register 23 with the value recorded at that address. (605).

On the other hand, FIG. 1 showing the VCI release procedure
The flow (B) is started by the software instructing release of the VCI.

In FIG. 1B, first, the VCI management unit 21 reads the value recorded in the free VCI final register 24 (607), and then releases it to the address of the VCI management RAM 22 corresponding to the value. The value of the VCI is written (608).

Finally, the release processing is completed by rewriting the value of the free VCI final register to the value of the VCI to be released (609).

By these processes, unused VCIs are managed in a chain, and double use of VCIs in use can be prevented.

It is not necessary to be released in the order in which they are allocated.
Will be chained in the order in which they are registered, and will be newly assigned.

(A-3) Effect of First Embodiment As described above, according to the present embodiment, AA without MID
Even when the L5 is used, the transfer processing in units of packets can be easily managed by providing the VCI with the function of the MID.

The VPI is separately managed by software or the like, and only the VCI resource is centrally managed by the address conversion unit 10, so that the address conversion unit is compared with the case where the address conversion is performed using all bits of the VPI and VCI. 10 can reduce the amount of hardware.

(B) Second Embodiment In the first embodiment, the VC which is performed mainly by software
By limiting the number of uses of I in advance by changing the set value of the register, it is characterized by being implemented mainly by hardware, flexibly, and with a low load on software.

The other points, such as providing the VCI with a function corresponding to the MID and using 1 VPI per subscriber (1 ATM terminal), may be the same as in the first embodiment.

(B-1) Configuration and Operation of the Second Embodiment FIG. 5 shows the address conversion unit 30 of this embodiment. The transmission device on which the address translator 30 is mounted is the CLS1 of FIG.
For example, the address conversion unit 10 may be exactly the same as the address conversion unit 10 of the first embodiment.

Referring to FIG. 5, the address conversion unit 30 includes a pointer bit 71, a VCI management unit 72, a VCI management RAM 73, an unused number register 74, a read pointer register 75, and a write pointer register 76. ing.

The VCI management unit 72 is provided with the VCI management unit 2.
This is a control device similar to 1.

The configuration of the VCI management RAM 73 itself is as follows.
As shown in FIG. 6, the hardware is exactly the same as the VCI management RAM 22.

In this embodiment, VCI resource management is performed by the VCI management RAM 73, the read pointer register 75, and the write pointer register 76. V
The CI management RAM 73 stores available VCI values.

As shown in FIG. 7, a read pointer 75 and a write pointer 76 are
This register specifies the above address.

The address specified by the read pointer register 75 is the address where the VCI to be next used (read) is stored, and the address specified by the write pointer register 76 is the next released (written) VC.
This is the address where I is stored.

The pointer bit 71 is the read pointer 7
5 is a flip-flop (FF) for determining whether all VCI resources are available or empty when no VCI resources are available when the position (address specification) of the write pointer 76 matches.

This coincidence can occur when no VCI resources are used and all VCI resources are available, and when all VCI resources are in use and no more can be used.

The initial value of the pointer bit 71 is “1”, which is cleared to “0” when the read pointer 75 is added (incremented) and set to “1” when the write pointer 76 is added (incremented). .

The value of the unused number register 74 is the available V
Shows the number of CIs. This value is the value of the write pointer 76
And the value of the read pointer 75. Although the value of the unused number register 74 is one bit larger than the value of the read pointer / write pointer, the most significant bit indicates the value of the pointer bit when the values of the write pointer 76 and the read pointer 75 match. Otherwise, it is "0".

At the time of initialization, the maximum number of VCIs to be used are written in the VCI management RAM 73. For example, as shown in FIG. 6, data having the same value as the lower 16 bits of the address may be written to the corresponding address.

In the present embodiment, by setting the value of the read pointer 75 and the value of the write pointer 76, the range of usable VCI values and the number of simultaneously usable VCIs can be set.

FIG. 8 is a flowchart showing the operation of the present embodiment.

In FIG. 8B, the VCI assignment process instructed by the software is performed as follows.

First, from the information in the unused number register 74, V
The CI management unit 72 determines whether there is a free VCI (10
01).

If there is no free VCI, it is regarded as a VCI hunt error and subjected to error processing (1006).

The contents of the error processing are the same as the error processing in the first embodiment described above.

If there is a free VCI, the VCI management unit 72
First reads the read pointer register 75 (100
2) The data stored in the VCI management RAM 73 is read using the value recorded in the read pointer register 75 as an address (1003).

Next, the data read from the RAM 73 is assigned (written) as an output-side VCI to an input packet, and the contents are notified to necessary function blocks such as the above-mentioned software for managing the VPI ( 1004).

As soon as the allocation is completed, the read pointer is incremented by one and rewritten.
Is set to "0" (1005).

On the other hand, the VCI release procedure also shown in FIG. 8A and also started by the instruction of software is as follows.

First, the value recorded in the write pointer register 76 is read (1007), and the VC to be released is stored in the address of the VCI management RAM 73 specified by the value.
The value of I is written (1008).

Finally, the write pointer 76 is incremented by one and rewritten, and at the same time, the pointer bit 71 is set to "1" (1009).

The VCI management RAM 73 does not necessarily need to be set with continuous values, and can freely set a value to be used.

(B-2) Effects of the Second Embodiment As described above, according to the present embodiment, exactly the same effects as those of the first embodiment can be obtained.

In addition, according to the present embodiment, the register 7
By changing the set value of 5,76, the available VC
The number and the range of values of I can be set flexibly, and the management of the unused number is easy.

Further, in the present embodiment, as in the first embodiment, the values of the registers 23 and 24 used for address specification are replaced by the data stored in each address of the VCI management RAM to be addressed. Since the chain system is not used, the relationship between the address of the VCI management RAM and the data stored in the VCI management RAM is not strict, and the VCI value to be stored in the VCI management RAM in the initial setting can be freely selected.

Further, in the present embodiment, it is only necessary to secure entries for the maximum number of VCIs to be used.
It is possible to save the memory capacity of the management RAM.

(C) Third Embodiment In the first and second embodiments, a single and fixed VCI
The number of digits (the number of bits) of the value can be changed as needed.

The other points, such as providing the VCI with a function corresponding to the MID and using 1 VPI per subscriber (1 ATM terminal), may be the same as in the first embodiment.

(C-1) Configuration and Operation of Third Embodiment FIG. 9 shows an address conversion unit 40 of this embodiment. The transmission device on which the address translator 40 is mounted is the CLS1 of FIG.
For example, the address conversion unit 10 may be exactly the same as the address conversion unit 10 of the first embodiment.

In FIG. 9, the address conversion unit 40
Except for the CI management unit 102, for low VCI and high VC
It has two components for I.

That is, for low VCI, low VC
I management RAM 103, low VCI unused number register 104, low VCI read pointer register 105
, Low VCI write pointer register 106, l
owVCI pointer bit 107, high
For VCI, high VCI pointer bit 101,
It comprises a high VCI management RAM 108, a high VCI unused number register 109, a high VCI read pointer register 110, and a high VCI write pointer register 111.

Among them, the VCI management RAM 103, 10
8 corresponds to the VCI management RAM 73 of the second embodiment, the unused number registers 104 and 109 correspond to the unused number register 74, and the read pointer registers 105 and 1
10 corresponds to the read pointer register 75; write pointer registers 106 and 111 correspond to the write pointer register 76;
Since 101 corresponds to the pointer bit 71, its detailed description is omitted.

It is assumed that the VCI management RAMs 103 and 108 storing available VCI values are set in different areas on the same RAM.

The VCI management unit 102 is a control device similar to the VCI management unit 21.

In this embodiment, the VCI resource management is performed by the low VCI management RAM 103, the low VCI read pointer register 105, the low VCI write pointer register 106, the high VCI management RAM 108,
high VCI read pointer register 110, high
This is performed by the hVCI write pointer register 111.

A low VCI is a VCI represented by a number of bits smaller than 16 bits, that is, a VCI having an effective bit number of less than 16, and all higher bits are defined as "0".

The high VCI is a VCI expressed using all 16 bits other than the low VCI, that is, a VCI having 16 effective bits. That is, hig
In the hVCI, one bit is always set to "1" in a bit higher than the low VCI.

For example, when returning the released VCI to the management RAMs 103 and 108, the VCI management unit 102 pays attention to the upper two bits of the VCI and sets the relevant two bits to "01", "10", and "11". If any, hi
The control may be returned to the ghVCI management RAM 108, and if the corresponding two bits are “00”, the control may be returned to the low VCI management RAM 103.

However, in the present embodiment, the top four
Paying attention to the bit, the bit concerned is "0001" to "111".
1 "(1 to FH), high VCI management RAM
108, and if "0000" (0H),
It is to be returned to the wVCI management RAM 103.

Therefore, in this embodiment, FIG.
As shown in (A) and (B), the same VCI is never stored in the RAMs 103 and 108.

FIG. 10A shows the initial setting state of the VCI management RAM 103, and FIG.
2 shows the initial setting state of.

FIG. 11A shows the initial state of each register of the read pointer 105 and the write pointer 106. FIG. 11B shows the initial state of each register of the read pointer 110 and the write pointer 111. Is shown.

As the initial setting, the high VCI management RA
The value of the VCI to be used is written in the M108 / low VCI management RAM 103.

A high VCI read pointer register 110 and a high VCI write pointer register 1
11 · low VCI read pointer register 105 · l
In each of the owVCI write pointer registers 106,
By setting the value of the read pointer and the value of the write pointer, the range of usable VCI values and the number of simultaneously usable VCIs can be set.

FIG. 12 shows the VCI assignment process, and FIG.
4 shows an operation flowchart of a CI release process.

In the VCI allocating process shown in FIG. 12, first, it is determined whether or not the transmission apparatus on the receiving side needs VCI bit restrictions (401). In this step, if it is determined that the bit constraint is necessary, the low VCI allocation processing is performed, and if it is determined that the bit restriction is unnecessary, the high VCI allocation processing is performed.

When entering the high VCI allocation processing, first, the presence or absence of an empty high VCI is checked (408), and if not, an error processing (403) is performed.

The contents of the error processing are the same as those in the first embodiment.

The presence or absence of an empty high VCI is determined by the high V
This is performed by checking the CI unused number register 109. If there is a free high VCI, the VCI management unit 10
2 is a high VCI read pointer register 110
(409), and using the value recorded in the read pointer register 110 as an address, the high VCI management RAM
The VCI management unit 102 reads the data stored in 108 (410).

For the packet whose transmission has started, R
A place where the value read from the AM 108 is allocated as an output side VCI and information is required (for example, the software).
Is notified (411).

As soon as the assignment is completed, the read pointer 110 is incremented by one and rewritten.
The I pointer bit 101 is set to "0" (412).

On the other hand, in the low VCI allocation processing, first, the presence or absence of an empty low VCI is checked (402), and if not, an error processing (403) is performed.

The presence / absence of an empty low VCI is determined by the low VCI
This is performed by checking the unused number register 104. If there is a free low VCI, the VCI management unit 102 first reads the low VCI read pointer register 105 (404), and reads the low VCI management RAM 103 using the value recorded in the read pointer register 105 as an address (405).

For the packet whose transmission has started, R
The value read from the AM 103 is assigned as an output VCI, and is notified to a place where information is required (406).

As soon as the assignment is completed, the read pointer is incremented by one and rewritten, and at the same time, the low VCI pointer bit 107 is set to "0" (407).

In the VCI release processing of FIG. 13, the VCI value to be released is first identified (501), and hi is released.
If it is recognized as ghVCI, high VCI release processing is performed.
If the low VCI is recognized, a low VCI release process is performed.

When entering the high VCI release processing, first, h
The value recorded in the high VCI write pointer register 111 is read (502), and the value of the VCI to be released is written to the high VCI management RAM 108 using the value as an address (503).

Finally, the high VCI write pointer 1
11 is added and rewritten, and at the same time, the high VCI pointer bit 101 is set to "1" (504).

When the low VCI release process is started, first, the value recorded in the low VCI write pointer register 106 is read (505), and then the value of the VCI to be released is written to the low VCI management RAM 103 using the value as an address (506). .

Finally, the low VCI write pointer 10
6 is added and rewritten, and at the same time, the low VCI pointer bit 107 is set to "1" (507).

(C-2) Effects of the Third Embodiment According to the present embodiment, exactly the same effects as in the second embodiment can be obtained.

In addition, according to the present embodiment, it is possible to connect to a transmission device in which the number of bits of the VCI is limited (receiving side).

(D) Fourth Embodiment In the flowchart of the third embodiment, branching is performed depending on whether or not there is a restriction on the number of bits of the VCI. Therefore, the number of simultaneously set connections increases, and high VC
I is in use, but the low VCI is not used.
In some cases, it is better to be able to use this instead of CI.

This embodiment makes this possible from the viewpoint of increasing the usage efficiency of the limited VCI resources.

The other points, such as providing the VCI with a function corresponding to the MID and using 1 VPI per subscriber (1 ATM terminal), may be the same as in the first to third embodiments.

(D-1) Configuration and Operation of Fourth Embodiment The hardware of the address conversion unit of this embodiment is exactly the same as the address conversion unit 40 of FIG. 9 of the third embodiment. The description is omitted.

Further, the address conversion unit 4 of the present embodiment
0 may be exactly the same as the address conversion unit 10 of the first embodiment, such as the CLS 14 in FIG.

The operation of the present embodiment is substantially similar to that of the third embodiment.

The operation of this embodiment differs from the operation of the third embodiment only in the VCI assignment process.

The VCI allocating process of this embodiment is described in FIG.
Is shown in the flowchart of FIG.

In FIG. 14, first, it is determined whether or not the transmission apparatus on the receiving side requires VCI bit restrictions (601), and if necessary, low VCI allocation processing is performed, and if not, high VCI allocation processing is performed.

When entering the high VCI allocation process, first, it is checked whether or not there is a free high VCI (608).

As already described in the third embodiment, h
The difference between the high VCI and the low VCI is only the four most significant bits, and there is no overlap between both VCIs.

Therefore, VCI has a bit constraint
When a packet having high VCI is sent to a transmission device that should receive wVCI, for example, VCI “0000”
H and “1000H” cannot be distinguished, and “0001H” and “1001H” cannot be distinguished. Therefore, a problem may occur in the transmission device or in the network.

However, a transmission apparatus which does not have a bit restriction on VCI and receives high VCI is provided with low VCI.
Even if a packet having a CI is transmitted, for example, the most significant bit “0”, which was invalid in the third embodiment, is only processed as a valid bit, so that no inconvenience occurs in the transmission apparatus. .

Alternatively, in order to avoid any inconvenience,
It suffices to make the software of the transmission apparatus aware that the VCI whose upper 4 bits are "0000" may be handled.

Paying attention to this point, the process of step 608 (branch without empty high VCI) of this embodiment is performed. Therefore, in the present embodiment, error processing is not performed when there is no empty high VCI as in the third embodiment.

The presence or absence of an empty high VCI is determined by the
This is performed by checking the CI unused number register 109.

If there is an empty high VCI, the VCI management unit 102 first reads the high VCI read pointer register 110 (609), and reads the read pointer register 11
The high VCI management RAM 108 is read using the value recorded in 0 as an address (610).

For the packet whose transmission has started, R
The value read from the AM 108 is assigned as the output VCI, and is notified to the place where information is required (611).

As soon as the assignment is completed, the read pointer 110 is incremented by one and rewritten.
The I pointer bit 101 is set to "0" (612).

Including the branch at step 608,
When entering the wVCI assignment processing, first, it is checked whether or not there is a free low VCI (602).
Perform 3).

Whether there is an empty low VCI is determined by the low VCI
This is performed by checking the unused number register 104. If there is a free low VCI, the VCI management unit 102 first reads the low VCI read pointer register 105 (604), and reads the low VCI management RAM 103 using the value recorded in the read pointer register 105 as an address (605).

For the packet whose transmission has been started, R
The value read from the AM 103 is assigned as the output VCI, and is notified to the place where the information is required (606).

As soon as the assignment is completed, the read pointer 105 is incremented by one and rewritten, and at the same time, the low VCI
The pointer bit 107 is set to "0" (607).

As described above, the VC of this embodiment
The I release processing is performed in the same manner as the other operations in the VC of the third embodiment.
Since it is exactly the same as the I release processing, the description thereof is omitted.

(D-2) Effects of the Fourth Embodiment According to the present embodiment, it is possible to obtain exactly the same effects as in the third embodiment.

In addition, according to the present embodiment, by setting priorities to VCIs that can be used, it is possible to prevent VCI that can be used only on the restricted side from being depleted. Efficiency can be increased.

(E) Other Embodiments In the above embodiment, the routing bits of the ATM cell are divided by VPI and VCI, and the connection is set by using the VCI. Absent. For example, only a part of the VPI is used to identify the destination terminal (transmission path selection).
It is also possible to use the remaining bits of the PI and VCI for connection selection.

Similarly, it is possible to selectively use a certain range of VCIs and other VCIs.

When there are a plurality of types of devices in which the number of bits of the VCI is restricted, the management area (for example, RAM area) of the VCI may be divided for each restricted range, and queues or chains may be provided by that number. .

The present invention is not limited to VCI,
It can also be used as a management method for other communication identifiers such as I, MID, and entry number of a temporary table. Possible factors for assigning these identifiers include when a new subscriber is registered, when a new call is established, and when a new PDU is transmitted.

Further, in the above description, the VPI is processed by software, but the VPI may be processed by hardware.

Furthermore, the functions of the hardware of the first to fourth embodiments may be borne by software having the same functions.

That is, according to the present invention, a transmitting-side transmitting apparatus supporting a predetermined protocol layer determines whether or not an input protocol unit signal based on a conversion source address which is a state of an address field used for selecting a transmission path of a signal. The present invention can be widely applied to an address conversion method and apparatus for determining a conversion destination address which is a state of an address field of an output protocol unit signal corresponding to a protocol unit signal.

[0161]

As described above, according to the present invention, message identification can be performed even in a protocol layer that cannot originally identify a message.

Further, since it is sufficient to secure the necessary resources, the hardware scale can be reduced.

Further, resource management becomes flexible and easy.

[Brief description of the drawings]

FIG. 1 is a flowchart according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of the first embodiment.

FIG. 3 is a memory map according to the first embodiment.

FIG. 4 is a schematic diagram of a network according to first to fourth embodiments.

FIG. 5 is a block diagram illustrating a configuration of a second embodiment.

FIG. 6 is a memory map according to the second embodiment.

FIG. 7 is a schematic diagram illustrating addressing according to the second embodiment.

FIG. 8 is a flowchart according to a second embodiment.

FIG. 9 is a block diagram illustrating a configuration of a third embodiment.

FIG. 10 is a memory map according to a third embodiment.

FIG. 11 is a schematic diagram illustrating addressing according to the third embodiment.

FIG. 12 is a flowchart according to a third embodiment.

FIG. 13 is a flowchart according to a third embodiment.

FIG. 14 is a flowchart according to a fourth embodiment.

[Explanation of symbols]

10, 30, 40... Address conversion units, 21, 72, 10
2 ... VCI management unit, 22, 73, 103, 108 ... VC
I management RAM, 23 ... Free VCI head register, 24 ...
Empty VCI last register.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Dr. Takenoshita, Inventor 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Morio Yoshida 1-7-112 Toranomon, Minato-ku, Tokyo Inside Electric Industry Co., Ltd. (72) Inventor Naoya Hashimoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Maki Tanigawa 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Within Telephone Co., Ltd. (72) Inventor Toshinori Ikegami Nippon Telegraph and Telephone Co., Ltd. 3-2-1, Nishi-Shinjuku, Tokyo Nippon Telegraph and Telephone Co., Ltd. Telephone Co., Ltd. F-term (reference) 5B014 HB01 5K030 GA05 HA10 HB14 HB16 HB29 HD09 JT02 KA05 LB05 5K033 AA04 CB01 CB09 CC01 DB12 EC03 9A001 BB01 BB03 BB04 CC06 CC07 FF03 JJ2 5 JJ27

Claims (10)

[Claims] 1. A transmitting-side transmission device that supports a predetermined protocol layer converts an input protocol unit signal into an input protocol unit signal based on a conversion source address which is a state of an address field used for selecting a transmission path of the input protocol unit signal. In an address conversion method for determining a conversion destination address which is a state of an address field of a corresponding output protocol unit signal, only a part of the address field set on the protocol unit signal for selecting the transmission path is transmitted. Converted as path selection data, and another part is converted as message identification data used to identify a message transmitted between the transmitting side transmitting apparatus and the receiving side transmitting apparatus connected thereto, and The conversion destination address is constituted by the selection data and the message identification data. Address conversion method for the butterflies. 2. The address translation method according to claim 1, wherein the transmission-side transmission device is provided with a storage memory for storing the message identification data, and the conversion destination address of the protocol unit signal at the start of the next message transmission. The head register storing the corresponding storage memory address for storing the message identification data is stored in the corresponding storage memory address addressed by its own stored value each time the message transmission starts. Is read, the message identification data replaces the stored value of itself, and at the end of the next message transmission, the final register storing the corresponding storage memory address storing the message identification data released is Stores the stored value in the message identification data that is released at the end of each message transmission. Address conversion method, wherein the address is replaced with a data. 3. The address translation method according to claim 1, wherein the transmission-side transmission device is provided with a storage memory storing the message identification data, and the storage memory is used to read out the message identification data to be used. The stored value of the read address pointer for addressing is changed each time the message transmission is started, and the stored value of the write address pointer for addressing the storage memory is written in order to write the released message identification data to the storage memory. An address translation method characterized in that the address is changed every time transmission is completed. 4. The address translation method according to claim 3, wherein when the pointer values of the read address pointer and the write address pointer match, the message identification data in the storage memory is in an all-in-use state or at least one of them is in use. An address conversion method characterized by determining whether the address is not used. 5. The address conversion method according to claim 3, wherein the number of unused message identification data is displayed by comparing pointer values of the read address pointer and the write address pointer. Conversion method. 6. The address translation method according to claim 1, wherein the number of bits of an address field processed by the transmitting side transmission device is different from the number of bits of an address field processed by the receiving side transmission device. In order to cope with the case, an address translation method characterized in that message identification data having different numbers of effective bits is prepared in the transmitting side transmission device. 7. The address translation method according to claim 6, wherein the message identification data having different numbers of effective bits is set so as not to overlap each other, and the reception corresponding to the message identification data having a large number of effective bits is performed. If the message identification data having a large number of effective bits is already in use for the side transmission device, the message identification data having a small number of effective bits is used instead. 8. A transmission-side transmission device that supports a predetermined protocol layer transmits an input protocol unit signal to an input protocol unit signal based on a conversion source address which is a state of an address field used for selecting a transmission path of the input protocol unit signal. An address translation device for determining a translation destination address which is a state of an address field of a corresponding output protocol unit signal, wherein only a part of the address field set on the protocol unit signal for transmission path selection is transmitted. Converted as path selection data, and another part is converted as message identification data used to identify a message transmitted between the transmitting side transmitting apparatus and the receiving side transmitting apparatus connected thereto, and The selection data and this message identification data make up the address that constitutes the translation destination address. Address converting apparatus comprising: a processing unit. 9. The address translation device according to claim 8, wherein a storage memory for storing the message identification data, and a message storage for storing message identification data to be a conversion destination address of the protocol unit signal at the start of the next message transmission. The memory address is stored, and every time message transmission is started, when the message identification data stored in the corresponding storage memory address addressed by its own storage value is read out, the corresponding message identification data is used. A head register for replacing a stored value and a corresponding storage memory address for storing message identification data to be released at the end of the next message transmission are stored. And a final register to be replaced with data. Address translation device. 10. The address translation device according to claim 8, wherein a storage memory for storing the message identification data, and a storage value for addressing the storage memory at each start of message transmission in order to read out the message identification data to be used. And a write address pointer for changing a storage value for addressing the storage memory each time a message transmission is completed, in order to write the released message identification data to the storage memory. Address translation device.