JP2000251470A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of the operation for obtaining continuous data stored in plural memory banks from an arbitrary position. SOLUTION: A buffer writing circuit 52 writes the data, which are read from a synchronous memory 7 by a burst access while switching memory banks, into a buffer memory in a word unit. The memory 7 stores continuous data for every burst access continuous access word number while successively switching the memory banks. A buffer writing circuit 52 inputs address information A9 and A2 to A0, that specify memory banks and a burst access leading word position, changes the generating order of writing addresses in accordance with the number of words to the leading word specified by address information against the leading position in the range of the word number corresponding to the bank number magnification of the continuous access word number by the burst access, changes the data language from the memory bank into an original data arrangement order and writes the data into a data buffer and executes a writing control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of memory banks and a burst-accessible synchronous memory access circuit, for example, a synchronous DRAM (hereinafter abbreviated as SDRAM) access circuit. In particular, the present invention relates to a technique which is effective when applied to the efficiency of processing for continuously accessing a fixed amount of data such as digitized image data and audio data from an arbitrary address position continuously.

[0002]

2. Description of the Related Art In recent years, there have been many systems for digitizing image data and audio data and performing signal processing.
M is often used. These audio data and image data have continuity. During the processing or when outputting the result, the continuous data is read from the SDRAM,
It is necessary to write to DRAM.

On the other hand, the SDRAM has a feature that it is easy to continuously access data continuous with a column address due to its configuration. That is, a column address counter preset with a column address supplied from the outside is provided, and continuous access can be performed by incrementing the counter internally. Such an access is also called a burst access. However, if an attempt is made to change the row address during continuous access, an idle time is generated when the row address is changed. That is, if the row address is changed, the operation time of the row address system becomes necessary in addition to the operation time of the column address system, and it takes a considerable amount of time before data is read out to the outside. To avoid this problem, the SDRAM has a plurality of memory banks (hereinafter also simply referred to as banks).

Generally, an SDRAM has a plurality of banks such as an A bank and a B bank, and by using these banks alternately, it is possible to efficiently perform an access. FIG. 10 exemplifies the timing when the A bank and the B bank of the SDRAM are alternately accessed. In the drawing, the bank is switched every four words, and CL (cass latency: the number of memory cycles from the determination of the column address to the determination of the read data) is an example of the access timing of three cycles. First, the bank A is selected by the active command (ACTV) and a row address (ROW) is given, and then the read command (RE
AD) to specify the column address (COL), so that four words of data A0 to A3
Are sequentially read. Subsequently, an active command and a read command specifying the bank B are input, and four words of data are read from the bank B. Here, the designation of the column address by the row address active command (ACTV) and the read command (READ) to the bank B can be issued during the access of the bank A. As described above, a command is issued in advance to the other bank during access to one bank, so that the A bank,
By alternately accessing the B banks, it is possible to efficiently access the memory without wasting access time.

[0005]

FIG. 11 shows an SDRAM.
An example in which continuous data is stored using the bank configuration of FIG. For example, continuous data corresponding to one line of an image is stored in banks A and B every eight words. Data 0 to data 7 shown in the figure are stored in bank A, and subsequent data 8 to data 15 are stored in bank B. Similarly, the following data is alternately stored in the A bank and the B bank every eight words.

When reading continuous data such as image data stored in an SDRAM or the like, there is a request to read a certain amount of data from an arbitrary position. For example, when an area of an image is displayed while being scrolled, image data necessary for display is read from an arbitrary position.

The inventor has studied a method of obtaining stored data from an arbitrary position when continuous data is stored alternately in a plurality of banks.

For example, if the start position of the required image data coincides with the boundary of the bank of the SDRAM storing the image, the above-mentioned A is used as illustrated in FIG.
SDRA by alternately accessing bank B and bank B
Data can be read without unnecessary access to M. For example, when image data 0 to image data 15 are continuously read, data 0 to data 7 in bank A and data 15 from data 8 in bank B may be read.

On the other hand, the start position of necessary image data is SD
When the data is shifted from the bank boundary of the RAM, as illustrated in (2) and (3) of FIG. 12, image data necessary for the read data is obtained. That is, as shown in (2) of FIG. 12, when burst access is performed in units of eight words, the read start data of necessary data is set to 3
Then, the first 3 data read from the data 0 in the A bank are
The word is treated as invalid data, and then 8
Then, 8 words of the A bank are read out, 5 words of the subsequent A bank are treated as invalid data, and read access is performed even though there is no read data in the B bank. As described above, when the read start data does not exist at the word boundary, reading is performed at the word boundary, invalid data is discarded, and only valid data is obtained. Therefore, the amount of access to the SDRAM requires twice the amount of data to be read. In this example, the bank B is read empty after reading the data 18 of the bank A. However, such an access need not be performed originally. In order to unify the entire access method, such an empty read is performed by accessing from the A bank and terminating the access in the B bank, or by performing the reverse access in consideration of accesses from other SDRAMs. It will be introduced.

Similarly, as shown in FIG. 12 (3), when the read start data is 13, when the access start from the A bank is secured, the idle read is first performed from the A bank. Then, three words out of eight words in the B bank are read as valid data, and subsequently, the A bank read and the B bank read are performed. In this case, as in the example of (2), the amount of access to the SDRAM requires twice the amount of data to be read.

As described above, when reading stored data continuously utilizing the SDRAM bank configuration, useless access occurs to required read data access depending on the read start position, and the SDRAM access band is not used. The width (for example, the number of words of continuous access data in burst access) may be wasted.

Further, in consideration of reducing unnecessary memory access as much as possible, as shown in FIGS. 13 (1) to 13 (3), it is necessary to change the read method every time according to the required data position. Is also possible. That is, when the beginning of necessary data is on a bank boundary, burst access may be performed in units of 8 words for each bank as described in (1) of FIG. When the start position of the necessary data is data 3, as shown in (2) of FIG. 13, a burst access to the bank A is started from the position of data 3, and a stop command is issued at the position of data 6. Then, a burst access is started at the position of data 8 for the bank B, a stop command is inserted at the position of data 15, and a burst access is finally started at the position of data 16 for the bank A. Then, a stop command is inserted at the position of the data 18. In this method, the access is stopped at an arbitrary position in the middle using the full page burst mode. However, since the access stop position is different every time the access is performed, the load on the CPU that issues the stop command is too large. It is not practical.
The same applies to (3) in FIG. 13, but in this case, A
Neither can access from the bank be guaranteed.

An object of the present invention is to provide a semiconductor integrated circuit capable of improving the efficiency of an operation of obtaining continuous data stored in a plurality of memory banks from an arbitrary position.

Another object of the present invention is not to increase the number of memory accesses and to increase the burden on an access control entity when obtaining continuous data stored in a plurality of memory banks from an arbitrary position. It is an object of the present invention to provide a semiconductor integrated circuit having an access control function capable of suppressing the problem.

Still another object of the present invention is to make sure that even when continuous data stored in a plurality of memory banks is obtained from an arbitrary position, memory access always starts at a certain bank and ends at a certain bank. It is an object of the present invention to provide a semiconductor integrated circuit having an access control function that can be realized.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

A semiconductor integrated circuit (1) according to the present invention is a memory access control circuit (1) capable of burst access in synchronization with a clock signal and capable of controlling access to a synchronous memory (7) having a plurality of memory banks. 5).

The memory access control circuit (5) according to the first aspect of the present invention comprises a buffer memory (51) and a buffer memory (51) for switching data read out by burst access while switching memory banks from the synchronous memory in data word units. A buffer write circuit (52) for generating a write address for writing to the memory. The synchronous memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access. The buffer write circuit receives first address information (A9) for specifying the memory bank and second address information (A2 to A0) for specifying the position of the first data word of burst access. The order in which write addresses are generated in accordance with the difference in the number of data words from the start position in the range of the number of data words corresponding to the number of banks equal to the number of access data words to the position of the start data word specified by the first and second address information And writing control is performed by changing the arrangement of the data words from the memory banks to the data buffer in an order (a prescribed order) corresponding to the arrangement order of the continuous data.

It is assumed that continuous data starting from the position of the data word specified by the first and second address information is read from the memory bank by a fixed number of data words. At this time, the head position in the range of the number of data words corresponding to the number of banks equal to the number of continuous access data words by burst access can be grasped as a boundary position of the memory bank. The head position of the data actually read from the memory bank has an offset corresponding to the number of data words from the boundary position of the memory bank to the position of the head data word specified by the first and second address information. . The buffer write circuit uses the offset to change the order in which write addresses are written to the data buffer so that the data words from the memory bank can be written to the data buffer in the above-described order.

Thus, when continuous data stored in a plurality of memory banks is obtained from an arbitrary position,
The memory access can be started from a fixed bank and terminated at a fixed bank, without increasing the number of memory accesses and without increasing the burden on an access control entity such as a CPU. It is possible to improve the efficiency of the operation of acquiring data from an arbitrary position.

A memory access control circuit according to a second aspect of the present invention performs the above-described arrangement change when data read from a synchronous memory and stored in a buffer memory is read from the buffer memory. It is.
That is, the memory access control circuit includes a buffer memory for sequentially storing data read by burst access while switching memory banks from the synchronous memory in data word units, and a read address for reading data words from the buffer memory. And a buffer read circuit for generating the same. The synchronous memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access. The buffer readout circuit includes a first circuit for designating the memory bank.
Address information and second address information for designating the first word of burst access, and inputting the first and second data from the first position in the range of the number of data words corresponding to the number of banks of continuous access data words by burst access. Changing the order of generation of read addresses according to the difference in the number of data words up to the position of the data word specified by the address information,
Data words are read from the data buffer and controlled in an order corresponding to the arrangement order of the continuous data.

The memory access control circuit according to the third aspect of the present invention, when writing data to a synchronous memory, changes the array as described above at the stage of writing to a buffer memory. That is, the memory access control circuit in this case includes a buffer memory and a buffer write circuit for generating a write address for writing data to be written by burst access to the buffer memory in data word units while switching a memory bank to the synchronous memory. And The synchronous memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access. The buffer write circuit inputs first address information designating the memory bank and second address information designating a head word of burst access, and responds to the number of banks of continuous access data words by burst access times the number of banks. Changing the order in which write addresses are generated in accordance with the difference in the number of data from the head position in the range of the number of data words to the position of the data word specified by the first and second address information; Are arranged in an order corresponding to the arrangement order of the continuous data, and writing control to the data buffer is performed.

A memory access control circuit according to a fourth aspect of the present invention performs the above-described array change at the stage of reading data to be written to the synchronous memory from the buffer memory when writing data to the synchronous memory. is there.
That is, in this case, the memory access control circuit includes a buffer memory for sequentially storing data to be written by burst access while switching memory banks to the synchronous memory in data word units, and a read for reading data words from the buffer memory. A buffer read circuit for generating an address. The synchronous memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access. The buffer readout circuit includes a first circuit for designating the memory bank.
Address information and second address information for designating the first word of burst access, and inputting the first and second data from the first position in the range of the number of data words corresponding to the number of banks of continuous access data words by burst access. Changing the order of generation of read addresses according to the difference in the number of data words up to the position of the data word specified by the address information,
Data words of write data to be supplied to the memory bank are read from the data buffer and controlled in an order corresponding to the arrangement order of the continuous data.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS << Data Processing LSI >> FIG. 2 shows an example of a semiconductor integrated circuit according to the present invention. Although the semiconductor integrated circuit shown in FIG. 1 is not particularly limited, a data processing LS specialized in image data processing for satellite broadcast reception is provided.
I, and is formed on a single semiconductor chip made of single crystal silicon. The data processing LSI 1 has a CP
U (central processing unit) 2, RAM (random access memory) 3, used for work area of CPU 1, etc., C
ROM (Read Only Memory) 4 having an operation program of PU 2, memory access control circuit 5, and logic circuit 6 for processing image data for satellite broadcast reception
Having. The access control circuit 5 includes an SDRAM 7 which is an example of a synchronous memory having a plurality of memory banks and capable of burst access in synchronization with a clock signal.
Is connected. The SDRAM 7 can be used for a frame buffer, a data memory, or the like.

<< SDRAM >> Before describing the access control circuit 5 in detail, an example of the SDRAM 7 will be described with reference to FIG. Although not particularly limited, the SDRAM 7 shown in FIG. 3 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
The SDRAM 7 has, although not particularly limited, two memory banks (hereinafter, also simply referred to as banks). That is,
The SDRAM 7 has a memory array 20 forming the A bank.
0A and a memory array 200B forming a B bank are provided. Each of the memory arrays 200A and 200B includes dynamic memory cells MC arranged in a matrix. According to the drawing, the selection terminals of the memory cells MC arranged in the same column are coupled to the word line WL for each column. The data input / output terminals of the memory cells arranged on the same row are coupled to complementary data lines BL, BLb for each row. Although only a part of the word lines and the complementary data lines are representatively shown in FIG. 1, a large number are actually arranged in a matrix.

The word line WL of the memory array 200A
One selected according to the decoding result of the row address signal by the row decoder 201A is the word driver 213.
Driven to the selected level by A.

The complementary data lines of memory array 200A are coupled to sense amplifier and column select circuit 202A.
The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a small potential difference appearing on each complementary data line by reading data from the memory cell MC. The column selection circuit in this case selects the complementary data lines individually and selects the complementary common data line 2
This is a switch circuit for making the transistor 04 conductive. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, on the memory array 200B side, the row decoder 201B,
A word driver 213B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are provided. The complementary common data line 204 is connected to the output terminal of the data input buffer 210 and the data output buffer 211.
Is connected to the input terminal. The input terminal of the data input buffer 210 and the output terminal of the data output buffer 211 are 1
It is connected to 6-bit data input / output terminals I / O0 to I / O15. According to this configuration, although not particularly limited, S
In the DRAM 7, read data and write data are input / output in parallel in units of 16 bits (1 word).

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs a column address signal as the preset data or the column address thereof according to an operation mode specified by a command described later. The value obtained by sequentially incrementing the signal is applied to the column decoder 203A,
Output to 203B.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, chip select signal CSb (suffix b means that the signal attached thereto is a row enable signal or a level inversion signal), column address strobe signal CASb, row address strobe signal RAS
b, an external control signal such as a write enable signal WEb, and control data from the address input terminals A0 to A9. The operation mode of the SDRAM 7 and the operation of the circuit block are determined based on the level and change timing of these signals. And a control logic (not shown) and a mode register 220 for generating an internal timing signal for controlling the timing.

The clock signal CLK is a master clock of the SDRAM, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

The chip select signal CSb indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other inputs have no meaning. However, an internal operation such as a memory bank selection state and a burst operation, which will be described later, is not affected by the change to the chip non-selection state.

Each of the signals RASb, CASb, and WEb has a different function from the corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. In a power down mode (which is also a data retention mode in SDRAM), the clock enable signal CKE is at a low level.

Although not shown, an external control signal for controlling output enable for the data output buffer 211 in the read mode is also supplied to the controller 21.
2, when the signal is at a high level, for example, the data output buffer 211 is brought into a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK.

The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at low level, bank A (memory array 200A) is selected, and when it is at high level, bank B (memory array 200A) is selected.
B) is selected. The selection control of the bank is not particularly limited, but the row decoder of the selected bank is activated and all the column switches of the non-selected bank are deselected, and the data input buffer 210 and the data output buffer 211 of the selected bank are supplied to the selected bank. Processing such as connection is performed.

The input of A8 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that the precharge target is both memory banks, and its low level. The level indicates that one of the memory banks indicated by A9 is to be precharged.

The column address signal is A0 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK.
ＡA7. The column address defined in this way is used as a start address for burst access.

The main operation modes of the SDRAM specified by the command are as follows:

[9] and the like.

[1] The mode register set command is
This is a command for setting the mode register 220. This command is used for CSb, RASb, CAS
b, WEb = low level designates the command, and data to be set (register set data) is A
0 through A9. Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. Although not particularly limited, the settable burst length is not particularly limited, but is 1, 2, 4, 8, or full page (256). The settable CAS latency is not particularly limited, but is 1, 2, 3 The light modes that can be set are
Burst light and single light.

The CAS latency specifies how many cycles of the clock signal CLK are required from the fall of CASb to the output operation of the data output buffer 211 in a read operation specified by a column address read command described later. It is. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the clock signal CLK. In other words, when using a clock signal CLK with a high frequency, the CAS latency is set to a relatively large value, and when using a clock signal CLK with a low frequency, the CAS latency is set to a relatively small value.

[2] The row address strobe / bank active command is used to specify the row address strobe and A
9, CSb, RASb = low level, CASb, WEb
= High level. At this time, the address supplied to A0 to A8 is captured as a row address signal, and the signal supplied to A9 is captured as a memory bank selection signal. The fetch operation is performed by the clock signal CLK as described above.
Is performed in synchronization with the rising edge of. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

[3] The column address read command is a command necessary for starting the burst read operation and a command for giving an instruction of a column address strobe. CSb, CASb, = low level, RASb, WEb = Directed by high level,
At this time, the addresses supplied to A0 to A7 are captured as column address signals. The fetched column address signal is preset in the column address counter 207 as a burst start address.
In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. 1 in accordance with the address signal output from the column address counter 207 in synchronization with
Words are sequentially selected and read continuously. The number of data (the number of words) read continuously is set to the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency. According to this example, the column address signal is 8 bits A0 to A7, and the number of parallel data input / output bits is 1 word.
Memory cells for 6 words are connected.

[4] The column address / write command is a command necessary to start the burst write operation when the mode register 220 is set to burst write as a mode of the write operation. When single write is set in the mode register 220, this is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is CSb, CASb, WEb, = low level, RAS
b = instructed by high level, at this time A0 to A7
Is taken in as a column address signal. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write.
The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

[5] Precharge commands are A8 and A
9 is a command to start the precharge operation for the memory bank selected by CS9, CSb, RASb, WE
b, = low level, CASb = high level.

[6] The auto refresh command is a command required to start auto refresh, and CSb, RASb, CASb = low level,
Indicated by WEb, CKE = high level. The refresh operation by this is the same as the CBR refresh.

[7] When the self-refresh entry command is set, the self-refresh function operates while CKE is kept at the low level. During this time, a predetermined interval is automatically set even if no external refresh instruction is given. Performs a refresh operation.

[8] The burst stop in full page command is a command required to stop the burst operation for a full page, and is ignored in burst operations other than the full page. This command is
b, WEb = low level, RASb, CASb = high level.

[0050]

[9] The no operation command is a command for not performing a substantial operation,
Instructed by CSb = low level and RASb, CASb, WEb = high level.

In the SDRAM, when a burst operation is being performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The operation of the row address system in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but may be held for each memory bank. It has become. Or, row address strobe
The data for one word line in the memory block selected by the bank active command cycle is latched by a latch circuit (not shown) for reading before the column operation. Therefore, as long as data does not collide at the data input / output terminals I / O0 to I / O15, during execution of a command whose processing has not been completed, the execution of a command for a memory bank different from the memory bank to be processed by the command being executed is not performed. It is possible to issue a precharge command and a row address strobe / bank active command to start the internal operation in advance.

As described above, the SDRAM 1 can input and output data, addresses, and control signals in synchronization with the clock signal CLK.
A high-speed operation comparable to that of a RAM can be performed, and the number of data to be accessed for one selected word line is designated by a burst length. It will be understood that a plurality of data can be read or written continuously by switching the selection state of the system.

<< Access Control Circuit >> An example of the access control circuit 5 is shown in FIG. The access control circuit 5 includes a buffer memory 51, a buffer write circuit 52, a read counter 53, a write counter 54, a column address output counter 55, and a row address output counter 5.
6.

The counters 53 to 56 are constituted by registers accessed by the CPU, and the data held by the registers is updated by the CPU 2 without any particular limitation.
In particular, in the row address counter 56 and the column address counter 55, initial values of a row address and a column address for accessing the SDRAM 7 are initialized by the CPU. The CPU 2 updates the value of the corresponding counter each time the row address strobe / bank active command and column address read command are issued.

Data output from the SDRAM 7 is supplied to the buffer memory 51. The write address of the buffer memory 51 is generated by the buffer write circuit 52. The read address of the buffer memory 51 is generated by the read counter 53. The output of the write counter 54 is supplied to the buffer write circuit 52. The write counter 54 and the read counter 53 perform an increment operation in synchronization with a read operation cycle of one word of the SDRAM 7.

Although not particularly limited, the buffer memory 51 has a storage capacity at least as large as the number of banks of continuous access data words by burst access in the SDRAM 7. Here, it is assumed that the number of continuous access data words by burst access is fixed at 8 words, and thus the storage capacity of the buffer memory 51 is 16 words. According to this example, the counters 53 and 54 each have 4 bits.

The buffer write circuit 52 includes address information A9 as first address information for designating the memory bank, and 3-bit information as second address information for designating the position of the first word of burst access in units of 8 words. Lower address information A2 to A0 are input, and the number of continuous access data words by burst access (8 words)
The address information A from the head position in the range of the number of data words (16 words) corresponding to the number of times (double) the number of banks
9, the write address generation order is changed based on the difference in the number of words up to the position of the first word specified by A2 to A0, and the read word data string from the SDRAM 7 is stored in the buffer memory 51 as described later. The writing control is performed on the buffer memory 51 in the order along the arrangement order of the continuous data such as the image data stored in the buffer memory 51.

<< Address Conversion Function >> Hereinafter, an example of the address conversion function of the buffer write circuit 52 will be described in detail. First, as shown in FIG. 11, for example, continuous image data corresponding to one line of an image is stored in banks A and B of the SDRAM 7 every eight words. The arrangement order of the continuous data for one line of the image to be stored in the SDRAM is as shown in FIG. In the burst read operation for the SDRAM 7 in which data is stored as described above, the address information A9,
It is assumed that continuous data starting from a word position in 16 words specified by A2 to A0 is always read out from bank A first 16 words at a time. Such read control is performed by the CPU 2 according to its operation program.

As shown in FIG. 5, if the read start position is at the beginning of the boundary between the A bank and the B bank, the B start in the A bank is performed as shown in FIG.
From the first data 0 to data 7 at the boundary with the bank, and from the first data 8 at the boundary with bank A in the B bank to data 1
5, a burst read access in units of eight words is performed. As described above, the bank is switched by setting a row address strobe / bank active command and a column address read command to another bank in advance while performing a burst read in one memory bank, and without interruption from the SDRAM 7. This is performed so that read data can be obtained.

On the other hand, if the read start position is the position of the data 3 in the middle of the A bank, as shown in FIG. Burst read of bank A is performed in the order of 7, 16, 17, and 18. Next, data 8 to data 15 in bank B are accessed by burst read.

If the read start position is the data 13 position in the middle of the bank B, the data 16 to data 13 of the bank A are burst-read first as illustrated in (3) of FIG. After that, data 14, 15, 24, 25, 2
Burst read of bank B is performed in the order of 6, 27, 28.

As described above, the number of banks (8 words), which is the number of continuous access data words by burst access, is 8 times (2
The start position in the 16-word range of (double) can be grasped as a boundary position of the memory bank. The head position of the data actually read from the memory bank with respect to the SDRAM N7 corresponds to the first and second address information A9, A2 to A2 with respect to the boundary position of the memory bank.
It has an offset corresponding to the number of words up to the position of the first word specified by 0. The buffer writing circuit 52 uses the offset to store data in word units from the memory bank in the buffer memory 51 as shown in FIG.
The order in which write addresses are written to the data buffer is changed so that the image data can be changed in the arrangement order of one image data and can be written.

FIG. 6 shows an example of such an address change logic. In FIG. 6, the counter values 0 to 15 are 4-bit outputs C3 to C0 of the write counter 54.
, For example, a 4-bit output C3 to
One counter value can be specified by decoding C0. 520 can be considered as such decoding logic. In FIG. 6, the start data positions 0 to 15 are 4-bit address information A9, A2 to A
0, for example, 4-bit information A
9. One start data position can be specified by decoding A2 to A0. The start data position means a data position in word units. 521 can be considered as such decoding logic. When one row is selected by the decode logic 521 and the columns are sequentially selected one by one by the decode logic 520 according to the counting operation of the counter 54, the value of the intersection becomes information indicating the word position of the buffer memory 52. . For example, when the start data position is the word data 3, the write address of the buffer memory, that is, the word address of the buffer memory 51 becomes
0,1,2,3,4,13,14,15,5,6,7,
The order is 8, 9, 10, 11, 12. In FIG. 6, the conversion logic is shown in a format such as a conversion table for easy understanding of the conversion logic, but the actual logical structure can be variously selected from the viewpoint of logical scale reduction.

Here, for example, in the form of (2) in FIG.
An address conversion operation realized by the buffer write circuit 52 when data is read from the RAM 7 will be described with reference to FIGS.

In the burst read of the SDRAM according to the mode (2) of FIG. 5, word data D3 to D7 and D16 to D18 are sequentially read from the bank A, as shown in FIG. To a total of 8 words of data D
8 to D15 are sequentially read. The output value of the write counter 54 that operates in synchronization with the reading is incremented from # 0 to # 15 in synchronization with the reading of data in word units. At this time, the buffer write circuit 5
2 corresponds to the contents of the row corresponding to the start data position 3 in FIG. 6, and # 0 as shown in FIG.
To # 4, # 13 to # 15, and # 5 to # 12. Therefore, as shown in FIG.
In the case of 3 to D7, D16 to D18, and D8 to D15, the read word data is stored in the buffer memory 51 in the order of D3 to D18. Thus, the buffer memory 5
2 shows the SDRA of the data as shown in FIG.
The data is stored in an order corresponding to the arrangement order of the continuous data written to M7. Accordingly, the read counter 53 is sequentially incremented in synchronization with the word access cycle, so that continuous data such as image data is output from the buffer memory 51 in an original arrangement.

In the above-mentioned burst read access, the number of words of the continuous read is fixed to 8 words. In this case, the subsequent 8 words can be accessed continuously regardless of the burst start address. Such a burst read operation is performed, for example, when the CPU 2 issues a burst stop command every eight words of burst read in the full page burst mode, or
This is enabled when the RAM 7 itself has hardware capable of always incrementing to +7 after the start address without the toggle of the column address counter even in the selected state of the 8-word burst mode.

S having a structure in which the column address counter toggles when the 8-word burst mode is selected.
In the case of the DRAM 7, as shown in FIG. 8, when the value of the column address counter has counted up to 8, a column address read command may be reissued to switch the column address. . For example, when the read start data in (2) of FIG. 8 is 3, the column address is issued so that the data 16 is read next to the data 7 in the middle of reading in the A bank. Similarly, when the read start data is 13 as shown in (3) of FIG.
A column address is issued so that data 24 is read next to data 15 in the middle of reading B bank.

According to the data processing LSI 1 employing the access control circuit 5, continuous data access from an arbitrary position can be performed without increasing access to the SDRAM 7.

Further, the access control circuit 5
Burst access of the DRAM 7 can be easily and efficiently started at the A bank and terminated at the B bank, and the waste time due to bank switching between accesses can be eliminated.

As described above, when continuous data stored in a plurality of memory banks is obtained from an arbitrary position,
The memory access can be started from the A bank and terminated at the B bank, without increasing the number of accesses to the SDRAM 7 and without increasing the load on the CPU 2 which is the main body of the access control. It becomes possible to increase the efficiency of the operation of acquiring the necessary data from an arbitrary position.

<< Another Form of Access Control Circuit >> The address conversion by the access control circuit 5 may be performed when data read from the SDRAM 7 and stored in the buffer memory 51 is read from the buffer memory 51. For example, the buffer memory 51 sequentially stores data read by burst access in units of words while switching memory banks from the SDRAM 7. Instead of the buffer write circuit 52, a buffer read circuit (not shown) for generating a read address for reading word data from the buffer memory 51 is employed. This buffer read circuit inputs A9 as first address information for designating the memory bank and A2 to A0 as second address information for designating the first word of burst access, and calculates the number of continuous access data words by burst access. The number of data words corresponding to the number of banks times the number of data words, for example, the order in which read addresses are generated based on the difference in the number of data words from the head position in the range of 16 words to the position of the data word specified by the first and second address information And the word data is read out from the data buffer 51 in an order corresponding to the arrangement order of the continuous data. FIG. 9 illustrates an example of the address conversion logic of the buffer read circuit in that case. The expression form of this figure is the same as that of FIG.

The address conversion by the access control circuit 5 can be applied to the case where data is written from the buffer memory 51 to the SDRAM 7. For example, such a memory access control circuit changes the array as described above at the stage of writing to the buffer memory 51 when writing data to the SDRAM 7. That is, the memory access control circuit in this case is
And a buffer write circuit for generating a write address for writing data to be written by burst access to the SDRAM in units of words while switching memory banks to the SDRAM. The SDRA
M7 can store the continuous data by sequentially switching the memory bank for each continuous access word number by the burst access, as described above. The buffer write circuit includes first address information A9 for designating the memory bank and second address information A2 for designating the first word of the burst access.
To A0, and designated by the first and second address information A9, A2 to A0 with respect to the head position in the range of the number of data words corresponding to the number of banks of the number of continuous access data words by burst access. The order in which write addresses are generated is changed in accordance with the difference in the number of data up to the word position, and the word data of the write data to be supplied to the memory bank is rearranged in an order corresponding to the array order of the continuous data, and stored in the buffer memory 51 It controls writing. The address conversion logic at this time can be configured in the same manner as in FIG.

As another mode, the memory access control circuit performs the above-described array change at the stage of writing data to the synchronous memory from the buffer memory 51 when writing data to the synchronous memory. is there. That is, in this case, the memory access control circuit includes a buffer memory 51 for sequentially storing data to be written by burst access while switching memory banks to the synchronous memory in word units, and a read for reading data words from the buffer memory. A buffer read circuit for generating an address. The synchronous memory SDRA
M can still store continuous data by sequentially switching memory banks for each continuous access word number by burst access. The difference is that the buffer read circuit inputs first address information A9 specifying the memory bank and second address information A2 to A0 specifying the first word of the burst access. In accordance with the difference in the number of words from the head position in the range of the number of words corresponding to the number of banks equal to the number of continuous access data words to the number of words specified by the first and second address information The generation order of the addresses is changed, and the word data of the write data to be supplied to the memory bank is controlled to be read from the data buffer in an order corresponding to the arrangement order of the continuous data. The address conversion logic at this time can be configured in the same manner as in FIG.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the unit of the data word is not limited to a word of 16 bits, but may be a byte (8 bits), a long word (32 bits), or the like. The storage capacity of the buffer memory is equal to S
The storage capacity of the DRAM 7 is not limited to the storage capacity of the number of banks of the number of continuous access data words by the burst access, but may be larger than that. Further, the synchronous memory is not limited to the SDRAM, but may be a synchronous SRAM.
For example, another clock-synchronous memory may be used.

In the above description, the invention made mainly by the present inventor is not limited to a data processing LSI for satellite broadcasting capable of processing image information, which is a field of application which is the background of the invention. The present invention can also be applied to a system LSI for controlling a still camera. Furthermore, continuous information is not limited to image information, but may be audio information or the like. In this case, the present invention can also be applied to a system LSI for voice recognition and audio control.

[0077]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when obtaining continuous data stored in a plurality of memory banks from an arbitrary position, the start bank and the end bank of the memory access can be easily set to a fixed bank, and the number of memory accesses It is possible to improve the efficiency of the operation of acquiring continuous data stored in a plurality of memory banks from an arbitrary position without increasing the number of data items and increasing the burden on the access control subject.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram schematically showing an example of an address conversion operation by a memory access control circuit of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram of a data processing LSI as an example of a semiconductor integrated circuit according to the present invention.

FIG. 3 is a block diagram illustrating an example of an SDRAM.

FIG. 4 is a block diagram illustrating an example of an access control circuit.

FIG. 5 is an explanatory diagram illustrating a burst access mode of an SDRAM adapted to the present invention;

FIG. 6 is an explanatory diagram illustrating an example of conversion logic of a buffer write circuit.

FIG. 7 is an explanatory diagram showing an address conversion operation realized by the buffer write circuit in a time-series manner.

FIG. 8 is a diagram showing an example of the SD in an 8-word burst mode selection state when the column address counter has a toggle structure.
FIG. 3 is an explanatory diagram illustrating an example of a burst access of a RAM.

FIG. 9 is an explanatory diagram showing an example of an address conversion logic of a buffer read circuit when performing address conversion when reading data read from an SDRAM and stored in a buffer memory from the buffer memory;

FIG. 10 is a timing chart illustrating the timing of a burst access operation of the SDRAM.

FIG. 11 is an explanatory diagram showing an example in which continuous data is stored using a plurality of banks of an SDRAM.

FIG. 12 is an explanatory diagram showing contents of a method of acquiring stored data from an arbitrary position when continuous data is stored alternately in a plurality of banks.

FIG. 13 is an explanatory diagram showing an operation in which the SDRAM performs a burst read by changing the read method each time according to the position of required data.

[Description of Signs] 1 Data processing LSI 2 CPU 200A, 200B Memory bank 5 Access control circuit 51 Buffer memory 52 Buffer writing circuit 53 Read counter 54 Write counter 7 SDRAM A9, A2-A0 Address information

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kenichi Iwata 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in the System LSI Development Center of Hitachi, Ltd. 5B024 AA15 BA29 CA16 CA19 5B060 AB13 AB19

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a memory access control circuit capable of burst access in synchronization with a clock signal and capable of controlling access to a synchronous memory having a plurality of memory banks, wherein the memory access control circuit is provided. Has a buffer memory, and a buffer write circuit that generates a write address for writing data read by burst access to the buffer memory in data word units while switching memory banks from the synchronous memory. The memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access, and the buffer write circuit includes first address information designating the memory bank, and a first data word of burst access. Second to specify the position of Address information and the data from the head position in the range of the number of data words corresponding to the number of banks equal to the number of banks of continuous access data words by burst access to the position of the head data word specified by the first and second address information A semiconductor, wherein the order of generation of write addresses is changed according to the difference in the number of words, and the data words from the memory bank are rearranged in the data buffer in an order corresponding to the order of arrangement of the continuous data to perform write control. Integrated circuit. 2. A semiconductor integrated circuit having a memory access control circuit capable of performing burst access in synchronization with a clock signal and capable of controlling access to a synchronous memory having a plurality of memory banks, wherein the memory access control circuit is provided. A buffer memory for sequentially storing data read by burst access while switching memory banks from the synchronous memory in data word units, and a buffer read circuit for generating a read address for reading data words from the buffer memory. Wherein the synchronous memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access, and wherein the buffer read circuit includes first address information specifying the memory bank and , The first word of burst access And the second address information designating the first and second address information from the head position in the range of the number of data words corresponding to the number of banks of continuous access data words by burst access. A semiconductor integrated circuit, wherein the generation order of read addresses is changed in accordance with the difference in the number of data words up to a position, and data words are read out from a data buffer in an order corresponding to the arrangement order of the continuous data. 3. A semiconductor integrated circuit having a memory access control circuit capable of performing burst access in synchronization with a clock signal and capable of controlling access to a synchronous memory having a plurality of memory banks, wherein the memory access control circuit is provided. Comprises a buffer memory, and a buffer write circuit for generating a write address for writing data to be written by burst access to the buffer memory in units of data words while switching memory banks to the synchronous memory. Can sequentially switch memory banks for each number of continuous access data words by burst access and store the data. The buffer write circuit specifies first address information for specifying the memory bank and a first word for burst access. And the second address information In accordance with the difference in the number of data from the start position to the position of the data word specified by the first and second address information in the range of the number of data words corresponding to the number of banks equal to the number of continuous access data words by burst access. A semiconductor device, wherein the write word generation order is changed to change the arrangement of the data words of the write data to be supplied to the memory bank in an order corresponding to the arrangement order of the continuous data, and the write control is performed on the data buffer. Integrated circuit. 4. A semiconductor integrated circuit having a memory access control circuit capable of burst access in synchronization with a clock signal and capable of controlling access to a synchronous memory having a plurality of memory banks, wherein the memory access control circuit is provided. A buffer memory for sequentially storing data to be written by burst access while switching memory banks to the synchronous memory in data word units, and a buffer read circuit for generating a read address for reading a data word from the buffer memory. The synchronous memory is capable of storing continuous data by sequentially switching memory banks for each number of continuous access data words by burst access, and the buffer read circuit includes first address information specifying the memory bank; Specify the first word of burst access And the second address information to be input, and from the head position in the range of the number of data words corresponding to the number of banks of continuous access data words by the burst access to the position of the data word specified by the first and second address information The generation order of read addresses is changed in accordance with the difference in the number of data words, and the data words of the write data to be supplied to the memory bank are read out from the data buffer in an order corresponding to the arrangement order of the continuous data. Semiconductor integrated circuit. 5. An apparatus according to claim 1, further comprising an address generation unit configured to generate access address information including the first and second address information for accessing the synchronous memory, wherein the address generation unit includes the first and second address information. 5. The method according to claim 1, wherein access address information for designating continuous data starting from the position of the data word specified by the address information by a predetermined number of data words from a prescribed memory bank is generated. 2. The semiconductor integrated circuit according to claim 1.