JP2000246943A - Method for divisionally driving thermal head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for divisionally driving a thermal head capable of suppressing the difference in recording density (heat quantity) which may be caused by the difference of the number of heating elements that are energized at the same time. SOLUTION: There is disclosed a method for divisionally driving a thermal head wherein energizing of a plurality of heating elements R0-R19 provided on the thermal head is executed in one line or one gradation level such that the number of pixels which are formed at the same time is allowed to be not greater than a predetermined value by calculating the number, then the heating elements R0-R19 are divisionally driven plural times. A counting order of the number of pixels to be formed for determining a diving position is varied by each N (N is not less than one) gradation level(s). As a result, it is possible to suppress the difference in recording density (heat quantity) which may be caused by the difference of the number of heating elements that are energized at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for energizing a plurality of heating elements arranged on a thermal head of a recording apparatus for one line or one gradation, and the number of heating elements simultaneously energized becomes equal to or less than a predetermined value. In this manner, the present invention relates to a thermal head division driving method for driving the apparatus in a plurality of times.

[0002]

2. Description of the Related Art Generally, in a printing apparatus using a thermal head having a plurality of heating elements for recording on thermal paper or the like, the number of heating elements to be energized simultaneously is controlled in order to reduce the power supply capacity. A method is used in which energization for one line or one gradation is divided into a plurality of times and driven. Here, a first example of the conventional thermal head division driving method will be described. 7 is a block diagram showing a conventional head drive circuit, FIG. 8 is a diagram showing an input / output relationship of a comparator, FIG. 9 is a timing chart showing signals of main parts in FIG. 7, and FIG. It is a schematic diagram which shows a state.

First, the function of each block constituting a conventional head drive circuit will be described with reference to FIG. Memory 1 is
This memory is for storing gradation data for one line to be recorded, and outputs gradation data b in synchronization with an address signal a. Here, in order to simplify the explanation, the total number of pixels in one line is 20 pixels (dots), the number of gradations of one pixel is 16 gradations (4 bits), and 1 For example, 0,
0, 1, 4, 4, 2, 1, 0, 0, 1, 0, 1, 2, 0, 2, 2, 4, 4,
Assume that 4 and 4 have already been written. The address counter 2 increments the counter in synchronization with a read clock (not shown), and outputs the output of the counter as an address signal a. Further, each time an address for one line is output, an address carry signal c and a latch pulse p are output, and the counter is repeated from 0 again.

The address latch 4 latches the address signal a in synchronization with the data carry signal f from the data counter 8, and outputs this to the address comparator 3 as an output signal d. The output signal d is cleared (output = 0) in synchronization with the gradation step signal h from the control circuit 7. The address comparator 3 compares the output signal d of the address latch 4 with the address signal a, and when these two signals a and d match, the address match signal e
Is output to the data counter 8. The gradation counter 6 increments the counter in synchronization with the gradation step signal h from the control circuit 7, and outputs the output of the counter 6 to the data comparator 5 as a gradation level signal i. The data comparator 5 compares the gradation data b read from the memory 1 with the gradation level signal i, and when the gradation data b is larger than the gradation level signal i (b> i), the comparison result j = “ H ”(high) is output. FIG. 8 shows the relationship between the gradation level signal i and each gradation data b read from the memory 1 and the comparison result (signal) j. In the drawing, "L" indicates low.

[0005] The data counter 8 counts the number of simultaneously energized dots transferred to the shift register by counting the number of read clocks input during a period when the comparison result j output from the data comparator 5 is "H". When the counted value reaches a predetermined value, the data counter 8 outputs a data carry signal f and stops the counting operation (0 reset).
This counting operation is restarted from 0 in synchronization with the arrival of the address coincidence signal e or the gradation step signal h. Further, the data counter 8 outputs the data mask signal g = “H” during the counting operation (period from when the address match signal e or the gradation step signal h is received until the data carry signal f is output). Here, it is assumed that the number of simultaneously energizable heating elements is four, and the data carry signal f is output when the count value of the data counter 8 is four.

The control circuit 7 outputs a gradation step-up signal h when the address carry signal c arrives while the data mask signal g is "H". The AND gate 9 outputs the logical product of the comparison result j output from the data comparator 5 and the data mask signal g to the shift register 10 as serial print data k. The shift register 10
The serial print data k is converted into parallel data m (20 bits) in synchronization with a read clock (not shown) for increasing the address counter 2 by the same number of stages as the number of heating elements for one line, for example, 20 stages. Output to the data latch 11. Data latch 11, the latch pulse p coming from the address counter 2 latches the parallel data m for one line, this latch output n, each heating element R ₀ to R ₁₉ of the thermal head is driven. A Between Generally the transistor Tr ₀ to Tr ₁₉ for driving the latch output n and the respective heating elements R ₀ to R ₁₉
An ND gate is inserted, and a control signal for controlling the energization time is input to the other input of the AND gate.
Here, it is omitted to simplify the description. Also,
The power supply 12 is a power supply for supplying power to each heating element.

Next, the operation of this circuit will be described with reference to FIGS. 9 and 10. The recording operation of one line is started by a line pulse LP coming from a main control circuit such as a CPU (Central Processing Unit) which controls the entire apparatus (not shown). At this time, the address counter 2 and the gradation counter 6 are activated. ,
Each count value of the data counter 8 and each output of the address latch 4 and the data latch 11 are set to 0, and the data mask signal g is set to "H". FIG.
As shown by, when the line pulse LP is received, the address counter 2 sequentially outputs the address signal a from 0 to one line (from 19) to the memory 1, and the first reading is performed. The memory 1 receives the address signal a (0, 1,
2, 3,..., 19) and the gradation data b (0, 0, 1, 4,
, 4) are output to the data comparator 5. Note that FIG.
7, the signals (excluding s) in FIG. 7 are given before each signal, the address information is described in the d signal waveform, and the gradation level is described in the i signal waveform.

The data comparator 5 has a gradation counter 6
Compares the gradation level signal i = 0 output from the memory device 1 with each gradation data b output from the memory 1, and sequentially outputs the comparison result. Here, as shown in FIG. 8 earlier, for the gradation level signal i = 0, the address signal a = 2, 3, 4, 5, 6, 9, 11 where the gradation data b is 1 or more. , 12, 14, 15,16, 1
At 7, 18, and 19 (14 times in total), the comparison result j = “H” is output. The data counter 8 sequentially counts the period of the comparison result j = “H”, and outputs a data carry signal f to the address latch 4 when the count value becomes 4 as shown by a signal s in FIG. Address latch for address signal a = 5
4 is held as a latch output d, and the counting operation is completed. In addition, the data counter 8 outputs the data mask signal g = “H” only during the period when the address signal a is 0 to 5. Thereby, the output k of the AND gate (first comparison result) k in the first reading becomes “H” only during the four dot period (address = 2, 3, 4, 5), and thereafter, the data mask signal Since g is "L", the AND gate output k also becomes "L" regardless of the comparison result j.

An AND gate output k supplied as a serial input signal to the shift register 10 is supplied to an address counter 2.
20 in synchronization with a read clock (not shown)
It is sequentially converted into bit parallel data m (m0 to m19). When the address signal a for one line is output by the address counter 2 and the AND gate output k (the first comparison result) for one line is simultaneously converted by the shift register 10 into parallel, the address counter 2 outputs the address carry signal. c and the latch pulse p. The first comparison result m subjected to the parallel conversion is a latch pulse p
Is held in the data latch 11. According to the output signal n of the data latch 11, the address = 2, 3, 4, 5
Period until only the next latch pulse arrives (second readout period) for only the _four heating elements R ₂ , R ₃ , R ₄ , R ₅ ,
The power is turned on.

Address carry signal c and latch pulse p
Is output and when the first reading is completed,
The second reading is performed by the address counter 2 as in the first reading. In the second reading, the data mask signal g is "L" until the address signal a becomes 5, but when the address signal a becomes 5, the address comparator 3 outputs the address match signal e. In response to this, the data counter 8 restarts the counting operation from the comparison result j for the address a = 6, and at the same time, sets the data mask signal g to "H". Similarly to the first time, the data counter 8 performs a counting operation until the count value becomes 4, and when the count value becomes 4, outputs the data carry signal f. The address signal a = 12 at this time is held in the address latch 4. Then, the counting operation ends. Further, the data mask signal g thereafter is set to “L”. As a result of the second reading, the parallel output m of the shift register 10 becomes address = 6, 9,
Only the 11th and 12th bits (m6, m9, m11, m12) become "H". At the same time, during the second reading period, the output n of the data latch 11 causes the first comparison result (heating elements: R ₂ , R ₃ , R ₄ , R ₅ ) to be energized.

Similarly, in the third reading, the address of the parallel output m = 14, 15, 16, 17 bits (m14, m1
5, m16, m17) become “H”, during which time 2
The energization is performed on the comparison result for the fourth time, and in the fourth reading, the bits (m18, m1) of the address = 18, 19
Only 9) becomes "H", during which time the third comparison result is energized. By the fourth reading,
One line of gradation data b written in the memory 1;
When the comparison with the gradation level signal i = 0 is completed and all the comparison results are transferred to the shift register 10 (the address carry signal c is input while the data mask signal g is “H”), the control is performed. The circuit 7 outputs a gradation step signal h.
The input of the gradation step signal h clears the address latch 4, the gradation counter 6 increases the count value by 1, sets the gradation level signal to i = 1, and the data counter 8 returns the count value to 0. Then, the counting state is continued (data mask signal g = “H”).

From the fifth reading, each gradation data b
And the gradation level signal i = 1 is started, and as shown in FIG.
The above address signal a = 3, 4, 5, 12, 14, 15, 16,
At 17, 18, 19 (20 times in total), the comparison result j = "H"
Is output. As a result, the count value of the data counter 8 becomes 4 when the address signal a = 12 (the data mask signal g).
Is "H" during the period of the address signal a = 0 to 12), and the parallel output m of the shift register 10 has the address = 3, 4,.
Only the 5th and 12th bits become “H”. Similarly, in the sixth and subsequent readings, similarly, the comparison result for the predetermined gradation level signal is divided into four pieces and transferred in ascending order of the address, and transferred for one line for the predetermined gradation level signal. Is increased by one each time all the comparison results are transferred to the shift register, so that the number of heating elements simultaneously energized is controlled to four or less. Modulation) recording is performed. In FIG.
FIG. 3 is a schematic diagram illustrating a current-carrying state of each heating element. Here, energized portions are indicated by circles. Also, the position of the heating element is shown in the horizontal direction, and the gradation level signal i at the time of reading is shown in the vertical direction, and the comparison result of the first time is normally energized at the time of the second reading. Therefore, the gradation level signal at the time of reading and the energization state are represented at the same vertical position. As a second conventional example, in the conventional device of FIG. 7, the gradation data of all the addresses (0 to 19) of the memory 1 is set to “8”, and the number of simultaneously energized pixels (the data counter 8 stores the data carry signal FIG. 11 is a schematic diagram showing the energized state of each heating element when the count value when f is output) is 6. Here, similarly to FIG. 10, the energized portion is indicated by a circle, and the gradation level signal at the time of reading and the energized state are indicated at the same position.

[0013]

According to the driving method described above, the number of heating elements that are simultaneously energized can always be less than a predetermined number (four or six). And the current capacity of the power supply wiring (electrodes) is not necessary for all the heating elements, and can be sufficient to drive a predetermined number of heating elements at the same time. On the other hand, in the first conventional example, when the number of heating elements to be energized for a predetermined gradation level is not an integral multiple of 4, the number of heating elements to be energized in the last energization period of the gradation level is: 3 or less. In the case of the above-described conventional method, the fourth time for the gray level i = 0, i = 1
This corresponds to the third energization period for i, the second energization period for i = 2, and the second energization period for i = 3, and the number of heating elements that are energized simultaneously is two. In FIG. 10, the portion is indicated by a black circle. In this case, the amount of current flowing through the power supply wiring increases or decreases in accordance with the number of heating elements that are simultaneously energized, and the amount of voltage drop due to wiring resistance increases or decreases accordingly. In the energizing period in which the number of simultaneously energized heating elements becomes three or less as compared with the energizing period, the voltage applied to the heating elements becomes slightly higher. Therefore, the heating element driven at this time is driven in another period. The heating value tends to be larger than that of the heating element.

For example, as shown in FIG. 10, six heating elements R ₃ , R ₄ , R ₁₆ , R ₁₇ , and R 6 to which the same gradation data “4” is to be recorded.
R ₁₈ and R ₁₉ are each energized four times, and the heating elements at addresses 3, 4, ₁₆ , and ₁₇ each have four simultaneous energizing heating elements (the hatched circles in the figure). ), The amount of heat generation is small, and the heating elements at addresses 18 and 19 are driven in a period in which the number of simultaneously energizing heating elements is two (indicated by a black circle in the figure) for all four times. Therefore, the calorific value increases.
As a result, even if the gradation data to be recorded is the same (the number of times of energization is also the same), the obtained recording density is different.
There is a problem that a boundary line is generated between 7 and 18 due to a density difference. In addition, as shown in the second conventional example, in the conventional driving method, when data of the same level or data of the same level continues, six data are always added in the order from the smallest address to the same combination. The heating elements are energized simultaneously. When a plurality of adjacent heating elements are energized at the same time, the heating elements located at both ends more easily dissipate heat than the heating elements located inside the heating elements. Therefore, as shown in FIG. 11, in the conventional driving method in which the division position does not always change, for example, the heating elements located at both ends of the divided heating element group such as addresses 6 and 11 (the energized state in the figure is indicated by a white circle) ) Has a lower temperature than the heating elements (the energized state is indicated by hatched circles in the figure) located inside the addresses 7, 8, 9, 10, etc. In the example shown in FIG. 11, since the recording is repeated eight times, the obtained recording density is lower at the heating elements located at both ends than at the heating elements located inside.
When this is only one line, a solid line having a uniform density is a density distribution like a [dotted line], and when a plurality of lines are continued, a so-called [white streak] is generated in a uniform density region. was there.

As a countermeasure against this white streak, Japanese Patent Publication No. 6-1023
No. 85, the heating element for one line is n
Each block is divided into m blocks (the division position is fixed), and the (j × n) -th and (j ×
A method has been proposed in which the (n + 1) -th print data is multiplied by a coefficient greater than 1 to increase the energy applied to the dots at the boundary and to correct the print density. However, in this case, since the multiplier is used to multiply the coefficient, the circuit scale becomes large, and the print data of one line or one gradation can be reproduced regardless of the load (the number of simultaneously energized dots). There is a problem that m driving times are always required for recording, and the recording speed cannot be increased. The present invention has been devised in view of the above problems and effectively solving them.
A first object of the present invention is to provide a thermal head division driving method capable of reducing a difference in recording density (calorific value) caused by a difference in the number of heating elements that are simultaneously energized. A second object of the present invention is to provide a thermal head division driving method that changes the division position at each gradation level and does not generate a "white streak" even when recording uniform gradation data.

[0016]

A first aspect of the present invention is defined by the first aspect.
According to the invention, energization for one line or one gradation level to a plurality of heating elements arranged on a thermal head is divided into a plurality of times while counting so that the number of pixels to be energized simultaneously becomes a certain value or less. In the thermal head division driving method, the counting order of the number of energized pixels for determining the division position is made different for each of N (N is 1 or more) gradation levels. As a result, the difference in recording density (heat generation amount) due to the difference in the number of heating elements that are simultaneously energized is reduced.

According to a second aspect of the present invention, when a plurality of heating elements arranged on the thermal head are energized for one line or one gradation level, the number of pixels simultaneously energized becomes equal to or less than a predetermined value. As described above, in the thermal head division driving method in which the division is performed a plurality of times while counting, the count initial value of the number of energized pixels for determining the division position is set to N
It is different for each line or N (N is 1 or more) gradation level. In this manner, the division position in each line or each gradation level is changed, so that no white streaks are generated even when uniform gradation data is recorded.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a thermal head divided driving method according to an embodiment of the present invention. First, the first method invention will be described. FIG. 1 is a block diagram showing a head drive circuit for performing a first thermal head division driving method of the present invention, FIG. 2 is a timing chart showing signals of main parts in the block diagram of FIG. 1, and FIG. FIG. 2 is a diagram showing a current-carrying state of each heating element in FIG. First, among the blocks shown in FIG. 1, blocks having the same functions as those of the conventional device shown in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted. Then, three blocks having different functions, that is, the address counter 102, the control circuit 107, and the shift register 110 will be described. The address counter 102 increments the counter in synchronization with a read clock (not shown) as in the conventional device, outputs an address signal a, and outputs an address carry signal c and a latch pulse p every time an address for one line is output. Output. However, here, the address counter 102 is constituted by an up / down counter, and when the incoming switching signal z is "L", the counter is incremented from 0 as the up counter (counting up), and the switching signal While z is "H", the counter is repeatedly incremented (counted down) from 19, which is the last address of one line, as a down counter.

When the address carry signal c is received while the data mask signal g is "H", the control circuit 107 outputs a gradation step-up signal h and inverts the switching signal z in synchronization with the signal. I do. The shift register 110 has the same number of stages as the number of heating elements for one line, for example, 20 here.
The serial print data k is converted into parallel data m (20 bits) in synchronization with a read clock (not shown). At this time, while the incoming switching signal z is “L”, the serial print data k is sequentially transferred in the direction from the address 19 (m19) bits of the parallel data m to the address 0 (m0) bits (positive direction). During the period when the switching signal z is “H”,
That is, the data is sequentially transferred in the direction from address 0 to address 19 (reverse direction).

Next, a first method invention (operation) performed using this circuit will be described with reference to FIGS. Note that in FIG. 3, circles indicate energization as in FIG. First, similarly to the conventional apparatus, the recording operation of one line is started by the line pulse LP.
The count values of the address counter 102, the gradation counter 6, and the data counter 8, and the outputs of the address latch 4 and the data latch 11 are set to 0. Further, the data mask signal g is set to “H”, and the switching signal z is set to “L”. During the period when the switching signal z is “L”, the address counter 102 functions as an up counter and the shift register 110 functions as a shift register in the positive direction, so that the fourth reading from the arrival of the line pulse LP is performed. Until the end (comparison with the gradation level signal i = 0), the same processing as in the conventional device is performed.

As a result, the bits of the addresses 18 and 19 of the parallel data m become "H" in the fourth reading, as in the case of the conventional device. Here, when the fourth reading is completed, the control circuit 107 outputs the gradation stepping signal h and inverts the switching signal z to “H”. And 5
Since the switching signal z is “H” in the readout period from the first readout to the seventh readout, the address counter
102 functions as a down counter, and as a result, the gradation data b in the memory 1 is the final address of one line 19
To address 0 sequentially. In the fifth read period, which is compared with the gray level signal i = 1,
Since the count value of the data counter 8 becomes 4 when the address signal a is 16, the data mask signal g
The output k of the AND gate 9 becomes “H” during the period from the address 19 to the address “16”.

The output k of the AND gate 9 is the shift register 110
Are sequentially transferred in the reverse direction and are converted into parallel data m. Therefore, even if the reading order of the memory is changed, the comparison result is transferred to the same heating element position as the memory address and latched. As a result, in the fifth reading, the bits of the addresses 19, 18, 17, 16 of the parallel data m become "H". Similarly, in the sixth and seventh readings, the address counter 102 functions as a down counter, and the shift register 110 functions as a shift register in the reverse direction, and stores the comparison result with the gradation level 1 in the latch. Output. As a result, the bits at addresses 15, 14, 12, and 5 of the parallel data m become “H” in the sixth read, and the bits at addresses 4 and 3 become “H” in the seventh read. When the seventh reading is completed, the control circuit 107 outputs the gradation stepping signal h,
The switching signal z is again inverted to z = “L”. Also, 8
Similarly, the reading after the first time is performed for one gradation level.
Each time the comparison result for the line is transferred, the switching signal z is inverted, and the multi-gradation recording is performed while changing the address order of the read, transfer and energization.

As a result, as shown in FIG. 3, the six heating elements R ₃ , R ₄ , R ₁₆ , R for which the same gradation data “4” is to be recorded.
Of the heating elements at addresses 16 and 17 among the elements ₁₇ , R ₁₈ , and R ₁₉ , the number of simultaneously energizing heating elements is driven in a period of four times in the same manner as in the conventional apparatus. As for the heating elements of addresses 3, 4, 18, and 19, the number of the simultaneously energizing heating elements is driven twice during the two periods, and the other two times during the period when the number of simultaneously energizing heating elements is four. Since it is driven, it is possible to reduce the difference in the amount of heat generation smaller than in the case of the conventional device. As a result, it is possible to reduce the difference in recording density caused by the difference in heat generation. In the embodiment of the first method invention, the reading order is reversed for each gradation level.
In the case of 56 gradations (= 8 bits), the reading order may be switched every N gradation levels (N ≧ 2), and in this case, the same effect can be obtained. When the reading order is switched for each gradation level as in this embodiment, the switching signal z is, for example, the gradation level signal i.
In the case where the least significant bit is used or switching is performed every N gray levels, for example, the gray level signal i may be decoded to obtain the switching signal z. In binary recording in which the gradation data is composed of one bit, N (N ≧ 1)
The same effect can be obtained by switching the reading order for each line.

Next, a description will be given of a second method of the invention mainly for suppressing the occurrence of white streaks in a recorded image. FIG. 4 is a block diagram showing a head drive circuit for performing the second thermal head division driving method of the present invention, FIG. 5 is a timing chart showing signals of main parts in the block diagram of FIG. 4, and FIG. FIG. 4 is a diagram showing the energized state of each heating element in FIG. First, the function of each block constituting the head drive circuit will be described with reference to FIG. Among the blocks shown in FIG. 4, a block having a different function from that of the conventional device shown in FIG. 7 is a data counter 208, and a newly added block is a preset counter 13. Blocks having the same functions as those of the conventional device other than these two blocks are denoted by the same reference numerals and description thereof is omitted. Also, as in the second conventional example shown in FIG. 11, it is assumed that gradation data "8" is written to all addresses 0 to 19 of the memory 1.

The data counter 208 counts the number of simultaneously energized dots to be transferred to the shift register by counting the number of read clocks during which the comparison result j output from the data comparator 5 is "H". I do. When the counted value reaches a predetermined value, the data counter 208 outputs the data carry signal f and stops the counting operation (reset to 0). This counting operation is restarted from 0 when the address coincidence signal e arrives, and the preset data r coming from the preset counter 13 is loaded when the gradation increment signal h comes in. Furthermore, this data counter 2
08 outputs a data mask signal g = “H” during the counting operation (a period from the arrival of the address match signal e or the gradation step-up signal h to the output of the data carry signal f). Here, it is assumed that the number of simultaneously energizable heating elements is 6, and the data carry signal f is output when the count value of the counter is 6. The newly added preset counter 13 is composed of a hexadecimal counter equal to the number of heat-generating elements that can be energized simultaneously, increments the counter in synchronization with the gradation increment signal h, and outputs the output of the counter as preset data r. .

Next, a second method invention (operation) performed using this circuit will be described with reference to FIGS. The one-line recording operation is started by a line pulse LP coming from a main control circuit such as a CPU (not shown) for controlling the entire apparatus. At this time, the address counter 2, the gradation counter 206, the data counter 208, the preset Each count value of the counter 13 and each output of the address latch 4 and the data latch 11 are set to 0. The data mask signal g is set to "H". As shown in FIG. 5, when the line pulse LP comes in,
The address counter 2 supplies an address signal a to the memory 1
Are sequentially output from 0 to one line (up to 19), and the first reading is performed. The memory 1 outputs the gradation data b to the data comparator 5 in synchronization with the address signal a. The data comparator 5 includes a gradation counter 206
Sequentially output the results of comparison between the gray level signal i = 0 output from the memory 1 and each gray data b output from the memory 1. In this embodiment, the gradation data b is 8 at any address.
Therefore, for the gray level signal i = 0, the comparison result j = “H” is output at all the addresses.

The data counter 208 sequentially counts the period of the comparison result j = “H”, and when the count value reaches 6, as shown by the signal waveform S in FIG. And the address signal a =
5 is held in the address latch 4 as a latch output d,
The counting operation ends. Also, the data counter 208
The data mask signal g = “H” is output only during the period when the address signal a is 0 to 5. As a result, the output k of the AND gate 9 in the first reading becomes “H” only during the 6 dot period (address = 0, 1, 2, 3, 4, 5), and thereafter, the data mask signal g becomes “H”. Since it is “L”, the comparison result j
, The output k of the AND gate 9 also becomes "L".

The output k of the AND gate 9 supplied as a serial input signal to the shift register 10 is sequentially converted into 20-bit parallel data m in synchronization with a read clock. When the address counter 2 outputs the address signal a for one line and the shift register 10 converts the AND gate output k (the first comparison result) for one line into parallel, the address counter 2 outputs the address carry signal c. It outputs a latch pulse p. In addition, the first comparison result m subjected to the parallel conversion is held in the data latch 11 by the latch pulse p. This data latch 11
Address = 0,1,2,3,4,5 by the output signal n of
Only the six heating elements R ₀ , R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ are energized until the next latch pulse arrives (second reading period).

Address carry signal c and latch pulse p
Is output and when the first reading is completed,
The second reading is performed by the address counter 2 as in the first reading. In the second reading, the data mask signal g is "L" until the address signal a becomes 5, but when the address signal a becomes 5, the address comparator 3 outputs the address match signal e. In response, the data counter 208 restarts the counting operation from the comparison result j for the address a = 6, and at the same time, sets the data mask signal g to "H". As in the first time, the data counter 208 performs a counting operation until the count value reaches 6, and when the count value reaches 6, outputs the data carry signal f. The address signal a = 12 at this time is held in the address latch 4. Then, the counting operation ends. Further, the data mask signal g thereafter is set to “L”. As a result of this second reading, in the parallel output m of the shift register 10, only the bits of the address = 6, 7, 8, 9, 10, 11 become "H". At the same time, during the second readout period, the output to the data latch 11 causes the first comparison result (heating elements: R ₀ , R ₁ , R ₂ , R ₃ , R ₄ , R ₅ ) to be energized. Done.

Similarly, in the third reading, only the bits of the address = 12, 13, 14, 15, 16, and 17 of the parallel output m become “H”. During this time, the second comparison result is energized. In the fourth read, address = 18,
Only the 19 bits become "H", and during this time, the energization for the third comparison result is performed. By this fourth reading, the gradation data for one line and the gradation level signal i
= 0, and when all the comparison results are transferred to the shift register (the address carry signal c is input while the data mask signal g is "H"), the control circuit 20
7 outputs a gradation step signal h. This gradation step signal h
, The address latch 4 is cleared, the gradation counter 206 increases the count value by 1, sets the gradation level signal to i = 1, the preset counter 13 increases the count value by 1, and sets the preset data. It is assumed that r = 1. The data counter 208 is loaded with the preset data r = 1 at the start of the next (fifth) reading, and continues the counting state (data mask signal g = “H”) from the loaded value.

From the fifth reading, each gradation data b
Is started, and the data comparator 5 outputs a comparison result j = “H” for all the address signals a. On the other hand, data counter 2
08 starts counting from the count value = 1, the count value becomes 6 when the address signal a = 4 (the data mask signal g
Is "H" during the period of the address signal a = 0 to 4), and the parallel output m of the shift register 10 has the address = 0, 1,.
Only the five bits 2, 3, and 4 become "H". In the sixth and subsequent readings, similarly to the first to third readings, the results of the comparison with the gradation level signal i = 1 are counted in order from the smallest address so that the number of simultaneously energized dots becomes six. Divide and transfer. Gradation level signal i
When all the comparison results for one line with respect to = 1 are transferred to the shift register (the eighth reading is completed),
The control circuit 207 outputs a gradation step signal h, increases the gradation level signal i and the preset data r by one, and
= 2, r = 2. The preset data r = 2 is loaded into the data counter 8 at the start of the next reading.

Similarly, at the time of the first reading in which the gradation level signal changes (increases), the data counter is counted from an initial value different for each gradation level, so that the current is simultaneously supplied for each gradation level. Heating element position (division position)
Is performed while varying the number of gray levels (pulse number modulation). FIG. 6 is a schematic diagram showing the energized state of each heating element. Here, the dots to which the heating elements adjacent to the left and right are energized at the same time are indicated by hatched circles in the figure, and the dots to which at least the heating elements adjacent to at least one side are not energized at the same time are indicated by white circles. Further, the position of the heating element is shown in the horizontal direction, and the gradation level signal i at the time of reading is shown in the vertical direction. Furthermore, although the first comparison result is normally energized at the time of the second reading, in this figure, the gray level signal at the time of reading and the energization state are shown at the same vertical position for simplicity.

In this embodiment, different initial values are loaded to the data counter for each gradation level.
A different initial value may be loaded for each gradation level (N ≧ 2). In this case, the same effect as described above can be obtained. In binary recording in which grayscale data is composed of one bit, a similar effect can be obtained by loading a different initial value for each N (N ≧ 1) line. Further, the number of addresses (the number of pixels) and the number of gradation levels in each of the embodiments described above are merely examples, and are not limited thereto.

[0034]

As described above, according to the thermal head division driving method of the present invention, the following excellent operational effects can be exhibited. According to the first method invention,
The position of the heating element that is driven during a period when the amount of heat generation is greater than other periods (when the number of simultaneously energized heating elements is less than a predetermined value) does not deviate to a specific position (direction) as in the related art. Since the right end and the left end of the heating element to be energized at the gradation level are alternately changed for each gradation level, the difference in the amount of heat (difference in recording density) caused by the difference in the number of simultaneously energized heating elements is reduced. Can be reduced. According to the second method invention, each time the gradation level is switched, a different initial value is given to the counter for counting the number of heating elements to be simultaneously energized, so that the division position of the heating element to be simultaneously energized at each gradation level Can be changed, so that the occurrence of [white streaks] can be suppressed even in an area where uniform gradation data is recorded, for example.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a head driving circuit that performs a first thermal head division driving method of the present invention.

FIG. 2 is a timing chart showing signals of main parts in the block diagram of FIG. 1;

FIG. 3 is a diagram showing an energized state of each heating element in FIG. 1;

FIG. 4 is a block diagram showing a head driving circuit that performs a first thermal head division driving method of the present invention.

5 is a timing chart showing signals of main parts in the block diagram of FIG. 4;

FIG. 6 is a diagram showing the energized state of each heating element in FIG.

FIG. 7 is a block diagram showing a conventional head drive circuit.

FIG. 8 is a diagram showing an input / output relationship of a comparator.

FIG. 9 is a timing chart showing signals of main parts in FIG. 7;

FIG. 10 is a schematic diagram showing the energized state of each heating element.

FIG. 11 is a schematic diagram showing the energized state of each heating element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory, 2 ... Address counter, 3 ... Address comparator, 4 ... Address latch, 5 ... Data comparator, 7 ... Control circuit, 8 ... Data counter, 10 ... Shift register, 11 ... Data latch, 13 ... Preset counter, 102 ... address counter, 107 ... control circuit,
110: shift register, 208: data counter, R
_{0 to} R ₁₉ ... heating element.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yu Endo 3-12 Moriyacho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture F-term in JVC, Ltd. (reference) 2C066 AA05 AA18 AB02 AB03 AB07 AD03 CD07 CF03 CF09 CF12

Claims (2)

[Claims] An electric current for one line or one gradation level is supplied to a plurality of heating elements arranged on a thermal head.
In the thermal head division driving method in which the number of pixels to be simultaneously energized is reduced to a certain value or less and divided and driven in a plurality of times while counting, the counting order of the energized pixels for determining the division position is set to N
(N is 1 or more) A thermal head division driving method characterized in that it differs for each gradation level. 2. Energizing one line or one gradation level to a plurality of heating elements arranged on a thermal head,
In a thermal head division driving method in which the number of pixels to be simultaneously energized is reduced to a certain value or less and divided and driven a plurality of times while counting, a counting initial value of the number of energized pixels for determining a division position is defined as:
A thermal head division driving method, wherein the method is different for each of N lines or N (N is 1 or more) gradation levels.