JP2000244293A - Circuit and method for selecting signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multi-stage multiplexer type signal selecting circuit with which power consumption is saved by suppressing a switching operation. SOLUTION: The circuit is constituted of seven multiplexers M00-M20 which are connected in a three-stage tree shape. They select one of input signals A and B in accordance with control signals S2, S1 and S0 and output it when an updating permission signal ENA of a state 1 is inputted from an external part, supply the updating permission signal E of the state 1 to the low-order multiplexer which is selected and supply the updating permission signal E of the state 0 to the low-order multiplexer which is not selected. The multiplexer to which the signal E of the state 0 is supplied holds previous contents and the switching operation is stopped. In a result, switching is operated only in the multiplexer where the input signals D0-D7 outputted as an output signal OUT pass through and one of the input signals D0-D7 is selected and outputted to an external bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal selection circuit and method, and more particularly to a technique for reducing power consumption when an input signal is selected and output by a multi-stage multiplexer type signal selection circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, when data is transferred between a plurality of blocks via a common signal line (bus), a signal selecting circuit for selecting a block for selecting a signal on the bus is required. Generally, a tri-state buffer or a multi-stage multiplexer is often used as such a signal selection circuit.

When a tri-state buffer is used as a signal selection circuit, only one buffer needs to be driven accurately at all timings. That is, if there is a period in which a plurality of buffers drive the bus at the same time, a short circuit occurs.
All of them induce a through current and increase power consumption. There is also a problem that the tristate processing is not suitable for automatic design using a design support device. Therefore, in a semiconductor integrated circuit aiming at low power consumption, a multi-stage multiplexer is often used as a signal selection circuit as described above.

FIG. 6 is a block diagram showing the configuration of a conventional multi-stage multiplexer type signal selection circuit. As shown in the figure, this signal selection circuit includes seven multiplexers m00 to m2 connected in a three-stage tree form.
0, and selects one of the eight sets of input signals d0 to d7 and outputs it as an output signal out.

FIG. 7 is a diagram showing a circuit configuration of each of the multiplexers m00 to m20 included in the signal selection circuit of FIG. When the selection signal c is at logic level 1, the input signal a conducts to the output signal o, and when it is 0, the input signal b conducts to the output signal o. In the case of the connection as shown in FIG. 6, each of the multiplexers m00 to m20 always selects one of the two inputs, so that there is no fear of short circuit or floating.

Further, each of the multiplexers m00 to m20
Is a simple combinational circuit, so automatic design is easy. Further, each of the multiplexers m00 to m20
Control signals s2, s1, and s0 are common to the stages, and generally, the control signals s2, s1, and s0 need only be directly input with the address signals to be selected. It's easy.

[0007]

However, the conventional signal selection circuit described above has a drawback that the control is shifted to the control of an unused multiplexer. For example, when the control signals s2, s1, and s0 are 0, 0, and 0, respectively, and the user wants to select the input signal d0, the output signal out is output from the multiplexer m00, the multiplexer m10, and the multiplexer m.
Since the signal passes through the control signal 20, it is only necessary to change the control signal input thereto if the control signal is different from the intended purpose. However, if the control of the multiplexer m00 is to be changed, the control of the multiplexer m03, the multiplexer m02, and the multiplexer m01 is also changed, and if the control of the multiplexer m10 is to be changed, the control of the multiplexer m11 is also changed.

Generally, each of the multiplexers m00-m09
The signal lines passing between them are often multi-bit and very long wires for connecting the blocks.
Therefore, unnecessary switching here significantly increases the power consumption of the entire signal selection circuit. For example, it is manufactured with the minimum processing size of 0.25um and the whole chip has 20mA
A processor operating at 33 MHz that consumes only about
The wiring between the multiplexers is about 1 mm with a 32-bit width, and the number of blocks selected by the multiplexer is three.
If there are two, the current consumption between each multiplexer is about 0.5.
25 mA. When all the signals transition, there are 31 points, and the current consumption reaches a maximum of 7.80 mA.

On the other hand, in order to suppress such unnecessary current consumption, a signal for individually controlling each multiplexer is previously generated from a control system without using a common line such as control signals s2, s1, and s0. It is also conceivable.
However, as the number of control signals increases, the clock constantly consumes current even when the bus is not used, the control becomes complicated and the machine cycle of the control system is reduced, and the number of control lines from the control system to the bus is increased. Problems such as an increase in In addition, it is generally difficult to solve problems such as glitches generated between multiplexers by individual control from a control system.

An object of the present invention is to provide a signal selection circuit and a method capable of reducing power consumption by suppressing a switching operation.

[0011]

In order to achieve the above object, a signal selection circuit according to a first aspect of the present invention comprises a signal selection circuit for selecting one of a plurality of signals input according to a control signal supplied from the outside. A plurality of multiplexers that select and output the selected signal are connected in multiple stages in a tree form, and one of the input signals input to all the multiplexers at the lowest stage is selected by selecting the signal at each multiplexer. A signal selection circuit that outputs as an output signal from an upper-stage multiplexer, wherein each of the plurality of multiplexers receives a signal from a plurality of input signals when an externally supplied update permission signal is in a first state. Means for selecting and outputting a signal according to the control signal, and irrespective of the control signal when the update permission signal is in the second state Means for maintaining a signal to be selectively output, wherein each of the plurality of multiplexers other than the lowest stage receives a first state update permission signal according to the control signal. Means for supplying a first state update permission signal to a lower-stage multiplexer for supplying a selected and output signal; and selecting and outputting the first state update permission signal when the first state update permission signal is supplied. To the lower stage multiplexer that supplies the
Means for supplying an update permission signal for the second state, and means for supplying an update permission signal for the second state to all connected lower multiplexers when the second state update permission signal is supplied. It is characterized by having.

Here, the control signals supplied from outside to the plurality of multiplexers may be the same between the multiplexers in the same hierarchical stage.

In the above-mentioned signal selection circuit, the update enable signal in the first state is supplied only to the multiplexer supplying the signal selected by the higher-level multiplexer, and the multiplexer in the second state is supplied to the multiplexers not selected. An update permission signal is supplied. That is, in the multiplexers other than the one through which the input signal output as the final output signal from the multiplexer at the highest stage passes, there is no switching of the signal being selectively output. As described above, the signal selection circuit does not perform an unnecessary switching operation at a place irrelevant to the final output signal, and can reduce power consumption as compared with the related art.

Further, since the signal selection circuit can supply the same control signal to the multiplexers in the same hierarchical stage, it is necessary to supply different control signals to each of the plurality of multiplexers. Nor.
For this reason, the signal selection circuit improves the layout and wiring efficiency, and can reduce power consumption without increasing clock addition.

In order to achieve the above object, a signal selection circuit according to a second aspect of the present invention is supplied with a control signal and an inverted control signal obtained by inverting the state of the control signal. It is configured by connecting a plurality of multiplexers that select and output any one of two input signals in a multi-tiered manner in a tree form, and the signals are input to all the multiplexers in the lowest stage by selecting the signal in each multiplexer. A signal selection circuit for outputting any one of the input signals as an output signal from a multiplexer at the highest stage, wherein each of the plurality of multiplexers is configured such that when an externally supplied update permission signal is in a first state. The state of the control signal supplied from the outside is captured and held, and when the update permission signal is in the second state, the state is held and held. And outputs the held control signal and an inverted control signal obtained by inverting the state as a control signal and an inverted control signal for selecting one of the two signals by the multiplexer. Each of the plurality of multiplexers, except for the lowest stage, performs a logical operation on an update permission signal supplied from the outside with each of the control signal and the inverted signal output by the state holding unit. And each of the operation results by the two logical operation means is connected to the lower part of the multiplexer.
Update enable signal generating means for outputting the update enable signal to one of the plurality of multiplexers, and the highest one of the plurality of multiplexers outputs the first state update signal to the flip-flop and the update enable signal generating means. The permission signal is supplied from outside.

Here, the control signals supplied to the state holding means included in the plurality of multiplexers may be the same between the multiplexers of the same hierarchical level.

In the signal selection circuit, a multiplexer through which an input signal selected and output as a final output signal from the uppermost stage multiplexer does not pass, that is, a multiplexer that supplies a signal not selected by the upper stage multiplexer. The state holding means is supplied with an update permission signal in the second state from the update permission signal generation means of the multiplexer in the upper stage. Therefore, the state of the control signal and the inverted control signal output from the state holding means does not change, and unnecessary switching operation is not performed. For this reason,
Compared to the conventional multi-stage multiplexer type signal selection circuit,
Power consumption can be reduced.

On the other hand, an update permission signal of the first state is supplied to the state holding means of the multiplexer through which the input signal selected and output as the final output signal passes, and the signal is supplied in response to an external control signal. Since the output is selected, the input signal input to the multiplexer at the lowest stage is correctly selected and output from the multiplexer at the highest stage according to the control signal supplied from the outside.

Further, since the signal selection circuit can make the same control signal supplied to the state holding means of the multiplexers of the same hierarchical stage, different control signals are supplied to each of the plurality of multiplexers. There is no need to supply. For this reason, the signal selection circuit improves the layout and wiring efficiency, and can reduce power consumption without increasing clock addition.

In the above-mentioned signal selection circuit, the lowest-order stage multiplexer may have the same means as the update permission signal generating means in the higher-order stage. However, in this case, there is no multiplexer to which the update permission signal generated by the means is supplied.

In the above-mentioned signal selection circuit, the plurality of multiplexers cause the update permission signal to be in a second state for a predetermined period when the update permission signal in the first state is supplied, and for the predetermined period to elapse. After that, the first state may be further provided with timing control means for supplying the state to the state holding means.

By providing such a timing control means, the control signal output from the state holding means is supplied before the update permission signal of the original state is supplied from the update permission signal generation means of the multiplexer in the upper stage. There is no transition. For this reason, the order that the control signal supplied to the upper-stage multiplexer transitions and then the control signal supplied to the lower-stage multiplexer transitions is maintained, and the control signal externally supplied to the state holding means of each multiplexer is maintained. The operation state does not become unstable due to the change.

In the signal selection circuit, each of the plurality of multiplexers delays a control signal and an inversion control signal output from the state holding means for a predetermined time, and the multiplexer selects one of the two signals. A delay unit that outputs the control signal and the inverted control signal may be further provided. In this case, the predetermined time for the delay means of each multiplexer to delay the control signal and the inversion control can be set longer for the higher-order multiplexer.

By providing such a delay means in each multiplexer, a higher-order multiplexer outputs a higher-order signal before a signal selected and output changes due to a change in an externally supplied control signal. The signal selected and output by the multiplexer at the stage does not transition. For this reason, the signal selected and output from the same multiplexer is never switched over a plurality of times.
Since the switching operation of the entire multiplexer constituting the signal selection circuit can be reliably suppressed to the minimum, power consumption is reduced as compared with the conventional signal selection circuit.

In order to achieve the above object, a signal selection method according to a third aspect of the present invention is to select and output one of a plurality of signals input according to a control signal supplied from outside. A multi-stage multiplexer configured by connecting a plurality of multiplexers in a multi-stage in a tree form, and by selecting a signal in each multiplexer, one of the input signals input to all the multiplexers in the lowest stage is converted to the highest-order multiplexer. A signal selecting method for outputting as an output signal from a multiplexer in a stage, wherein, when a supplied update permission signal is in a first state in each of the plurality of multiplexers, the control signal is output from the plurality of input signals. Selecting and outputting a signal according to the following, and in each of the plurality of multiplexers, Maintaining the signal to be selected and output irrespective of the control signal when the state is the state described above, and in each of the plurality of multiplexers other than the lowest stage, the update permission signal in the first state is Supplying, when supplied, an update enable signal in a first state to a lower stage multiplexer for supplying a signal selected and output according to the control signal; and a lowermost stage among the plurality of multiplexers. Supplying a second state update permission signal to a lower stage multiplexer that supplies a signal that has not been selectively output when the first state update permission signal has been supplied to each of the other elements. And when a second state update enable signal is supplied to each of the plurality of multiplexers other than the lowest stage, all of the connected lower order stages are provided. Wherein the the multiplexer and supplying an update permission signal in the second state.

[0026]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a multi-stage multiplexer type signal selection circuit according to this embodiment. As shown in the figure, this signal selection circuit is composed of seven multiplexers M00 to M20 connected in a three-stage tree form, and selects one set from eight input signals D7 to D0 having a 16-bit width. Then, it is output as an output signal OUT.

The multiplexer M00 selects either the input signal D1 or the input signal D0 according to the control signal S0,
Output to the next stage multiplexer M10. Similarly, multiplexers M03, M02, and M01 respectively provide input signal D7 or D6, input signal D5 or D4, and input signal D
Either 3 or D2 is selected and output to the next-stage multiplexers M11 and M10.

The multiplexers M11 and M10 respond to the control signal S1 and receive the preceding multiplexers M03 and M03, respectively.
02, M01, and M00, and selects one of the two sets of signals sent to the multiplexer M20. The multiplexer M20 selects one of the two sets of signals sent from the multiplexers M11 and M10 at the preceding stage according to the control signal S2, and outputs the selected signal as an output signal OUT to a bus (not shown).

FIG. 2 is a diagram showing a circuit configuration of each of the multiplexers M00 to M20 included in the signal selection circuit of FIG. As shown, the multiplexers M00 to M20
Is a multiplexer 20 composed of CMOSs 20a and 20b and a buffer 20c provided for each bit,
RS flip-flop 21 and update permission signal generation circuit 2
And 2.

The multiplexer 20 controls the control signals CA, C
When B is a combination of logic levels 1 and 0, the input signal A is made conductive to the output signal O, and when B is a combination of 0 and 1, the input signal B is made conductive to the output signal O. When the update permission signal E is 1, the RS flip-flop 21 transmits the selection signal C to the control signal CA, and transmits an inverted signal of the selection signal C to the control signal CB. When the update permission signal E is 0, the previous control signals CA and CB are held. The update permission signal generation circuit 22 outputs the control signals CA and CB as they are to the preceding multiplexers M00 to M11 as the update permission signals EA and EB when the update permission signal E is 1, and when the update permission signal E is 0, , And always outputs 0 as the update permission signals EA and EB to the multiplexers M00 to M11 at the preceding stage.

The update permission signal E supplied to the RS flip-flops 21 of the multiplexers M00 to M20 is transmitted in a direction opposite to the above-described data flow. That is, the update permission signals E of the multiplexers M03 and M02 are given by the update permission signals EA and EB output from the update permission signal generation circuit 22 of the multiplexer M11.

The update permission signal E of the multiplexers M01 and M00 is given by the update permission signals EA and EB output from the update permission signal generation circuit 22 of the multiplexer M10. The update permission signals E of the multiplexers M11 and M10 are given by the update permission signals EA and EB output from the update permission signal generation circuit 22 of the multiplexer M20. The update permission signal E of the multiplexer M20 is, as shown in FIG. 1, an update permission signal ENA supplied from outside the multi-stage multiplexer type signal selection circuit.
Given by

In the signal selection circuit shown in FIG.
The lowermost multiplexers M00 to M03 have no lower multiplexers to propagate the update permission signals EA and EB. Therefore, the multiplexer M00
To M03 may not have the update permission signal generation circuit 22 shown in FIG.

The operation of the signal selection circuit according to this embodiment will be described below. Here, control signals S2, S1, S0 supplied from outside the signal selection circuit are provided.
Are 1, 0, and 1, respectively, as an example, a case where any one of the input signals D0 to D7 is selected by the signal selection circuit and output as an output signal OUT to an external bus will be described.

First, a logic level 1 is input to the update permission signal ENA supplied to the multiplexer M20 from outside the signal selection circuit. At this time, the multiplexer M2
Since the update permission signal E of 0 becomes 1, the multiplexer M
The 20 RS flip-flop 21 receives the selection signal C connected to the control signal S2, and propagates the selection signal C to the control signal CA and the inverted signal thereof to the control signal CB. Here, since the control signal S2 is 1, the control signal C2
A is 1 and control signal CB is 0.

The multiplexer 2 of the multiplexer M20
When 0 indicates that the combination of the control signals CA and CB is 1, 0, the input signal A is conducted, and when the combination is 1, 0, the input signal B is conducted, so that the multiplexer 20 selects the input signal A. Here, the input signal A is an output signal from the multiplexer M11.

The update permission signal generating circuit 22 of the multiplexer M20 transmits the control signal CA to the update permission signal EA and the control signal CB to the update permission signal EB when the update permission signal E is "1". M2
The update permission signals EA, EB of 0 are control signals CA,
CB is transmitted as it is and becomes 1 and 0. The update permission signal EA of the multiplexer M20 becomes the update permission signal E to the multiplexer M11, and the update permission signal EB becomes the update permission signal E to the multiplexer M10.

The multiplexer M11 outputs the update permission signal E
Becomes 1 so that it operates similarly to the multiplexer M20. That is, the selection signal C becomes 0 because it is connected to the control signal S1, the control signals CA and CB become 0 and 1 by the RS flip-flop 21, and the multiplexer 20 outputs the input signal B which is the output signal from the multiplexer M02. Select The update permission signal EA output from the multiplexer M11 is 0 because the control signal CA is 0, and the update permission signal EB is 1 because the control signal CB is 1, and propagates to the multiplexers M03 and M02, respectively.

The multiplexer M02 outputs the update permission signal E
Becomes 1 so that it operates similarly to the multiplexers M20 and M11. That is, the selection signal C is 0 because it is connected to the control signal S1, and the control signals CA and CB are RS
The flip-flop 21 sets the value to 0 or 1, and the multiplexer 20 outputs the input signal B, that is, the input signals D0 to D0.
7, the input signal D5 is selected.

On the other hand, in the multiplexer M10, since the update permission signal E becomes 0, the RS flip-flop 21 is not updated, and the control signals CA and CB retain their previous values.
Therefore, the update permission signals EA and EB output from the multiplexer M10 are both set to 0 by the update permission signal generation circuit 22, and propagate to the multiplexers M01 and M00, respectively.

Multiplexers M00, M01 and M03
Operates in the same manner as the multiplexer M10 because the update permission signal E becomes 0. That is, the control signal is held, and updating of all the lower multiplexers is stopped. The update permission signal E thus input is 0, and the unselected multiplexers M10, M00, M01 and M03 are not selected.
Then, unnecessary switching does not occur.

With the above operation, the input signal D5 is output to the bus as the output signal OUT via the multiplexers M02, M11, and M20, thereby completing the signal selection. At this time, the other four multiplexers through which the signal does not pass keep the previous state because the update permission signal is always 0.

In the same manner as described above, for all combinations of the values of the control signals S2, S1, and S0 supplied from outside the signal selection circuit, any of the input signals D0 to D7 is output as the output signal OUT. Table 1 shows the relationship. In Table 1, S2 and S in the leftmost column
1, S0 indicates a combination of external control signals, and N03 to N00 in the second column from the left indicate multiplexer M0.
3 to M00 select and output signals from the input signals D0 to D7, and N11 and N10 in the third column from the left select the signals that the multiplexers M11 and M10 select and output from the signals N03 to N00 from the right. N20 in the second column
Is a signal that the multiplexer M20 selects and outputs from the signals N11 and N10, and OUT in the leftmost column is an output signal OUT that this signal selection circuit finally selects from the input signals D0 to D7 and outputs to the bus. Is shown.

[0045]

[Table 1]

As described above, in the signal selection circuit according to this embodiment, the multiplexers M00 to M11
Among them, the one in which the input signal D0 to D7 selected as the final output signal OUT from the final stage multiplexer M20 does not pass, the update permission signal E becomes 0, and the state of the flip-flop 21 is maintained. . Then, the control signals CA and CB supplied to the multiplexer 20 do not change. Therefore, the final output signal OUT
Since unnecessary switching operations in the multiplexers M00 to M11 unrelated to the above do not occur, the number of switching operations is reduced, and the power consumption of the entire signal selection circuit can be reduced.

In the signal selection circuit according to this embodiment, it is not necessary to supply individual control signals to each of the multiplexers M00 to M20. Therefore, the power consumption is reduced without increasing the clock addition.
The efficiency of placement and routing can be improved, and the clock design can be facilitated.

In each of the multiplexers M10 to M20, the update enable signals EA and EB generated by the update enable signal generating circuit 22 having a simple configuration using the control signal held by the RS flip-flop 21 are used. It is used as an update permission signal E for the multiplexers M00 to M11. For this reason, the signal selection circuit can be configured as a relatively small circuit without a large increase in the number of gates as compared with the conventional multi-stage multiplexer type signal selection circuit.

[Second Embodiment] In this embodiment, the basic configuration as a signal selection circuit is the same as that shown in the first embodiment (FIG. 1). However, in this embodiment, the circuit configuration of each of the multiplexers M00 to M20 included in the signal selection circuit is different from that of the first embodiment, and the control update timing is further higher than that of the first embodiment. It is ingenious.

FIG. 3 shows multiplexers M00 to M20 included in the signal selection circuit applied to this embodiment.
FIG. 3 is a diagram showing a circuit configuration of FIG. As shown in the figure, multiplexers M00 to M20 applied in this embodiment include:
The one-shot circuit 3 according to the first embodiment (FIG. 2)
3 is added. The RS flip-flop 21 is configured not to receive the update permission signal E from the outside but to input the update permission signal Ei output from the one-shot circuit 33. As can be seen by comparing FIG. 3 with FIG. 2, the AND circuit is replaced by an OR circuit, and the NOR circuit is replaced by a NAND circuit.

The one-shot circuit 33 outputs an update enable signal E
When the state rises to 1, it outputs 0 for a certain period from the rise timing. During this time, the RS flip-flop 21 takes in the selection signal C and outputs the control signal C
A and CB states are updated. Update permission signal generation circuit 2
1 is the lower multiplexer M10, M11 or M00
Normally, the control signals CA and CB are output as they are, but only when the update permission signal Ei output from the one-shot circuit 33 becomes zero. Even if 1 is output, it becomes 0. That is, a negative pulse is output during this time.

When the update permission signal generating circuit 22 has output the update permission signals EA and EB in the state of 0, the update permission to the lower stage is performed regardless of the update permission signal Ei output from the one-shot circuit 33. The signals EA and EB remain at 0 and do not transition.

The update enable signal ENA externally supplied to the uppermost multiplexer M20 is input as a positive pulse only when updating the output signal OUT selectively output from the signal selection circuit.

Hereinafter, the operation of the signal selection circuit according to this embodiment will be described with reference to the timing chart of FIG. First, a positive pulse is input as an update permission signal ENA supplied from the outside to the multiplexer M20. At this time, the one-shot circuit 33 of the multiplexer M20 outputs 0 for the update permission signal Ei for a certain period.

During this time, the RS flip-flop 21 of the multiplexer M20 takes in the value of the selection signal C, transitions and outputs the control signals CA and CB, and switches the signal selected and output by the multiplexer 20. on the other hand,
During this time, the update permission signal generation circuit 22 of the multiplexer M20 outputs the state 0 regardless of the values of the control signals CA and CB.
EA and EB are output.

The multiplexer M11 to which the update permission signal EA is connected and supplied as the update permission signal E performs the same operation as the multiplexer M20, triggered by the rising edge of the update permission signal Ei. On the other hand, the update permission signal EB
Is connected, and the multiplexer M10 supplied as the update permission signal E does nothing because the rising edge is not included in the update permission signal Ei. Similarly, since the multiplexers of each stage are activated by using the end of the control pulse of the previous stage as a trigger, the control is not switched simultaneously with the previous stage.

Although not shown in the timing chart of FIG. 7, the same processing is performed when the selection signal C has the same value as in the previous cycle. That is, in the case of the multiplexers M00 to M20 in which the selection signal C remains 0 and does not switch, the control signal C
A is 0, and the update permission signal EA is also 0. In this case, the update permission signal EA to the lower stage is always output as 0 by the update permission signal generation circuit 22 regardless of whether or not a pulse is included in the update permission signal Ei. That is, the pulse is not transmitted to the lower stage. Therefore, no control pulse is input to all multiplexers below this stage, and the previous state is maintained.

On the other hand, at this time, the update permission signal E
Although B outputs 1, it outputs 0 during the period in which a negative pulse is output as the update permission signal Ei, and returns to 1 after the end of the pulse. Here, a rising edge occurs,
The lower multiplexer operates as described above assuming that the update permission signal pulse is input to the update permission signal Ei.

By the above operation, each multiplexer M0
0 to M20 change their operation only during the period in which the update permission signal Ei of the state 1 is in, but the pulse of the update permission signal Ei is sequentially propagated only in the multiplexers M00 to M20 which always need to be updated as a whole, It can be seen that the other multiplexers do not change.

In the signal selection circuit according to this embodiment, the order of updating is maintained and the timing is shifted at each stage, so that the control does not change redundantly. In each stage, the update enable signal of the unused multiplexer is always invalidated before proceeding to the next stage. Therefore, in the signal selection circuit according to this embodiment, in addition to the effects of the first embodiment, problems such as glitches which occur at the time of control switching and greatly affect power consumption are easily eliminated. A new effect is obtained.

[Third Embodiment] In this embodiment, the basic configuration as a signal selection circuit is the same as that shown in the first embodiment (FIG. 1). However, in this embodiment, the circuit configuration of each of the multiplexers M00 to M20 included in the signal selection circuit is different from that of the first embodiment, and the control update timing is that of the first and second embodiments. It is even more creative than it is.

FIG. 5 shows each of the multiplexers M00 to M20 included in the signal selection circuit applied to this embodiment.
FIG. 3 is a diagram showing a circuit configuration of FIG. As shown in the figure, multiplexers M00 to M20 applied in this embodiment include:
The configuration is such that a delay circuit 44 is added to that of the second embodiment (FIG. 3).

The delay circuit 44 includes the RS flip-flop 2
The control signals CA and CB output from 1 are delayed by an inverter having an even number of stages.
Adjust the timing of switching. Specifically, the delay circuit 44 includes an upper-stage multiplexer (M20 for M10 and M11 and M10 and M1 for M00 to M03).
The control of 1) is sufficiently delayed so that the signal selected and output by the lower multiplexer is always switched first. That is, the multiplexers M20, M in the upper stage
10, the delay time of the delay circuit 44 is longer for M11.

For this purpose, the delay circuit 44 updates the update permission signal EA, EA,
The EB propagates to the lower stage, and a longer delay time is generated in anticipation of the time from when the selection is switched to the return and the input signal returns. Since the delay circuit 44 is inserted between the update permission signals EA and EB and the multiplexer 40, the update permission signals EA and EB propagate to the lower multiplexer at the same timing as in FIG. The multiplexer is switched after the delay time of the delay circuit 44.

As described above, when the upper stage selects the input opposite to the path to be selected, the transition of the input signal due to the control change in the lower stage does not propagate earlier than the upper stage.
When the upper stage has already selected the path to be selected, the control of the multiplexer at the upper stage does not transition, so that the output load is not driven again. For this reason, the loads on the signal propagation path are driven exactly once, and it is possible to avoid the possibility that the same load is driven repeatedly, and to logically propagate the signal with the minimum number of switching times. Can be.

[Modifications of Embodiment] The present invention is not limited to the above-described first to third embodiments, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the first to third embodiments, the 16
The case has been described in which any one of eight sets of input signals D0 to D7 having a bit width is selected and output as output signal OUT. However, the present invention can be applied regardless of the bit width of an input signal or the number of input signal sets to be selected. In this case, an appropriate number of multiplexers may be connected in multiple stages in a tree form according to the number of sets of input signals.

In the first to third embodiments, each of the multiplexers M00 to M20 constituting the multi-stage multiplexer type signal selection circuit selects and outputs one set from two sets of input signals. Was. However, as each multiplexer constituting the multi-stage multiplexer type signal selection circuit, a multiplexer that selects one set from two or more sets of input signals can be used. Also in this case, an appropriate number and configuration of multiplexers may be connected in multiple stages in a tree form according to the number of sets of input signals to each multiplexer and the number of sets of input signals to the entire signal selection circuit.

In the first to third embodiments, the multiplexers M00 to M20, and the RS flip-flop 21, the update permission signal generation circuit 22, the one-shot circuit 33, and the delay circuit 44, which constitute the multiplexers M00 to M20, have a positive logic. Although the configuration is made by using logic, it may be configured by using illogical logic.

In the above-described first to third embodiments, for simplicity of description, only essential elements are shown in the drawings. However, in a circuit actually formed on a semiconductor integrated circuit chip, optimization of logic between components, insertion of a buffer for driving wiring, adjustment of timing for preventing glitches, and the like are performed.

[0071]

As described above, according to the present invention,
A multiplexer that does not pass an input signal that is finally output as an output signal does not need to perform a switching operation, so that power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a multi-stage multiplexer-type signal selection circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of FIG. 1 applied in a first embodiment of the present invention;
3 is a diagram showing a circuit configuration of each multiplexer included in the signal selection circuit of FIG.

FIG. 3 is a diagram showing a configuration of FIG. 1 applied in a second embodiment of the present invention;
3 is a diagram showing a circuit configuration of each multiplexer included in the signal selection circuit of FIG.

FIG. 4 is a timing chart showing an operation of the signal selection circuit of FIG. 3;

FIG. 5 is a diagram illustrating the configuration of FIG. 1 applied in a third embodiment of the present invention;
3 is a diagram showing a circuit configuration of each multiplexer included in the signal selection circuit of FIG.

FIG. 6 is a block diagram showing a configuration of a multistage multiplexer type signal selection circuit according to a conventional example.

FIG. 7 is a diagram showing a circuit configuration of each multiplexer included in the signal selection circuit of FIG. 6;

[Explanation of symbols]

 M00 to M20 Multiplexer 20 Multiplexer 21 RS flip-flop 22 Update permission signal generation circuit 33 One shot circuit 44 Delay circuit

Claims (7)

[Claims] A plurality of multiplexers each of which selects one of a plurality of signals input according to a control signal supplied from the outside and outputs the selected signal, the plurality of multiplexers being connected in multiple stages in a tree shape, A signal selection circuit that outputs any of the input signals input to all the multiplexers at the lowest stage as an output signal from the multiplexer at the highest stage by selecting the signal at Means for selecting and outputting a signal according to the control signal from a plurality of input signals when the update permission signal supplied from the outside is in a first state, and wherein the update permission signal is in a second state Means for maintaining a signal to be selected and output irrespective of the control signal in the case of When the first stage update permission signal is supplied to each of the stages other than the first stage, the lower stage multiplexer that supplies the signal selected and output in accordance with the control signal outputs the first state update permission. Means for supplying a signal, and, when the update permission signal in the first state is supplied, supplying the update permission signal in the second state to a lower-stage multiplexer for supplying a signal not selected and output. Means for supplying a second state update permission signal to all connected lower multiplexers when the second state update permission signal is supplied. . 2. The signal selection circuit according to claim 1, wherein the control signals supplied from outside to the plurality of multiplexers are the same between the multiplexers in the same hierarchical stage. 3. A plurality of multiplexers, which are supplied with a control signal and an inverted control signal whose state is inverted, and select and output one of two signals input according to the state of the control signal and the inverted control signal. It is configured by connecting in multiple stages in a tree form, and by selecting a signal in each multiplexer, one of the input signals input to all the multiplexers at the lowest stage is output as an output signal from the multiplexer at the highest stage A signal selection circuit, wherein each of the plurality of multiplexers captures and holds a state of the externally supplied control signal when the externally supplied update permission signal is in a first state, When the update permission signal is in the second state, the state of the held control signal is maintained, and the held control signal and its state are inverted. A state holding means for outputting the inverted inverted control signal as a control signal for selecting either one of the two signals by the multiplexer and an inverted control signal, wherein the plurality of multiplexers other than the lowest stage are provided. Has two logic operation means for performing a logical operation on an update permission signal supplied from the outside with each of the control signal and the inverted signal output by the state holding means,
Update enable signal generating means for outputting each of the operation results by the two logical operation means to two multiplexers connected below the multiplexer as an update enable signal, and an uppermost stage among the plurality of multiplexers A signal selection circuit, wherein an update permission signal in a first state is externally supplied to the flip-flop and the update permission signal generating means. 4. The signal selection circuit according to claim 3, wherein the control signals supplied to the state holding means included in the plurality of multiplexers are the same among the multiplexers in the same hierarchical stage. 5. When a plurality of multiplexers are supplied with an update permission signal in a first state, the plurality of multiplexers set the update permission signal in a second state for a predetermined period, and after the predetermined period elapses, change the first state to a first state. 5. The signal selection circuit according to claim 3, further comprising a timing control unit that supplies the state to the state holding unit. 6. Each of the plurality of multiplexers includes:
A delay unit that delays the control signal and the inversion control signal output from the state holding unit by a predetermined time, and outputs the control signal and the inversion control signal for selecting one of the two signals by the multiplexer; 6. The predetermined time for the delay means to delay the control signal and the inversion control is longer for the higher-order multiplexer.
The signal selection circuit according to the paragraph. 7. A multi-stage multiplexer constituted by connecting a plurality of multiplexers each of which selects one of a plurality of signals input according to a control signal supplied from the outside and outputs the selected signal in a tree-type multi-stage. A signal selection method for outputting any one of the input signals input to all of the multiplexers at the lowest stage as an output signal from the multiplexer at the highest stage by selecting a signal at each multiplexer; A step of selecting and outputting a signal according to the control signal from a plurality of input signals when each of the multiplexers has the supplied update permission signal in the first state; When the update permission signal is in the second state, a signal to be selected and output regardless of the control signal is output. Supplying a signal selected and output according to the control signal when an update permission signal in the first state is supplied to each of the plurality of multiplexers other than the lowest stage. Supplying a first state update permission signal to a lower stage multiplexer; and a case where the first state update permission signal is supplied to each of the plurality of multiplexers other than the lowest stage. Supplying a second-stage update enable signal to a lower-stage multiplexer that supplies a signal that has not been selectively output; and in each of the plurality of multiplexers other than the lowest-stage, Supplying a second state update permission signal to all connected lower multiplexers when the second state update permission signal is supplied; A signal selection method comprising: