JP2000242613A - Meta address architecture and address specifying method for dynamic reconstitution calculation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform reprogramming. SOLUTION: This meta address specifying architecture for specifying a local memory destination for a data packet for the network of a dynamic reprogrammable processing machine is constructed by plural address specifying machines 14 provided with an unique geographical address for executing interruption, generating and transmitting a meta address including the geographical address and a local address and making respective messages stand by, the plural dynamic reprogrammable processing machines 12 connected to at least one address specifying machine for storing, retrieving and processing data from a local memory device corresponding to the received local address, plural memory devices relating to the dynamic reprogrammable processing machines 12 and an interconnection device 16 connected to the address specifying machines 14 for routing the data between the address specifying machines corresponding to the geographical address included in the meta address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to computer architecture, and more particularly to a system and method for reconfiguration computation, that is, a meta-address architecture and addressing method for dynamic reconfiguration computation.

[0002] The present invention is disclosed in US Pat. U.S. Pat. Patent application no. This is a priority application based on the U.S. Serial No. 09 / 031,323.

[0003]

2. Description of the Related Art Advances in computer architecture include:
Driven by the demand for better computing performance.
To quickly and accurately solve various types of computational problems, different types of computational resources are generally required. If the type of problem is limited, computational performance can be improved by using computational resources specifically constructed for the type of problem under consideration. For example, when digital signal processing (DSP) hardware is used in combination with a general-purpose computer, certain signal processing capabilities can be significantly improved. When the computer itself is specially constructed for the type of problem under consideration, the computational performance for these particular types of problems will be further improved, or perhaps further optimized, relative to the available computational resources. It was done. Current parallel computers and massively parallel computers are
Excellent handling of special types of problems (n ² ) or more, which is an example in the above case.

While good computational performance is required, it must be balanced with the need to minimize system costs and maximize system productivity in the widest possible range of current and future applications. Needs to be balanced. In general, specialized hardware is more expensive than general-purpose hardware,
Incorporating computing resources dedicated to a limited number of problems into a computer system has a negative impact on keeping system costs low. Designing and producing a special purpose computer is extremely expensive in terms of engineering time and hardware costs. In the case where dedicated hardware is used to enhance the calculation performance, if the degree of calculation performance changes, the performance advantage decreases. In the prior art, as computational performance needs change, new dedicated hardware or new dedicated systems are designed and manufactured, resulting in recurring undesirably high non-reusable design and manufacturing costs. Thus, using computation resources dedicated to a particular type of problem results in inefficient use of available silicon resources when the computational needs change. For this reason, it is not desirable to use dedicated hardware to improve the calculation performance.

In the past, various attempts have been made to improve computational performance using reprogrammable or reconfigurable hardware and to maximize the applicability of the type of problem. The first such prior art approach relies on a downloadable microcode computer architecture. In a downloadable microarchitecture, the functionality of fixed non-reconfigurable hardware resources can be selectively varied by using a particular version of microcode. An example of such an architecture is the IBM System / 360. Since the basic computing hardware of such prior art systems is not reconfigurable itself,
When considering a wide variety of problems, such systems do not provide optimized computational performance.

A second prior art approach to improving computational performance and maximizing the applicability of a type of problem uses reconfigurable hardware coupled to a non-reconfigurable host processor or host system. That is.
This prior art approach most commonly utilizes one or more reconfigurable processors coupled to a non-reconfigurable host. This approach can be categorized as an "Attached Reconfigurable Processor (ARP)" architecture, where a portion of the hardware in the processor set attached to the host can be reconfigured. Examples of current additive reconfigurable processor (ARP) systems utilizing a set of reconfigurable processors coupled to a host system include SPLASH-1 and SPLASH designed by the Supercomputing Research Center (Bowie, MD).
-2, WILDFIRE Custom Configurable Computer manufactured by Annapolis Micro Systems (Annapolis, MD)
(Commercial version of SPLASH-2), Virtual Comp
EC made by uter Corporation (Reseda, California)
V-1. In many computationally intensive problems, a significant amount of time is spent executing relatively small portions of program code. Generally, additional reconfigurable processors (A
Using the (RP) architecture, a reconstruction computation accelerator is provided for such portions of program code.

[0007]

Unfortunately, computational models based on one or more reconstructed computational accelerators have significant disadvantages, as described in detail below.

First disadvantage The first disadvantage of the incrementally reconfigurable processor (ARP) architecture is that when the incrementally reconfigurable processor (ARP) system is specific, the optimal implementation of the specific algorithm of the reconfigurable hardware is not possible. Happens to try to perform the mobilization.

For example, Virtual Computer Corporation
The design philosophy behind the ECV-1 is to translate that particular algorithm into a particular configuration of reconfigured hardware sources to provide optimal computational performance for that particular algorithm. Reconfigured hardware resources are used only to provide optimal performance for a particular algorithm. Using reconfigurable hardware resources for general purposes such as managing instruction execution is avoided. Thus, for a given algorithm, the reconfigured hardware resources are considered from an overview of the individual gates combined for optimal performance.

Some additional reconfigurable processors (ARs)
P) Systems rely on a programming model in which a "program" includes both conventional program instructions and dedicated instructions that define how the various reconfigurable hardware resources are interconnected. Since the additive reconfigurable processor (ARP) system considers the reconfigurable hardware resources in a unique manner appropriate for the gate-level algorithm, these dedicated instructions provide detailed information about the characteristics of each reconfigurable hardware resource used. Content and
A method must be provided in which reconfigured hardware resources are combined with other reconfigured hardware resources.
This makes the program complicated. Attempts have been made to use programming models that include both conventional high-level programming language instructions and high-level dedicated instructions in programs to reduce programming complexity. That is, current additive reconfigurable processor (ARP) systems attempt to utilize a compilation system that can compile both high-level programming language instructions and the high-level dedicated instructions described above. The intended output of such a compilation system is assembly language code for conventional high-level programming language instructions, and hardware description language (HDL) for dedicated instructions.
anguage). Automatically determining a set of reconfigured hardware resources and interconnection schemes for optimal computational performance for the particular algorithm under consideration is:
Unfortunately, it is an NP hardware problem. The long-term goal of some additive reconfigurable processor (ARP) systems is to develop a compilation system that can compile algorithms directly into an optimized interconnection scheme for a set of gates. However, developing such a compilation system is an extremely difficult task, especially when considering multiple types of algorithms.

<Second Disadvantage> A second disadvantage of the additively reconfigurable processor (ARP) architecture is that the computational work associated with the algorithms that make up the incrementally reconfigurable processor (ARP) device is performed by the additional reconfigurable processor. (A
RP) occurs because devices are spread across multiple reconfigurable logic devices.

For example, an additional reconfigurable processor (ARP) device implemented using a set of field-programmable logic circuits (FPGAs) and configured to implement a parallel multiplication accelerator may be associated with parallel multiplication. The calculated work is distributed throughout the field programmable logic circuit (FPGA). Therefore, the size of the algorithm that can constitute an additional reconfigurable processor (ARP) device is limited by the number of reconfigurable logic devices present. Similarly, the additional reconfigurable processor (A
The size of the largest data set that the RP) device can handle is also limited. Because some algorithms have data dependencies, testing source code does not always explicitly indicate the limitations of additional reconfigurable processor (ARP) devices. Generally, data dependency algorithms are avoided.

Further, an additional reconfigurable processor (AR)
P) Because the architecture discloses distributing the computational work across multiple reconfigurable logic units, the reconfiguration must be performed in batches to include new or slightly modified algorithms. That is, the multiple reconfigurable logic device must be reconfigured. This limits the maximum rate at which reconstruction can be performed for another problem or a cascaded secondary problem.

<Third Disadvantage> A third disadvantage of the additively reconfigurable processor (ARP) architecture arises because one or more portions of the program code are executed on the host.

That is, the additional reconfigurable processor (A
RP) device is not an independent computing system itself,
It does not execute the entire program. This requires interaction with the host. Since some program code runs on a non-reconfigured host, available silicon resources are not fully utilized in the time frame of program execution. In particular, during the execution of instructions by the host, the silicon resources of the additional reconfigurable processor (ARP) device are idle or inefficiently utilized.
Similarly, utilization of silicon resources at the host is generally inefficient when additional reconfigurable processor (ARP) devices process data. In order to easily execute all of the programs, the silicon resources in the system must be grouped into resources that can be easily reused. As described above, additive reconfigurable processor (ARP) systems treat reconfigurable hardware resources as a set of gates that are optimally interconnected for the implementation of a particular algorithm at a particular time. Therefore, since an algorithm must have some degree of independence to be reusable, an additively reconfigurable processor (ARP) system uses a resource that can easily reuse a particular set of reconfigurable hardware resources for each algorithm. It does not provide a means to treat as.

An additively reconfigurable processor (ARP) device cannot handle the currently executing host program as data, and generally cannot adapt itself to the computing environment. Additional Reconfigurable Processor (AR
P) The device is not designed to simulate itself by executing its own host program. In addition, additional reconfigurable processor (AR
P) The device is not designed to compile its own hardware description language (HDL) or application program for itself, directly using the reconfigured hardware resources that are built. Accordingly, additional reconfigurable processor (ARP) devices are architecturally limited with respect to an independent computation model that discloses independence from the host processor.

An add-on reconfigurable processor (ARP) device functions as a computation accelerator and generally cannot perform independent input / output (I / O) processing. Normally,
Additional reconfigurable processor (ARP) devices require host interaction for I / O processing. Thus, the performance of an additively reconfigurable processor (ARP) device may be limited in input and output. However, those skilled in the art will recognize that additional reconfigurable processor (ARP) devices can be configured to accelerate certain input / output problems. However, additional reconfigurable processors (AR
P) Since the entire device is configured for a single particular problem, additive reconfigurable processor (ARP) devices cannot balance input / output processing and data processing without adversely affecting each other. Further, additional reconfigurable processor (ARP) devices do not provide a means for interrupt handling. Since additional reconfigurable processor (ARP) devices are aimed at maximizing computational acceleration, the disclosure of additional reconfigurable processor (ARP) does not mention such an interrupt mechanism, and Has a negative effect on computational acceleration.

<Fourth Disadvantage> A fourth disadvantage of the additively reconfigurable processor (ARP) architecture is that it has inherent data parallelism that is difficult to use with additively reconfigurable processor (ARP) devices. Caused by the presence of software applications.

A hardware description language (HDL) compilation application is one such example when very large netlists need to be deduced for netname symbols.

<Fifth Disadvantage> A fifth disadvantage of the additional reconfigurable processor (ARP) architecture is that its architecture is basically SIMD (Single Instruction S
(tream Multiple Data Stream) is a computer architecture model.

Accordingly, the additively reconfigurable processor (ARP) architecture is not as efficient as an architecture as compared to one or more innovative prior art non-reconfigurable systems. An additive reconfigurable processor (ARP) system provides, for each particular configuration example, only a small part of the process of executing a program, primarily arithmetic, for the same amount of computing power that available reconfigurable hardware can provide. Only reflects the calculation logic. In contrast, in the system design of the SYMBOL machine at Fairchild in 1971, the entire computer uses a unique hardware context for each phase of program execution. as a result,
SYMBOL will include all components for computer system applications, including the host portion disclosed by the Additive Reconfigurable Processor (ARP) system.

Other Disadvantages The additional reconfigurable processor (ARP) architecture has other disadvantages.

For example, an additional reconfigurable processor (A
RP) devices have no effective means to provide independent timing to multiple reconfigurable logic devices. Similarly, a cascaded additional reconfigurable processor (AR
P) Devices do not have effective clock distribution means to provide independently timed devices.
As another example, it may be difficult to accurately correlate execution time with the source code statement attempting to accelerate. In order to accurately calculate the net system clock rate, it is necessary to compile a hardware description language (HDL) and then execute a computer-aided design (CAD).
The er-Aided Design means must be used to model additional reconfigurable processor (ARP) devices, but reaching such basic parameters is a time consuming process.

An equally important problem with conventional architectures is that they use virtual or shared memory. The disclosure discloses the use of a unified address space, which requires more complex addressing operations, which slows down memory access and reduces efficiency. For example, to access individual bits of a memory device in a system using virtual memory, the physical address space of the memory must first be partitioned into logical addresses, and then the virtual addresses must be mapped to the logical addresses. Thus, each bit of the memory can be finally accessed. Further, in shared memory systems, memory operations are further complicated because the processor typically performs address confirmation operations before allowing access to the memory. Finally, the processor must provide coordination (arbitration) between multiple processes attempting to simultaneously access the same area of memory by providing some sort of prioritization system.

To address many of the problems caused by using shared and virtual memory, many conventional systems use a memory management system (MMU).
Most of the memory management functions such as conversion of a logical address to a virtual address are performed by using an anagement unit. However, the memory management operation (MMU) / software interaction further complicates the memory access operation. Furthermore, the types of operations that can be performed by a memory management system (MMU) are extremely limited. The memory management system (MMU) cannot handle interrupts, cannot queue messages,
Also, since complex addressing operations cannot be performed, all must be performed by the processor. The use of a shared memory or virtual memory system in a computer architecture having multiple parallel processors further amplifies the disadvantages described above. Not only must the hardware / software interaction be managed as described above, but also the coherency and consistency of the data in memory depending on the multiple processors attempting to access the shared memory, software and hardware Must be maintained by both. With the addition of processors, the translation of virtual addresses to logical addresses becomes more difficult. Such complexity in memory access operations necessarily reduces system capacity, and the more processors are added and the size of the system increases, the greater the reduction in capacity.

One example of a conventional system is a cache coherent, non-uniform memory access (ccNUMA: No
n-Uniform Memory Access) computer architecture. Non-uniform memory access (ccNUMA) machines use complex and expensive hardware, such as cache controllers and crossbar switches, which are individually shared, even though they are actually shared by multiple processors. A single address space phantom (virtual space) is maintained for a given CPU. Non-uniform memory access (ccNUMA) is somewhat scalable, but this scalability is achieved by adding hardware to tightly couple processors in the system. This type of system is used in computing environments where a single program image is required that requires extremely high bandwidth for shared memory I / O operations, such as the case of finite element grids in scientific computing. This is more advantageous. Further, non-uniform memory access (ccNUMA) is useless in systems where the characteristics of the processors are not similar to each other. In a non-uniform memory access (ccNUMA) architecture, each processor added must be of the same type as an existing processor. Thus, in systems where processors are optimized to perform different functions and operate differently, a non-uniform memory access (ccNUMA) architecture is not a viable solution. Finally, in traditional systems,
Only standard memory addressing schemes are used to address memory in the system.

What is needed is a method for addressing memory in a parallel computing environment that provides scalable and easy addressing and has little effect on the processing power of the system. Means.

[0028]

According to the first aspect of the present invention, there is provided a meta-address architecture for dynamic reconfiguration calculation.
A meta-addressing architecture for specifying a local memory destination for data packets for a network of dynamically reprogrammable processing machines, each implementing an interrupt and generating a meta-address including a geographic address and a local address. A plurality of addressing machines having a unique geographical address for transmitting, waiting for each message, and a local memory device each coupled to at least one of said addressing machines and responsive to a received local address A plurality of dynamically reprogrammable processing machines for storing, retrieving, and processing data from a plurality of memory devices each associated with the dynamically reprogrammable processing machine; and Previous depending on the geographic address included in the address Comprising a mutual coupling device that routes data between addressing machines each other.

According to a second aspect of the present invention, in the meta-address architecture for dynamic reconfiguration calculation according to the first aspect, at least one of the addressing machines converts a received meta-address into a geographical address and a local address. An address decoder for decoding to the dynamic reprogrammable processing machine, the local memory device and the address decoder, and responsive to receipt of an unconditional instruction from the dynamic reprogrammable processing machine. Retrieving the meta address information from the local memory, assembling a data packet according to the retrieved meta address, receiving the geographic address and the local address from the address decoder, and determining that the decoded geographic address corresponds to the relevant geographic address. Data packet to the dynamic reprogrammable processing machine Comprising a control unit for transmitting and.

According to a third aspect of the present invention, in the meta-address architecture for dynamic reconfiguration calculation according to the first aspect, the dynamic reprogrammable processing is coupled to the dynamic reprogrammable processing machine. A plurality of architectural description memory devices for storing said geographic addresses for machines.

According to a fourth aspect of the present invention, in the meta-address architecture for dynamic reconfiguration calculation according to the second aspect, the addressing machine further includes an interrupt handler coupled to an input / output device. A handler for identifying the interrupt request, a comparator for comparing the identified interrupt request with a stored list of interrupt requests to verify the validity of the interrupt request, and a stored interrupt process Interrupt logic for processing an interrupt request that has been validated according to the instruction.

According to a fifth aspect of the present invention, in the meta-address architecture for dynamic reconfiguration calculation according to the first aspect, the meta-address is 80 bits wide, the geographic address is 16 bits wide, and the local address is It is 64 bits wide.

[0033] The invention of an addressing method according to claim 6 uses a local processing machine coupled to a local addressing machine and a local memory, wherein the local addressing machine is identified by a unique geographical identification and is mutually exclusive. A method for processing instructions in a parallel processor architecture interconnected by a coupling device, the method comprising: receiving a program instruction; determining whether the received program instruction requires a remote operation; Storing remote component information in the local memory in response to the remote operation being requested; and issuing unconditional instructions to the local addressing machine to initiate the remote operation.

According to a seventh aspect of the present invention, in the addressing method according to the sixth aspect, the local addressing machine receives an unconditional instruction from the local processing machine; Retrieving remote component information from the local memory including a remote local memory address; generating a meta-address in response to the retrieved remote component information; and generating a data packet in response to the generated meta-address. And sending the data packet to the interconnection device.

The invention of an addressing method according to claim 8 is an addressing method for addressing a memory in a parallel computing environment in which a local processing unit is connected to a local memory, a local address machine and an interconnecting unit. Wherein the local address machine receives a data packet, decodes the data packet into a geographical address and a local address, compares the geographical address with an associated geographical address, Transmitting the data packet to the local processor according to the address.

According to a ninth aspect of the present invention, in the addressing method according to the eighth aspect, the step of transmitting a data packet to the local processor includes the step of storing the data packet in a queue for processing by the local processor. including.

According to a tenth aspect of the present invention, in the addressing method according to the eighth aspect, a step of receiving data from the local processor, and a step of retrieving remote operation data from the local memory in accordance with the received data.
Generating a meta-address from the retrieved data, generating a data packet according to the generated meta-address, and transmitting the data packet to the interconnection device.

In the eleventh aspect of the present invention, in the addressing method according to the tenth aspect, the step of retrieving the remote operation data includes the step of retrieving a remote geographical address and a remote local memory address.

According to a twelfth aspect of the present invention, in the addressing method according to the eleventh aspect, a step of retrieving a source geographical address from the local memory is provided.

According to a thirteenth aspect of the present invention, in the addressing method according to the twelfth aspect, an architecture description memory for storing a geographical address for the local processor coupled to each processor is provided,
Retrieve the source geographic address from this architecture description memory.

[0041] The invention of an addressing method according to claim 14 uses a local processing machine coupled to a local addressing machine and a local memory, wherein the local addressing machine is identified by a unique geographical identification, and A method for processing instructions in a parallel processor architecture interconnected by a coupling device, the local addressing machine receiving an unconditional instruction from the local processing machine; a local geographical address; Retrieving remote component information including a geographic address and a remote local memory address from the local memory; generating a metaaddress in response to the retrieved remote component information; and storing data in response to the generated metaaddress. Generating a packet; Comprising the steps of sending to the interconnecting device Tapaketto, the.

The invention of an addressing method according to claim 15 is an addressing method for addressing a memory in a parallel computing environment in which a local processing unit is connected to a local memory, a local address machine and an interconnecting unit. Receiving the data from a local processor, retrieving remote operation data from the local memory in accordance with the received data, generating a meta-address from the retrieved data; Generating a data packet according to the meta-address and transmitting the data packet to the interconnection device.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Overview> The present invention provides a set of S machines, a T machine corresponding to each S machine, and a general-purpose interconnect matrix (GPIM).
ct Matrix), a set of input / output T machines, a set of input / output devices, and a master timebase device form a system for scalable, parallel, dynamic reconfiguration calculations. Each S
The machine includes a memory, a first local time base device, and a dynamically reconfigurable processing device (DRPU).
nfigurable Process unit). The dynamic reconfiguration processor (DRPU) includes a reprogrammable logic device configured as an instruction fetch unit (IFU: Instruction Fetch Unit), a data operation unit (DOU: Data Operate unit), and an address operation unit (AOU: Address OperateUnit). ), Which are selectively reconfigured during program execution in response to selection of a reconfiguration interrupt or a reconfiguration instruction embedded in a set of program instructions, respectively. Each reconfiguration interrupt and each reconfiguration instruction is a configuration data set that specifies a dynamic reconfiguration processor (DRPU) hardware organization optimized for the implementation of a particular instruction set architecture (ISA). To illuminate.
An instruction fetch unit (IFU) instructs a reconfiguration operation, an instruction fetch / decode operation, and a memory access operation, and sends control signals to a data operation unit (DOU) and an address operation unit in order to facilitate execution of an instruction. (AOU).
The data operation unit (DOU) executes data operation, and the address operation unit (AOU) executes address operation. Each T machine has a common interface controller (CICU:
A data transfer device including a common interface and control unit, one or more interconnected input / output devices, and a second local time base device. The Generic Interconnect Matrix (GPIM) is an extensible interconnect network that facilitates parallel communication between T machines. This set of T machines and a general interconnect matrix (GPIM) facilitate parallel communication between S machines. The T machines also control the transfer of data between the S machines in the network and provide the required addressing operations. The meta-address is used to provide scalable bit addressability to each S-machine.

<Specific Embodiment> FIG. 1 is a block diagram of a preferred embodiment of a system 10 for scalable, parallel, dynamic reconfiguration calculation constructed according to the present invention. The system 10 includes at least one S machine 12, a T machine 14 corresponding to each S machine 12, a general interconnect matrix (GPIM) 16, at least one input / output T machine 18, and one or more With the above input / output device 20,
Preferably, a master time base device 22 is included. In a preferred embodiment, system 10 includes multiple S-machines 12, and thus multiple T-machines 14, multiple I / O T-machines 18, and multiple I / O devices 20.

The S machine 12, the T machine 14, and the input / output T machine 18 are connected to the master time base unit 2 respectively.
And a master timing input coupled to the second timing output. Each S-machine 12 includes an input and an output coupled to its corresponding T-machine 14. Each T machine 14 includes a routing input and a routing output coupled to a general interconnect matrix (GPIM) 16 in addition to an input and an output coupled to its corresponding S machine 12. Similarly, each input / output T machine 18 includes an input and an output coupled to an input / output device 20 and has a routing input and a routing output coupled to a general interconnect matrix (GPIM) 16. Contains.

As described in detail below, each S machine 12 is a dynamically reconfigurable computer. A general interconnect matrix (GPIM) 16 forms a point-to-point parallel interconnect that facilitates communication between T machines 14. The T machine 14 and the general interconnect matrix (GPIM) 16 form a point-to-point parallel interconnect for data transfer between the S machines 12. Similarly,
A general-purpose interconnect matrix (GPIM) 16, a set of T machines 14, and a set of input / output T machines 18 provide two points for input / output transfer between the S machine 12 and each input / output device 20. An inter-parallel interconnection means is formed. The master time base device 22 includes each S machine 12 and each T machine 14
And an oscillator for sending a master timing signal to the CPU.

In the exemplary embodiment, each S machine 12 has 64
Xilinx XC4013 (Xilinx, Inc., San Jose, Calif.) Field Programmable Gate Arra (FPGA) coupled to megabytes of random access memory (RAM)
y) is implemented. Each T machine 14 is, like the input / output T machine 18, a Xilinx XC401.
3-field programmable gate array (FPGA)
Implemented using about 50% of the reconfigured hardware resources. Generic interconnect matrix (GPIM) 1
6 is implemented as an interconnected mesh of annular bodies. The master time base unit 22 is a clock oscillator coupled to a clock distribution circuit that presents a frequency reference for the entire system, and is a U.S. patent application for "phase synchronization,
System and Method for Phase-Sy for Flexible Frequency Clocking and Messaging
nchronous, Flexible Frequency Clocking and Messagi
ng) ". T machine 14 and S machine 1
2 and the input / output T machine 18 preferably transfer information according to ANSI / IEEE standard 1596-1992 which defines an extensible coherent interface (SCI).

In the preferred embodiment, system 10 includes multiple S machines 12 functioning in parallel. The structure and function of each S machine 12 will be described in detail below with reference to FIGS. FIG. 2 is a configuration diagram of a preferred embodiment of the S machine 12. The S machine 12 includes a first local time base device 30, a dynamic reconfiguration processor (DRPU) 32 for executing a program instruction, and a memory 34. The first local time base device 30 includes a timing input forming a master timing input of the S machine. The first local time base device 30 also applies a first local timing signal or clock to a timing input of a dynamic reconfiguration processor (DRPU) 32 via a first timing signal line 40 and to a timing input of a memory 34. And a timing output unit for sending to the user. Dynamic reconfiguration processor (DR
PU) 32 is connected to a memory 34 via a memory control line 42.
A control signal output coupled to a control signal input of the memory 34, an address output coupled to an address input of the memory 34 via an address line 44, and a bidirectional data port of the memory 34 via a memory input / output line 46. And a combined bidirectional data port. In addition, the dynamic reconfiguration processor (DRPU) 32 includes a bidirectional data port coupled via an external control line 48 to a corresponding bidirectional data port of the T-machine 14. As shown in FIG. 2, the memory control line 42 is X bits, the address line 44 is M bits, and the memory input / output lines 46
Are (N × k) bits, and the external control line 48 is Y bits.

In the preferred embodiment, first local time base device 30 receives a master timing signal from master time base device 22. The first local time base device 30 generates a first local timing signal from the master timing signal and sends the first local timing signal to a dynamic reconfiguration processor (DRPU) 32 and a memory 34. In the preferred embodiment, the first local timing signal is different for each individual S machine 12. Therefore, a dynamic reconfiguration processing device (DRPU) in a predetermined S machine 12
32 and the memory 34 operate at a clock rate independent of the dynamic reconfiguration processing unit (DRPU) 32 and the memory 34 in the other S machines 12. Preferably, the first local timing signal is in phase synchronization with the master timing signal. In a preferred embodiment, the first local time base device 30 is implemented using a phase locked frequency conversion circuit including a phase locked detection circuit implemented using reconfigured hardware resources. One skilled in the art will appreciate that in another embodiment,
It will be appreciated that the first local time base device 30 can be implemented as part of a clock distribution tree.

The memory 34 is implemented as a RAM,
It is also preferable to store program instructions, program data, and configuration data for a dynamic reconfiguration processor (DRPU) 32. Memory 3 of any S machine 12
Preferably, 4 has access to other S machines 12 in system 10 via a general interconnect matrix (GPIM) 16. Further, each S machine 12 preferably has a uniform memory address space. In the preferred embodiment, the program instructions stored in memory 34 optionally include reconfiguration instructions directed to a dynamic reconfiguration processor (DRPU) 32. FIG. 3 is an exemplary program list 50 including a reconfiguration instruction. As shown in FIG. 3, the exemplary program list 50 includes a set of an outer loop portion 52, a first inner loop portion 54, a second inner loop portion 55, a third inner loop portion 56, and a fourth inner loop portion. 57 and a fifth inner loop portion 58. One skilled in the art will recognize that the term "inner loop" refers to an iterative portion of a program that performs a particular set of related operations,
It will also be readily appreciated that the term "outer loop" refers to a portion of a program that primarily performs general purpose operations and / or transfers control from one inner loop portion to another. Generally, the inner loop portions 54, 55, 56, 57, 58 of the program
Perform certain operations on potentially large data sets. For example, in an image processing application, the first inner loop portion 54 performs a color format conversion operation on image data, and the second to fifth inner loop portions 5
4, 55, 56, 57, and 58 perform a linear filtering operation, a convolution operation, a pattern search operation, and a compression operation. One skilled in the art will appreciate that the inner loop portions 55,5,
It will be appreciated that a continuous sequence of 6, 57, 58 can be considered as a software pipeline. Each outer loop portion 52 is responsible for inputting and outputting data and / or directs the transfer of data and control from the first inner loop portion 54 to the second inner loop portion 55.
Those skilled in the art will further appreciate that certain inner loop portions 54, 55,
It will be appreciated that 56, 57, 58 include one or more reconfiguration instructions. Generally, for any program, the outer loop portion 52 of the program list 50 contains various general-purpose instructions, while the inner loops 54, 56 of the program list 50 contain relatively few types of instructions used to execute a particular instruction set. It is composed of

In the exemplary program list 50, the first reconfiguration instruction appears at the start of the first inner loop portion 54, and the second reconfiguration instruction appears at the end of the first inner loop portion 54. Similarly, the third reconfiguration instruction is the second inner loop part 5
5, the fourth reconstruction instruction is at the beginning of the third inner loop part 56, the fifth reconstruction instruction is at the beginning of the fourth inner loop part 57, the sixth and seventh reconstruction instructions. Appear at the beginning and end of the fifth inner loop portion 58, respectively. Each reconfiguration instruction is for implementing a specific instruction set architecture (ISA), and an internal dynamic reconfiguration processor (DRP) optimized for it.
U) It is preferable to indicate a configuration data set that specifies the hardware organization. Instruction Set Architecture (I
SA) is a basic or core instruction set that can be used to program a computer. The instruction set architecture (ISA) defines an instruction format, an operation code, a data format, an addressing mode, an execution control flag, and a program accessible register. One skilled in the art will recognize that this corresponds to the traditional definition of an instruction set architecture (ISA). In the present invention, the dynamic reconfiguration processor (DRPU) 32 of each S machine uses a multiple instruction set architecture (I) using a unique configuration data set for each desired instruction set architecture (ISA).
A rapid runtime configuration can be implemented to implement SA) directly. That is, each instruction set architecture (ISA) is implemented with a unique internal dynamic reconfiguration processor (DRPU) hardware organization defined by a corresponding configuration data set. Therefore, in the present invention, the first to fifth inner loop portions 54, 55, 56, 57, 58
Are unique instruction set architectures (IS
A) Instruction Set Architecture (ISA)
1. Instruction Set Architecture (ISA) 2, Instruction Set Architecture (ISA) 3, Instruction Set Architecture (ISA) 4, and Instruction Set Architecture (IS)
A) Corresponds to k. Those skilled in the art will recognize that each successive instruction set architecture (ISA) need not be unique. Therefore, the instruction set architecture (ISA) k is
A) 1, an instruction set architecture (ISA) 2, an instruction set architecture (ISA) 3, an instruction set architecture (ISA) 4, or a different instruction set architecture (ISA). The set of outer loop portions 52 also corresponds to a unique instruction set architecture (ISA), ie, instruction set architecture (ISA) 0. In the preferred embodiment, during the execution of the program, the selection of successive reconfiguration instructions is made data-dependent (depending on the data). Upon selection of a particular reconfiguration instruction, the program instructions are then executed according to the corresponding instruction set architecture (ISA), with a unique Dynamic Reconfiguration Processor (DRPU) hardware configuration specified by the corresponding configuration data set. You.

In the present invention, a particular instruction set architecture (ISA) is an instruction set architecture (IS).
According to the number and type of instructions included in A), they can be classified as inner loop instruction set architecture (ISA) or outer loop instruction set architecture (ISA). An instruction set architecture (ISA) that includes several instructions and is useful for performing general-purpose operations is an outer loop instruction set architecture (ISA), whereas it includes a relatively small number of instructions and is directed to executing certain types of instructions. The current instruction set architecture (ISA) is the inner loop instruction set architecture (ISA). Since the outer loop instruction set architecture (ISA) is directed to performing general purpose operations, it is most useful when sequential execution of program instructions is desired. The execution performance of the outer loop instruction set architecture (ISA) is preferably characterized by a clock cycle for each instruction executed. In contrast, the inner loop instruction set architecture (ISA) is most useful when parallel execution of program instructions is desired, as it is directed to the execution of certain types of instructions. The execution performance of the inner loop instruction set architecture (ISA) is preferably characterized by the instructions executed per clock cycle or by the computation results obtained per clock cycle.

Those skilled in the art will recognize that the preceding description of the sequential and parallel execution of program instructions relates to the execution of program instructions within a single dynamic reconfigurable processor (DRPU) 32. There will be. Due to the presence of multiple S-machines 12 in the system 10, if each program instruction sequence is executed by a specific dynamic reconfiguration processor (DRPU) 32, the multiple program instruction sequences can be executed in parallel at any time. It will be easier. Each dynamic reconfiguration processor (DRPU) 32 is a parallel or serial hardware for implementing a particular inner loop instruction set architecture (ISA) or outer loop instruction set architecture (ISA) at a particular time. It is configured to include hardware. The internal hardware configuration of any dynamic reconfiguration processor (DRPU) 32 changes over time according to the selection of one or more reconfiguration instructions embedded in the sequence of program instructions to be executed.

In the preferred embodiment, each instruction set architecture (ISA) and its corresponding internal dynamic reconfigurable processor (DRPU) hardware organization is specific to a set of available reconfigurable hardware resources. It is designed to provide optimal computational performance for class computational problems. As mentioned above and as described in more detail below, the outer loop instruction set architecture (I
Internal dynamic reconfiguration processor (DRPU) corresponding to SA)
The hardware organization is preferably optimized for the sequential execution of program instructions. Also, the internal dynamic reconfiguration processor (DRPU) hardware organization corresponding to the inner loop instruction set architecture (ISA) is preferably optimized for parallel execution of program instructions. Model Universal External Loop Instruction Set Architecture (ISA)
Is shown in Reference Material A, and Reference Material B shows an exemplary inner loop instruction set architecture (ISA) dedicated to convolution operation.

Except for each restructuring instruction, the exemplary program list 50 of FIG.
It is preferably composed of sentences written according to a programming language. Those skilled in the art will recognize that including one or more reconfiguration instructions in a sequence of program instructions requires a compiler modified to accommodate the reconfiguration instructions. FIG. 4 is a flowchart of a prior art compilation operation performed during compilation of a series of program instructions. Here, the compilation operation of the prior art substantially corresponds to that executed by a GNU C Compiler (GCC) created by the Free Software Foundation (Cambridge, Mass.). One skilled in the art will recognize that the prior art compilation operations described below can be easily generalized to other compilers. The prior art compilation operation begins at step 500, where the compiler front end selects the next higher level statement from a series of program instructions. Next, at step 502, the compiler front end generates intermediate-level code corresponding to the selected high-level statement. This is the GNU C compiler (GC
In the case of C), the register transfer level (RTL: Register)
er Transfer Level) statement. After step 502, at step 504, the compiler front end determines whether further high-level statements need to be considered. If so, the preferred method returns to step 500.

If at step 504 the compiler front end determines that no other high level statements need to be considered, then at step 506 the compiler back end performs a conventional register allocation operation. Step 5
After 06, at step 508, the compiler backend selects the next register transfer level (RTL) statement for consideration within the current register transfer level (RTL) statement group. Next, at step 510, the compiler back end determines whether there are rules that define how the current register transfer level (RTL) statement group can be translated into a set of assembly language statements. If no such rule exists, the preferred method returns to step 508, where the current register transfer level (RT
L) Select yet another register transfer level (RTL) statement for inclusion in the statement group. If there is a rule corresponding to the current register transfer level (RTL) statement group, at step 512 the compiler back end generates a set of assembly language statements according to the rule. After step 512, the compiler backend determines whether the next register transfer level (RTL) statement needs to be considered in the context of the next register transfer level (RTL) statement group. When necessary, the preferred method returns to step 508. If not, the preferred method ends.

The present invention preferably includes a compiler for dynamic reconfiguration calculations. 5 and 6 are flowcharts of a preferred compile operation performed by a compiler for dynamic reconfiguration calculations. The preferred compilation operation begins at step 600, where the front end of the compiler for dynamic reconfiguration computation selects the next higher level statement in the sequence of program instructions. Next, in step 602, the front end of the compiler for the dynamic reconfiguration calculation determines whether the selected high-level statement is a reconfiguration instruction. If the instruction is a reconfiguration instruction, the front end of the compiler for the dynamic reconfiguration calculation generates a register transfer level (RTL) reconfiguration statement in step 604, and returns to step 600. In a preferred embodiment, the register transfer level (RTL) reconfiguration statement is a non-standard register transfer level (RTL) statement that includes an instruction set architecture (ISA) identification. If, at step 602, the selected high-level program statement is not a reconfiguration instruction, then at step 606 the front end of the compiler for dynamic reconfiguration computation uses a set of register transfer level (RTL) statements in a conventional manner. Generate Step 606
After, at step 608, the front end of the compiler for dynamic reconfiguration computation determines whether additional high-level statements need to be considered. When necessary, the preferred method returns to step 600.
Otherwise, the preferred method proceeds to step 610, where the back-end operation is started.

At step 610, the back end of the compiler for the dynamic reconfiguration calculation performs a register allocation operation. In the preferred embodiment of the present invention, each instruction set architecture (ISA) is defined such that the register architecture for each instruction set architecture (ISA) matches each other. Therefore, the register allocation operation is performed in a conventional manner. Those skilled in the art generally
It will be appreciated that it is not an absolute requirement that the register architectures per instruction set architecture (ISA) match each other. Next, at step 612, the back end of the compiler for dynamic reconfiguration computation selects the next register transfer level (RTL) statement in the register transfer level (RTL) statement group under consideration. Next, at step 614, the compiler back end for the dynamic reconfiguration calculation uses the selected register transfer level (RTL).
Determine whether the statement is a register transfer level (RTL) reconstructed statement. Selected register transfer level (RT
If the L) statement is not a register transfer level (RTL) reconstructed statement, then at step 618 the compiler back end for dynamic reconfiguration computations has rules for the register transfer level (RTL) statement group currently under consideration. Decide if you want to. If not, the preferred method returns to step 612 to select the next register transfer level (RTL) statement group to include in the currently considered register transfer level (RTL) statement group. Register transfer level (RTL) currently under consideration in step 618
If there are rules for the statement group, then in step 620 the compiler back end for dynamic reconfiguration computations will follow the rules to set the assembly corresponding to the register transfer level (RTL) statement group currently under consideration. Generate a language sentence. After step 620, the compiler backend for dynamic reconfiguration computation in step 622 needs to consider yet another register transfer level (RTL) statement in the context of the next register transfer level (RTL) statement group. Determine if there is. If so, the preferred method returns to step 612; otherwise, the preferred method ends.

At step 614, when the selected register transfer level (RTL) statement is a register transfer level (RTL) reconstructed statement, at step 616, the compiler back end for the dynamic reconfiguration calculation uses the register transfer level (RTL). RTL) Select a set of rulesets corresponding to the instruction set architecture (ISA) identification in the reconstructed statement. In the present invention, each instruction set architecture (IS
Preferably, there is a unique rule for A).
Thus, each rule set has a register transfer level (RTL) according to a specific instruction set architecture (ISA).
Provide one or more rules for converting a sentence group into an assembly language sentence. After step 616, the preferred method proceeds to step 618. A rule set corresponding to any instruction set architecture (ISA) may include rules for translating a register transfer level (RTL) reconstructed statement into a set of assembly language instructions that cause a software interrupt. preferable.
As a result of this software interrupt, a reconfiguration handler is executed, which is described in more detail below.

In the method described above, the compiler for dynamic reconfiguration computation selectively and automatically generates assembly language statements according to the multiple instruction set architecture (ISA) during the compilation operation. In other words, during compilation, the compiler for dynamic reconfiguration computation compiles a set of program instructions according to different instruction set architectures (ISAs). The compiler for the dynamic reconfiguration calculation is preferably a conventional compiler modified to perform the preferred compilation operation as described above with reference to FIGS. Those skilled in the art will recognize that the modifications required are not complex, but such modifications are not obvious from the prior art compilation and prior art reconstruction computation techniques.

FIG. 7 shows a dynamic reconfiguration processor (DRPU).
FIG. 32 is a block diagram of a preferred embodiment of the present invention. The dynamic reconfiguration processor (DRPU) 32 includes an instruction fetch unit (IFU) 6
0, a data operation unit (DOU) 62, and an address operation unit (AOU) 64. An instruction fetch unit (IFU) 60, a data operation unit (DOU) 62,
Each of the address operation units (AOU) 64 includes a timing input coupled to the first timing signal line 40. An instruction fetch unit (IFU) 60 includes a memory control output coupled to the memory control line 42, a data input coupled to the memory input / output line 46, and a bidirectional control port coupled to the external control line 48. Includes The instruction fetch unit (IFU) 60 further includes a data operation unit (DOU) 62 via a first control line 70.
A first control output coupled to the first control input of the second
Address operation unit (AOU) 64 via control line 72
And a second control output coupled to the first control input. An instruction fetch unit (IFU) 60 is connected to a second control input of a data operation unit (DOU) 62 and a second control input of an address operation unit (AOU) 64 via a third control line 74. Includes output section. Data operation unit (DOU) 62 and address operation unit (AO)
U) 64 includes a bi-directional data port coupled to the memory input / output line 46, respectively. Finally, the address operation unit (AOU) 64 is a dynamic reconfiguration processing unit (D
RPU) to form an address output.

The dynamic reconfiguration processing unit (DRPU) 32
Reconfigurable or reprogrammable logic devices, such as Xilinx XC4013 (Xilinx, Inc., San Jose, CA) or AT & T ORCA I
It is preferably implemented using a field programmable gate array (FPGA) such as C07 (AT & T Microelectronics, Allentown, PA).
The reprogrammable logic device comprises a plurality of 1) selectively reprogrammable logic blocks or configurable logic blocks (CLBs).
e Logic Blocks or Configurable Logick Blocks) and 2) Selective reprogrammable input / output blocks (IOB:
I / O Blocks), 3) a selectively reprogrammable interconnect structure, 4) a data storage resource, 5) a ternary buffer resource, and 6) a wired logic function capability. Each logical block (CL
B) preferably includes selective reconfiguration circuitry for generating logic functions, storing data, and performing signal routing. Those skilled in the art will recognize that, depending on the exact design of the reprogrammable logic device in use, the reconfigurable data storage circuit may have one or more data storage blocks (DSBs) separate from logic blocks (CLBs).
Will also be included. Here, a field programmable gate array (FPG)
The reconstructed data storage circuit in A) is a logical block (CL)
B). That is, the existence of a data storage block (DSB) is not assumed. Those skilled in the art
One or more components utilizing the logic block (CLB) based reconfigurable data storage circuit described above also utilize a data storage block (DSB) based circuit if a data storage block (DSB) is present I will admit that I can do it. Each input / output block (IOB)
Preferably includes a selective reconfiguration circuit for transferring data between a logic block (CLB) and a field programmable gate array (FPGA) output pin. The configuration data set is a logical block (CLB)
A dynamic reconfigurable processor (DRPU) hardware configuration or organization is defined by specifying the functions to be executed within: 1) within a logical block (CLB); 2) between logical blocks (CLB); ) Within the input / output block (IOB), 4) between input / output blocks (IOB), and 5) logical block (CLB) and input / output block (IO)
And B). Those skilled in the art will recognize that depending on the configuration data set, the memory control line 42 and the address line 44
And that the number of bits in each of the memory input / output lines 46 and the external control lines 48 is reconfigurable. The reconstructed data set is preferably stored on one or more S machines 34 in the system 10. Those skilled in the art will recognize a dynamic reconfiguration processor (DRP).
U) 32 is a field programmable gate array (F)
It will be appreciated that it is not limited to PGA) based implementations. For example, a dynamic reconfiguration processor (DRPU) 32
It can be implemented as a RAM-based state machine, possibly containing one or more lookup tables. Alternatively, the dynamic reconfiguration processing device (DRPU) 32
It can be implemented using a composite programmable logic device (CPLD). However, those skilled in the art will recognize that the S
It will be appreciated that a portion of machine 12 may include a non-reconfigurable dynamic reconfigurable processor (DRPU) 12.

In the preferred embodiment, the instruction fetch unit (I
The FU) 60, the data operation unit (DOU) 62, and the address operation unit (AOU) 64 are each dynamically reconfigurable. Therefore, the internal hardware configuration can be selectively changed during execution of the program. The instruction fetch unit (IFU) 60 includes an instruction fetch / decode operation, a memory access operation, and a dynamic reconfiguration processing unit (DR).
PU), and sends a control signal to a data operation unit (DOU) 62 and an address operation unit (AOU) 64 in order to easily execute the instruction. The data operation unit (DOU) 62 executes an operation related to data calculation,
The address operation unit (AOU) 64 executes an operation related to address calculation. An instruction fetch unit (IFU) 60;
The internal structures and operations of the data operation unit (DOU) 62 and the address operation unit (AOU) 64 will be described in detail below.

FIG. 8 is a block diagram of a preferred embodiment of the instruction fetch unit (IFU) 60. Instruction fetch device (IF
U) 60 is an instruction state sequencer (ISS: Instructio).
n state sequencer) 100, an architecture description memory 101, a memory access logic 102, a reconfiguration logic 104, an interrupt logic 106, a fetch controller 108, an instruction buffer 110, a decoding controller 112, and an instruction decoder. 114, an operation code storage register set 116, and a register file (RF: Register)
er File) address register set 118, constant register set 120, process control register set 12
And 2. Instruction status sequencer (ISS) 10
0 includes first and second control outputs forming first and second control outputs of the instruction fetch unit (IFU) 60, respectively, and forms timing inputs of the instruction fetch unit (IFU) 60. It includes a timing input section. The instruction state sequencer (ISS) 100 also controls the fetch controller 108 via a fetch / decode control line 130.
And an extraction / decoding control output coupled to the control input of the decoding controller 112. The instruction state sequencer (ISS) 100 further includes a bi-directional control port coupled to a first bi-directional control port of each of the memory access logic 102, the reconfiguration logic 104, and the interrupt logic 106 via a bi-directional control line 132. Contains. Instruction status sequencer (ISS) 1
00 includes an operation code input coupled to the output of operation code storage register set 116 via operation code line 142. Finally, the instruction status sequencer (I
SS) 100 includes a bi-directional control port coupled to the bi-directional control port of process control register set 122 via processing data line 144.

The memory access logic 102, the reconfiguration logic 104, and the interrupt logic 106 each include a second bidirectional control port coupled to the external control line 48. Further, the memory access logic 102
, Reconstruction logic 104, interrupt logic 106
Each include a data input coupled to a data output of the architecture description memory 101 via an implementation control line 131. Memory access logic 102
Also includes a control output forming the memory control output of the instruction fetch unit (IFU) 60, and the interrupt logic 106 further includes an output coupled to the processing data line 144. The instruction buffer 110 includes a data input forming the data input of the instruction fetch unit (IFU) 60, a control input coupled to the control output of the fetch controller 108 via a fetch control line 134, and an instruction line 136. And an output coupled to the input of the instruction decoder 114 via The instruction decoder 114 has a control input coupled to a control output of the decoding controller 112 via a decoding control line 138, and, via a decoding instruction line 140: 1) an input of an operation code storage register 116; 3) an input of a register file (RF) address register set 118; and 3) an output coupled to the input of the constant register set 120. The register file (RF) address register set 118 and the constant register set 120 are respectively provided in the third control output unit 7 of the instruction fetch unit (IFU) 60.
4 is included.

The architecture description memory 101 stores an architecture designation signal characterizing the current dynamic reconfiguration processing unit (DRPU) configuration. The architecture specification signals include: 1) a criterion for the default configuration data set; 2) a criterion for the list of allowed configuration data sets; and 3) an instruction set architecture (ISA) currently under consideration.
A reference to the configuration data set corresponding to the above, i.e., a reference to the configuration data set defining the current dynamic reconfiguration processor (DRPU) configuration; An interconnect address list identifying one or more interconnect I / O devices 304 in machine 14 (which is described in greater detail below with reference to FIG. 18); 5) interrupt latency and instruction fetch. Equipment (IFU) 60
Preferably includes a set of interrupt response signals that specify how interrupts respond to interrupts, and 6) a memory access constant that defines atomic memory address increments.
In the preferred embodiment, each configuration data set implements the architecture description memory 101 as a set of logical blocks (CLBs) configured as read-only memory (ROM). Preferably, an architecture designating signal that determines the contents of the architecture description memory 101 is included in each configuration data set. Therefore, since each configuration data set corresponds to a specific instruction set architecture (ISA), the contents of the architecture description memory 101 are stored in the instruction set architecture (ISA) currently under consideration.
Depends on A given instruction set architecture (I
For SA), program access to the contents of the architecture description memory 101 is preferably facilitated by including a memory read instruction in the instruction set architecture (ISA). This allows the program to retrieve information about the current dynamic reconfiguration processor (DRPU) configuration during program execution.

In the present invention, the reconstruction logic 104 is a state machine that controls a series of reconstruction operations, whereby the dynamic reconstruction processing unit (DR) is controlled according to the configuration data set.
PU) 32 is easily reconfigured. Preferably, the reconstruction logic 104 starts the reconstruction operation upon receiving the reconstruction signal. As will be described in greater detail below, the reconfiguration signal is a signal generated by interrupt logic 106 in response to a reconfiguration interrupt received on external control line 48, or in response to a reconfiguration instruction embedded in a program. This is a signal generated by the instruction status sequencer (ISS) 100. The reconfiguration operation results in an initial dynamic reconfiguration processor (DRPU) configuration after power on / reset using default configuration data referenced by the architecture description memory 101. Also, the reconfiguration operation provides a selective dynamic reconfiguration processor (DRPU) reconfiguration after the initial dynamic reconfiguration processor (DRPU) configuration is determined. When the reconstruction operation is completed, the reconstruction logic 104 issues a completion signal. In the preferred embodiment, the reconfiguration logic 104 is non-reconfiguration logic that controls the loading of a configuration data set into the reprogrammable logic device itself, so that the sequence of reconfiguration operations is determined by the manufacturer of the reprogrammable logic device. Therefore, reconstruction operations are known to those skilled in the art.

Each Dynamic Reconfiguration Processor (DRPU) configuration is preferably provided by a configuration data set that defines the specific hardware organization for the implementation of the corresponding instruction set architecture (ISA). In the preferred embodiment, instruction fetch unit (IFU) 60 includes the components described above, regardless of the dynamic reconfiguration processor (DRPU) configuration. At the basic level, the instruction fetch unit (I
The functionality provided by each component within the FU) 60 is based on the instruction set architecture (ISA) currently under consideration.
Has nothing to do with. However, in the preferred embodiment, the detailed structure and functionality of one or more components of instruction fetch unit (IFU) 60 will depend on the characteristics of the instruction set architecture (ISA) in which it is configured. . In the preferred embodiment, the architecture description memory 1
Preferably, the structure and functionality of 01 and the reconfiguration logic 104 are constant for each dynamic reconfiguration processor (DRPU) configuration. Instruction fetch unit (IFU) 6
The structure and functionality of the other components of O.0 and how they vary with the type of instruction set architecture (ISA) are described in detail below.

The process control register set 122 stores signals and data used by the instruction status sequencer (ISS) 100 during instruction execution. In the preferred embodiment, the process control register set 122 includes a register for storing a process control word, a register for storing an interrupt vector, and a register for storing a reference to a configuration data set. . Preferably, the process control word includes a plurality of condition flags that can be selectively set or reset based on conditions that occur during instruction execution. Further, the process control word includes a plurality of transition control signals that define one or more ways in which an interrupt can be implemented (this is described in more detail below). In the preferred embodiment, the process control register set 122 is implemented as a set of logic blocks (CLBs) configured for data storage and gating logic.

The instruction status sequencer (ISS) 100
Retrieval control unit 108, decoding control unit 112, data operation unit (DOU) 62, and address operation unit (AO
U) Preferably, the state machine transmits memory read and write signals to memory access logic 102 to control operations with 64 and facilitate instruction execution. FIG. 9 shows an instruction status sequencer (ISS) 10
FIG. 4 is a state diagram showing a set of preferred states supported by 0. After power-on or reset, or immediately after reconfiguration, the instruction state sequencer (ISS) 100 starts operation in state P. In response to the completion signal issued by the reconfiguration logic 104, the instruction status sequencer (IS
S) 100 proceeds to state S, where the instruction state sequencer (IS
S) initializes or restores the program state information when power on / reset or reconfiguration is performed. The instruction state sequencer (ISS) 100 then proceeds to state F and performs an instruction fetch operation. In an instruction fetch operation, the instruction status sequencer (ISS) 100 sends a memory read signal to the memory access logic 102, sends a fetch signal to the fetch controller 108, and increments the next instruction program address register (NIPAR) 232. An increment signal is transmitted to the address operation unit (AOU) 64 (this is shown in FIG. 1).
5 and FIG. 16 will be described in detail below). After state F, the instruction state sequencer (ISS) 100 proceeds to state D and starts the instruction decoding operation. In state D, instruction state sequencer (ISS) 100 sends a decode signal to decode control 112. In state D, instruction state sequencer (ISS) 1
00 further retrieves the operation code corresponding to the decoding instruction from the operation code storage register set 116. Instruction status sequencer (ISS) 1 based on the retrieved operation code
00 proceeds to the state E or the state M, and executes an instruction execution operation. The instruction state sequencer (ISS) 100 proceeds to state E when the instruction can be executed in one clock cycle. Otherwise, the instruction status sequencer (IS
S) 100 proceeds to state M to execute the instruction in multiple cycles. In an instruction execution operation, the instruction state sequencer (ISS) 100 facilitates execution of instructions corresponding to data operation unit (DOU) control signals, address operation unit (AOU) control signals, and / or retrieved operation codes. And a signal dedicated to the memory access logic 102 for the purpose. After state E or M, instruction state sequencer (ISS) 100 proceeds to state W. In the state W, the instruction state sequencer (ISS) 100 operates the data operation device (D
OU) control signal, an address operation unit (AOU) control signal, and / or a memory write signal for facilitating storage of the result of the instruction execution. Therefore, state W is called a write-back state. Those skilled in the art will recognize that states F, D, E, M, W include a complete instruction execution cycle. After state W, the instruction state sequencer (ISS) 100 proceeds to state Y when execution of the instruction needs to be interrupted. State Y is, for example, T machine 1
4 corresponds to an idle state as required when the memory 34 of the S machine has to be accessed. After state Y, or after state W when continuing execution of the instruction, instruction state sequencer (ISS) 100 returns to state F and begins another instruction execution cycle.

As shown in FIG. 9, the state diagram also includes the state I. This state is defined as an interrupt execution state. In the present invention, the instruction status sequencer (ISS) 10
0 receives an interrupt notification signal from the interrupt logic 106. As described in greater detail below with reference to FIG. 10, interrupt logic 106 generates a transition control signal and stores the transition control signal in a process control word in process control register set 122. The transition control signals are states F, D,
Which of E, M, W, and Y are interruptible, the level of interrupt accuracy required in each interruptible state, and the state of each interruptable state in which instruction execution should continue after state I. It is preferable to show the following state. When the instruction state sequencer (ISS) 100 receives the interrupt notification signal in a predetermined state, and the transition control signal indicates that the current state is interruptible, the instruction state sequencer (ISS) 100 Proceed to state I. Otherwise, the instruction status sequencer (IS
S) 100 proceeds as if no interrupt signal had been received until the interrupt enabled state was reached.

When the instruction state sequencer (ISS) 100 advances to state I, the instruction state sequencer (ISS) 100 sets an interrupt masking flag and retrieves the process control register set 122 to retrieve the interrupt vector.
It is preferable to access. After receiving the interrupt vector, the instruction state sequencer (ISS) 100 preferably performs a conventional subroutine jump to the interrupt handler specified by the interrupt vector to perform the current interrupt.

In the present invention, the dynamic reconfiguration processor (DRP)
U) The reconfiguration of 32 may be 1) a reconfiguration interrupt asserted on external control line 48, or
Or 2) It is started in response to execution of a reconfiguration instruction in a series of program instructions. In a preferred embodiment, a subroutine jump to a reconfiguration handler is performed whether a reconfiguration interrupt or a reconfiguration instruction is performed. The reconfiguration handler saves program state information and reconfigures configuration data set addresses and reconfiguration signals to the reconfiguration logic 104.
It is preferred to send to

When the current interrupt is not a reconfiguration interrupt, the instruction state sequencer (ISS) 100 proceeds to the next state indicated by the transition control signal if the interrupt was performed, thereby restarting the instruction execution cycle, Complete or start.

In the preferred embodiment, the set of states supported by the instruction state sequencer (ISS) 100 depends on the characteristics of the instruction set architecture (ISA) in which the dynamic reconfigurable processor (DRPU) 32 is configured. different. Thus, there is no state M for an instruction set architecture (ISA) where one or more instructions can execute in one clock cycle, as in a typical inner loop instruction set architecture (ISA). As shown, the state diagram of FIG. 9 preferably defines states supported by an instruction state sequencer (ISS) for implementing a general purpose external loop instruction set architecture (ISA). For an internal loop instruction set architecture (ISA) implementation, the instruction state sequencer (ISS) 100 includes a plurality of states F, D, E,
Preferably, W is supported in parallel. This facilitates pipeline control of instruction execution in a manner readily understood by those skilled in the art. In a preferred embodiment,
The instruction state sequencer (ISS) 100 is implemented as a logic block (CLB) based state machine that supports the states or subsets of states described above according to the instruction set architecture (ISA) under consideration.

The interrupt logic 106 preferably includes a state machine that generates a transition control signal and performs an interrupt notification operation in response to an interrupt signal received via the external control line 48. FIG. 10 illustrates the interrupt logic 106
FIG. 4 is a state diagram showing a set of preferred states supported by the system. The interrupt logic 106 starts operation in state P. State P corresponds to a power on, reset, or reconfiguration state. In response to the completion signal issued by the reconfiguration logic 104, the interrupt logic 106
To retrieve an interrupt response signal from the architecture description memory 101. The interrupt logic 106 then generates a transition control signal from the interrupt response signal and stores the transition control signal in the process control register set 122. In a preferred embodiment, interrupt logic 106 includes a logic block (CLB) based programmable logic array (PLL) for receiving interrupt response signals and generating transition control signals.
A). After state A, interrupt logic 10
6 goes to state B and waits for an interrupt signal. When the interrupt signal is received and the interrupt masking flag in the process control register set 122 is reset, the interrupt logic 1
06 proceeds to state C. In state C, the interrupt logic 10
6 determines an interrupt start point, an interrupt priority, and an interrupt handler address. When the interrupt signal is a reconfiguration interrupt, the interrupt logic 106 proceeds to state R and stores the configuration data set address in the process control register set 122. After state R, or after state C when the interrupt signal is not a reconfiguration interrupt, the interrupt logic 106 proceeds to state N and stores the interrupt handler address in the process control register set 122. The interrupt logic 106 then proceeds to state X and issues an interrupt notification signal to the instruction state sequencer (ISS) 100. After state X, interrupt logic 106 returns to state B and waits for the next interrupt signal.

In a preferred embodiment, the interrupt response signal is:
Therefore, the level of the interrupt latency specified by the transition control signal differs depending on the current instruction set architecture (ISA) in which the dynamic reconfigurable processor (DRPU) 32 is configured. For example, instruction set architectures (ISAs) for high performance real-time operation control require fast and predictable interrupt response capabilities. Accordingly, the configuration data set corresponding to such an instruction set architecture (ISA) preferably includes an interrupt response signal indicating that a low latency interrupt is required. Preferably, the corresponding transition control signal identifies a plurality of instruction state sequencer (ISS) states as interruptible. Thus, the instruction execution cycle can be interrupted by an interrupt before the instruction execution cycle is completed. Unlike an instruction set architecture (ISA) for real-time operation control, an instruction set architecture (ISA) for image convolution operation has an interrupt response capability that maximizes the number of convolution operations executed per unit time. is necessary. Preferably, the configuration data set corresponding to the instruction set architecture for image convolution (ISA) includes an interrupt response signal that specifies that a high latency interrupt is required. Preferably, the corresponding transition control signal identifies state W as interruptible. An instruction state sequencer (ISS) 100 configured to implement an instruction convolution architecture (ISA) for image convolution comprises a plurality of states F, D, E, W
In parallel, the transition control signals may each identify state W as interruptible and further specify that interrupt execution should be delayed until each parallel instruction execution cycle has completed its state W operation. preferable. This ensures that all instructions are executed before the interrupt is serviced, thereby maintaining a proper pipeline execution capability level.

Like the interrupt latency level, the level of interrupt accuracy specified by the interrupt response signal also depends on the instruction set architecture (ISA) in which the dynamic reconfigurable processor (DRPU) 32 is configured. For example, if state M is defined as being interruptible for an external loop instruction set architecture (ISA) that supports interruptible multi-cycle operations, then the interrupt response signal specifies that a precise interrupt is required. Is preferred. Thus, the transition control signal specifies that the interrupt received in state M should be treated as an accurate interrupt so that the multi-cycle operation can be successfully restarted. Another one
As one example, for an instruction set architecture (ISA) that supports defect-free pipeline arithmetic, the interrupt response signal preferably specifies that an incorrect interrupt is required. The transition control signal then specifies that an interrupt received in state W should be treated as an incorrect interrupt.

Any instruction set architecture (IS
For A), the interrupt response signal is defined and programmed by a portion of the corresponding configuration data set of the instruction set architecture (ISA). By means of a programmable interrupt response signal and the generation of a corresponding transition control signal, the present invention facilitates implementing an optimal interrupt scheme for each instruction set architecture (ISA). Those skilled in the art will appreciate that most of the prior art computer architectures do not provide flexibility in specifying interrupt capabilities, ie, enabling programmable state transitions, programmable interrupt latency, and programmable interrupt accuracy. In the preferred embodiment, the interrupt logic 106 is implemented as a logic block (CLB) based state machine that supports such states.

The fetch controller 108 instructs the instruction buffer 110 to load instructions in response to a fetch signal issued by the instruction set architecture (ISA) 100. In the preferred embodiment, the unload controller 10
8 is implemented as a conventional one-hot encoded state machine using flip-flops within a set of logic blocks (CLBs). One skilled in the art will appreciate that in other embodiments, the retrieval controller 108 may be configured to use a conventional encoding state machine or RO
It will be appreciated that it can be configured as an M-based state machine. The instruction buffer 110 temporarily stores the instruction loaded from the memory 34. For the implementation of the outer loop instruction set architecture (ISA), see instruction buffer 1
10 is a conventional R using multiple logic blocks (CLBs).
It is preferably implemented as an AM-based first-in-first-out (FIFO) buffer. For the implementation of the inner loop instruction set architecture (ISA), see the instruction buffer 11
0 indicates that a plurality of flip-flops are used in a set of input / output blocks (IOB) or input / output blocks (IOB)
And a logic block (CLB) are preferably implemented as a set of flip-flop registers using a plurality of flip-flops.

The decoding control unit 112 sends an instruction from the instruction buffer 110 to the instruction decoder 1 in accordance with the decoded signal issued by the instruction set architecture (ISA) 100.
14 to be transferred. For the inner loop instruction set architecture (ISA), the decoding controller 11
2 is preferably implemented as a ROM-based state machine that includes a logic block (CLB) based ROM coupled to a logic block (CLB) base register. For the outer loop instruction set architecture (ISA),
The decoding controller 112 is preferably implemented as a logical block (CLB) based encoding state machine. For each instruction received as input, the instruction decoder 114
The corresponding operation code, register file address, and optionally one or more constants are output in a conventional manner. Inner loop instruction set architecture (IS
For A), the instruction decoder 114 is preferably configured to decode a sequence of instructions received as input. In the preferred embodiment, the instruction decoder 114 is a logic block (CL) configured to decode each instruction in the instruction set architecture (ISA) under consideration.
B) Implemented as a base decoder.

The operation code storage register set 116 includes:
Each operation code output by the instruction decoder 114 is temporarily stored, and each operation code is stored in an instruction state sequencer (ISS).
Output to 100. When implementing an outer loop instruction set architecture (ISA) in a dynamic reconfigurable processor (DRPU) 32, the operation code storage register set 116 is preferably implemented using an optimal number of flip-flop register banks. The flip-flop register bank receives from the instruction decoder 114 a signal representing a class code or group code derived from the operation code literal bit field of the instruction that has already formed the queue through the instruction buffer 110. The flip-flop register bank stores the aforementioned class code or group code according to a decoding scheme that can minimize the complexity of the instruction state sequencer (ISS). Inner loop instruction set architecture (ISA)
In the case of the operation code storage register set 116,
An operation code indication signal directly derived from the operation code literal bit field by the instruction decoder 114 is stored. The inner loop instruction set architecture (ISA) necessarily has a small operation code literal bit field, which causes an instruction buffer 110, an instruction decoder 114, and an operation code storage register set 11 respectively.
6 minimizes implementation requirements for buffering, decoding, and operation code display for instruction sequencing. In summary, for the outer loop instruction set architecture (ISA), the operation code storage register set 116 is implemented as a small combination of flip-flop register banks characterized as a bit width equal to or part of the operation code literal size. Preferably. For the inner loop, the operation code storage register set 116 preferably has a smaller and integrated flip-flop register bank than in the outer loop instruction set architecture (ISA). The only reason why the size of the flip-flop register bank in the inner loop is small is that
This is because the number of instructions of the inner loop instruction set architecture (ISA) is extremely small compared to the outer loop instruction set architecture (ISA).

The register file (RF) address register set 118 and the constant register set 120 temporarily store each register file and each constant output by the instruction decoder 114, respectively. In the preferred embodiment, the operation code storage register set 116 and the register file (R
F) Address register set 118 and constant register set 120 are each implemented as a set of logic blocks (CLBs) configured for data storage.

The memory access logic 102 has a memory 34, a data operation unit (DOU) 62, and an address operation unit (AOU) according to the size of the atomic memory address specified in the architecture description memory 122.
64 is a memory control circuit for instructing and synchronizing data transfer with the H.64. The memory access logic 102 further directs and synchronizes the transfer of data and commands between the S machine 12 and a given T machine 14. In a preferred embodiment, memory access logic 102 supports burst memory access and is preferably implemented as a conventional RAM controller using logic blocks (CLBs). Those skilled in the art will recognize that during reconfiguration, the input and output pins of the reconfigurable logic device are ternary, and that a non-asserted logic level can be defined by a resistive stop, and thus the memory 3
Would admit not to confuse 4. In another embodiment, memory access logic 102 may be implemented external to dynamic reconfiguration processor (DRPU) 32.

FIG. 11 is a block diagram of a preferred embodiment of the data arithmetic unit 62. Data operation unit (DOU) 62
Performs operations on data according to data operation unit (DOU) control signals, register file (RF) addresses, and constants received from instruction set architecture (ISA) 100. Data operation unit (DOU) 62
Is a data operation unit (DOU) crossbar switch 15
0, storage / alignment logic 152, and data operation logic 154. Data operation unit (DOU) crossbar switch 150 and storage / alignment logic 152
And the data operation logic 154 each include a control input coupled to a first control output of an instruction fetch unit (IFU) 60 via a first control line 70. The data operation unit (DOU) crossbar switch 150 includes a bidirectional data port forming a bidirectional data port of the data operation unit (DOU), a constant input unit coupled to the third control line 74, and a first data line. A first data feedback input coupled to a data output of data operation logic 154 via a second data line 164;
And a data output coupled to the data output of the storage / alignment logic 152 via a third data line and a data output coupled to the data input of the storage / alignment logic 152 via a third data line. . The storage / alignment logic 152 includes an address input coupled to the third control line 74 in addition to its data output.
Data operation logic 154 further includes a data input coupled via a second data line 164 to an output of the storage / alignment logic.

Data operation logic 154 performs arithmetic, shift, and / or logical operations on data received at the data input in response to a data operation unit (DOU) control signal received at the control input. I do.
The storage / alignment logic 152 receives the register file (R) at its address and control inputs, respectively.
F) It includes a data storage element for temporarily storing operands, constants, and partial results related to data calculation according to an instruction of an address and a data operation unit (DOU) control. Data operation unit (DOU) crossbar switch 15
0 is the data arithmetic unit (DO) received at the control input unit.
U) Loading of data from the memory 34 in accordance with the control signal, storage / alignment of the result output by the data operation logic 154 to the logic 152 or the memory 34, and storage / alignment of the constant output by the instruction fetch unit (IFU) 60. Preferably, it is a conventional crossbar switch network that facilitates loading into logic 152. In the preferred embodiment, the detailed structure of the data operation logic 154 depends on the type of operation supported by the instruction set architecture (ISA) currently under consideration. That is, the data operation logic 15
4 is an instruction set architecture (IS
It includes circuitry for performing the arithmetic and / or logical operations specified by the data processing instructions in A). Similarly, the detailed structures of the storage / alignment logic 152 and the data operation unit (DOU) crossbar switch 150 are described in the instruction set architecture (ISA) currently under consideration.
Is determined by Instruction Set Architecture (ISA)
The detailed structures of the data operation logic 154, the storage / alignment logic 152, and the data operation unit (DOU) crossbar switch 150 according to the type of the data operation are shown in FIGS.
The details will be described below with reference to FIG.

External Loop Instruction Set Architecture (I
Regarding SA), it is preferable that the data operation unit (DOU) 62 is configured to execute a sequential operation on the data. FIG. 12 is a configuration diagram of a first exemplary embodiment of a data arithmetic unit (DOU) 61 configured for realizing a general-purpose external loop instruction set architecture (ISA). General-purpose external loop instruction set architecture (I
In SA), mathematical operations such as multiplication, addition, and subtraction, and A
Hardware configured to perform Boolean operations such as ND, OR, NOT, shift operations, and rotation operations is required. Thus, for a general-purpose outer loop instruction set architecture (ISA) implementation, the data operation logic 154 includes a conventional arithmetic logic device having a first input, a second input, a control input, and an output. ALU) / shifter 184. The storage / alignment logic 152 preferably comprises a first RAM 180 and a second RAM 182,
It includes a data input, a data output, an address selection input, and an enable input, respectively.
Data operation unit (DOU) crossbar switch 150
Preferably comprises a conventional crossbar switch network having bidirectional and unidirectional crossbar couplings and having inputs and outputs as already described with reference to FIG. Those skilled in the art will appreciate that efficient implementation of a data operation unit (DOU) crossbar switch 150 for an outer loop instruction set architecture (ISA) requires multiplexers, ternary buffers, and logic block (CLB) based logic. It will be appreciated that sub-sets of the above components coupled in any combination by direct wiring or by reconfiguration coupling means are included. For the outer loop, the data operation unit (DO
U) Crossbar switch 150 is implemented to facilitate sequential data movement in the shortest amount of time, but also provides the maximum number of single data movement crossbar couplings to support universal outer loop instructions.

The data input section of the first RAM 180 is the second R
Similar to the data input of the AM 182, it is coupled via a third data line 162 to the data output of a data operation unit (DOU) crossbar switch 150. 1st RA
An address selection input unit of the M180 and the second RAM 182 is connected to an instruction fetching device (IF
U) 60 to receive the register file address. Similarly, the first RAM 180 and the second RAM
An enable input to 182 is coupled to receive a data processing unit (DOU) control signal via a first control line 70. The data outputs of the first RAM 180 and the second RAM 182 are respectively coupled to the first input and the second input of the ALU / shifter 184, and the second data feedback input of the data operation unit (DOU) crossbar switch 150. The part is also joined. ALU /
The control input of shifter 184 is coupled to receive a data processing unit (DOU) control signal via first control line 70. Also, the output of ALU / shifter 184 is coupled to a first data feedback input of data arithmetic unit (DOU) crossbar switch 150. The connections to the remaining inputs and outputs of the data operation unit (DOU) crossbar switch 150 are the same as those described above with reference to FIG.

To facilitate the execution of data operation instructions, instruction fetch unit (IFU) 60 includes a data operation unit (DOU) control signal and a register when the instruction state sequencer (ISS) is in state E or M. File (R
F) The address signal and the constant signal are converted into a data operation device (D
OU) 61. First RAM 180 and second RAM 1
82 provides first and second register files, respectively, for temporary data storage. Individual addresses in the first RAM 180 and the second RAM 182 are selected according to the register file (RF) address received at the respective address selection input of each RAM. Similarly, the first R
The loading of the AM 180 and the second RAM 182 is performed by the write enable input of each of the first RAM 180 and the second RAM 182.
AM182 and the data arithmetic unit (DO
U) Controlled by control signals. In a preferred embodiment, at least one of the first RAM 180 and the second RAM 182 has a transfer capability to facilitate the direct transfer of data from the data operation unit (DOU) crossbar switch 150 to the ALU / shifter 184. Contains. ALU / shifter 184 operates according to the instructions of the data operation unit (DOU) control signal received at its control input.
Perform an arithmetic, logical, or shift operation based on the first operand received from first RAM 180 and / or based on the second operand received from second RAM 182. Data arithmetic unit (DO
U) The crossbar switch 150 is selectively: 1) The memory 34, the first RAM 180, and the second RAM 18
2) routing of the results from ALU / shifter 184 to first RAM 180 and second RAM 182 or to memory 34; 3) to memory 34 of data stored in first RAM 180 or second RAM 182. 4) Instruction fetch unit (IFU) 60 to first RAM 18
0 and the routing of constants to the second RAM 182. As already mentioned, the first RAM 180 or the second
When any of the RAMs 182 has a transmission capability,
A data operation unit (DOU) crossbar switch 150 also selectively routes data from the memory 34 back to the ALU / shifter 184 or directly from the output of the ALU / shifter to the ALU / shifter 184. Data operation unit (DOU) crossbar switch 150 performs a specific routing operation according to a data operation unit (DOU) control signal received at its control input. In a preferred embodiment, ALU / shifter 184 is implemented using a set of logic blocks (CLBs) for mathematical operations in the reconfigurable logic and logic function generators in the circuit. First RAM 18
0 and the second RAM 182 are preferably implemented using data storage circuits, each of which resides in a set of logic blocks (CLBs). The data operation unit (DOU) crossbar switch 150 is preferably implemented in the manner already described.

FIG. 13 is a configuration diagram of a second exemplary embodiment of the data arithmetic unit (DOU) 63 configured for realizing the inner loop instruction set architecture (ISA). Generally, the inner loop instruction set architecture (IS
A) preferably supports relatively few dedicated operations and is used to perform a common set of operations on large data sets. Thus, optimal computational performance for an inner loop instruction set architecture (ISA) is provided by hardware configured to execute operations in parallel. Therefore, the data operation unit (DOU) 6
In the second exemplary embodiment of FIG.
, Storage / alignment logic 152, and a data operation device (D
OU) crossbar switch 150 is configured to perform pipeline calculations. Data operation logic 154
Includes a pipeline functional unit 194 having a plurality of inputs, a control input, and an output. The storage / alignment logic 152 includes: 1) a set of conventional flip-flop arrays 192 (each including a data input, a data output, and a control input); and 2) a data selector 190 (control). An input section, a data input section, and a number of data output sections corresponding to the number of flip-flop arrays 192). Data operation unit (DOU) crossbar switch 150 includes a conventional crossbar switch network with dual unidirectional crossbar connections. In the second exemplary embodiment of the data operation unit (DOU) 63, the data operation unit (DOU) crossbar switch 15
0 preferably includes the input and output already described with reference to FIG. 11, except for the second data feedback input. As with the outer loop instruction set architecture (ISA), the data operation unit (DO) for the inner loop instruction set architecture (ISA)
U) Efficient implementation of crossbar switch 150 includes multiplexers, ternary buffers, and logic blocks (CL
B) It may include base logic, direct wiring, or a subset of the above components combined in a reconfigurable manner. For the inner loop instruction set architecture (ISA), the data operation unit (DOU) crossbar switch 150 is preferably implemented to maximize parallel data movement in the shortest amount of time, but with a highly pipelined inner loop instruction set architecture. (ISA)
A minimum number of single data operation crossbar connectors are also provided to support the instructions.

The data input section of the data selector 190
Data operation device (DO) via first data line 162
U) It is coupled to the data output of the crossbar switch 150. The control input of the data selector 190 is
The data selector 190 is coupled to receive a register file (RF) address via control line 74.
Are coupled to corresponding flip-flop array data inputs. Each flip-flop array 1
A control input of 92 is coupled to receive a data operation unit (DOU) control signal via a first control line 70, and each flip-flop array data output is coupled to an input of a functional unit 194. The control input of the functional unit 194 is coupled to receive a data processing unit (DOU) control signal via the first control line 70, and the output of the functional unit 194 is connected to the data processing unit (DOU) crossbar switch 150. It is coupled to a first data feedback input. The remaining input section and output section of the data operation unit (DOU) crossbar switch 150 are
This is the same as that already described with reference to FIG.

In operation, functional unit 194 performs a pipeline operation on data received at its data input in accordance with a data operation unit (DOU) control signal received at its control input. One skilled in the art will recognize that the functional unit 194 is a multiply / accumulator, a threshold determiner, an image rotator, an edge enhancer, or any other suitable for performing pipeline operations on partitioned data. It will be appreciated that this is a type of functional unit. Data selector 19
0 is the register file (R
F) Data is routed (determined) from the output of the data operation unit (DOU) crossbar switch 150 to a predetermined flip-flop array 192 according to the address. Each flip-flop array 192 is sequentially coupled to spatially and temporally align data with the data content of another flip-flop array 192, as indicated by a control signal received at its control input. Preferably, it includes a data latch. The data operation unit (DOU) crossbar switch 150 selectively: 1) routes the data from the memory 34 to the data selector 190; 2) passes the result from the multiplication / accumulation unit 194 to the data selector 1
3) Route constants from instruction fetch unit (IFU) 60 to data selector 190. One skilled in the art will recognize the inner loop instruction set architecture (IS
It will be appreciated that A) contains a set of "built-in" constants. In such an internal loop instruction set architecture (ISA) implementation, the storage / alignment logic 154 has a logic block (CLB) based ROM with built-in constants.
, So that the storage / alignment logic 152 from the instruction fetch unit (IFU) 60 via the data operation unit (DOU) crossbar switch 150
This eliminates the need to route constants to In the preferred embodiment, the functional units 194 are preferably implemented using logic function generators and circuits for mathematical operations in a set of logic blocks (CLBs). Each flip-flop array 192 is a set of logic blocks (CLB).
It is preferably implemented using flip-flops within. The data selector 190 is a set of logical blocks (CL
It is preferably implemented using the logic function generator and the data selection circuit in B). Finally, the data operation device (DO
U) The crossbar switch 150 is preferably implemented in the manner already described for the inner loop.

FIG. 14 shows an address operation unit (AOU) 6
FIG. 4 is a configuration diagram of a fourth preferred embodiment. The address operation unit (AOU) 64 performs an operation on the address according to the address operation unit (AOU) control signal, the register file (RF) address, and the constant received from the instruction fetch unit (IFU) 60. Address arithmetic unit (AO
U) 64 is an address operation unit (AOU) crossbar switch 200, storage / counting logic 202, address operation logic 204, and address multiplexer 20.
6 is included. An address operation unit (AOU) crossbar switch 200, a storage / counting logic 202,
Address operation logic 204 and address multiplexer 206 each include a control input coupled to a second control output of instruction fetch unit (IFU) 60 via second control line 72. Address arithmetic unit (AO
U) The crossbar switch 200 includes a bidirectional data port forming a bidirectional data port of an address operation unit (AOU) and an address feedback input coupled to an address output of the address operation logic 204 via a first address line 210. And a constant input coupled to the third control line 74 and an address output coupled to the address input of the storage / counting logic 202 via a second address line 212. The storage / counting logic 202, in addition to its address and control inputs,
A register file (R) coupled to the third control line 74
F) Includes an address input and an address output coupled to the address input of address arithmetic logic 204 via third address line 214. Address multiplexer 206 has a first input coupled to first address line 210, a second input coupled to third address line 214, and an output forming an address output of address operation unit (AOU) 64. Department and contains.

Address operation logic 204 performs an arithmetic operation on the address received at the address input according to the instruction of the address operation unit (AOU) control signal received at the control input. Storage / counting logic 20
2 temporarily stores the address and the address calculation result.
Address operation unit (AOU) crossbar switch 200
Is the address arithmetic unit (AO) received at the control input unit.
U) Loading of the address from the memory 34, transfer of the result output of the address operation logic 204 to the storage / counting logic 202 or the memory 34, and storage / counting of the constant output by the instruction fetch unit (IFU) 60 according to the control signal. Loading into the logic 202 is facilitated. The address multiplexer 206 transfers the address received from the storage / counting logic 202 or the address multiplexer 206 to the address output of the address arithmetic unit (AOU) 64 in accordance with the instruction of the address arithmetic unit (AOU) control signal received at its control input. Selectively output. In the preferred embodiment, the address arithmetic unit (AO
U) The detailed structure of the crossbar switch 200, the storage / counting logic 202, and the address operation logic 204 will be described below with reference to FIGS. ) Is determined by the type.

FIG. 15 is a configuration diagram of a first exemplary embodiment of an address arithmetic unit (AOU) 65 configured for realizing a general-purpose external loop instruction set architecture (ISA). General-purpose external loop instruction set architecture (I
In SA), hardware for executing operations such as addition, subtraction, increment, and decrement on the contents of the program counter and the address stored in the storage / counting logic 202 is required. In a first exemplary embodiment of the address operation unit (AOU) 65, the address operation logic 204 includes a next instruction program address register (NIP) having an input, an output, and a control input.
AR) Arithmetic unit 23 having 232, first input unit, second input unit, third input unit, control input unit, and output unit
4, a multiplexer 230 having a first input, a second input, a control input, and an output. The storage / counting logic 202 includes a third RAM 220 and a fourth RAM 22 each having an input, an output, an address selection input, and an enable input.
And preferably 2. Address multiplexer 206 preferably includes a multiplexer having a first input, a second input, a third input, a control input, and an output. Address arithmetic unit (AO
U) The crossbar switch 200 preferably includes a conventional crossbar switch network having a dual unidirectional crossbar coupling and the inputs and outputs previously described with reference to FIG. Address arithmetic unit (AO
U) For efficient production of the crossbar switch 200,
A multiplexer, a ternary buffer, and a logic block (C
LB) Includes a subset of such components coupled by base logic, direct wiring, or reconfiguration coupling. For the external loop instruction set architecture (ISA), the address operation unit (AOU) crossbar switch 200 is preferably implemented to maximize sequential data movement in the shortest time, but supports general external loop address operation instructions. It also provides a maximum number of unique address move crossbar joiners.

The input section of the third RAM 220 and the fourth RAM 2
22 are input to the second address line 21 respectively.
2 is coupled to the output of an address operation unit (AOU) crossbar switch 200. Third RAM 220
And an address selection input of the fourth RAM 222 are coupled to receive a register file (RF) address from the instruction fetch unit (IFU) 60 via a third control line 74. The enable inputs of the third RAM 220 and the fourth RAM 222 are coupled to receive an address arithmetic unit (AOU) control signal via a second control line 72. The output of the third RAM 220 is the multiplexer 23
0, a first input of the arithmetic unit 234, and a first input of the address multiplexer 206. Similarly, the output of the fourth RAM 222 is connected to the second input of the multiplexer 230 and the second input of the arithmetic unit 234.
An input and a second input of the address multiplexer 206 are coupled. Multiplexer 230 and NIP
The control inputs of AR 232 and arithmetic unit 234 are each coupled to a second control line 72. Arithmetic unit 2
34 form the output of the address arithmetic logic 204, and therefore the address arithmetic unit (AO)
U) is coupled to the address feedback input of crossbar switch 200 and to a third input of address multiplexer 206; Address operation unit (AOU) crossbar switch 200 and address multiplexer 206
The remaining connection parts to the input and output parts are the same as those already described with reference to FIG.

To facilitate the execution of the address operation instruction, the instruction fetch unit (IFU) 60 controls the address operation unit (AOU) control signal and the register file (IU) when the instruction state sequencer (ISS) is in the state E or M. An RF) address and a constant are issued to an address arithmetic unit (AOU) 64. The third RAM 220 and the fourth RAM 222 provide first and second register files for temporary storage of addresses, respectively. Third RAM 220 and Fourth RAM
Each storage location in 222 is selected according to the register file (RF) address received at the address selection input of each RAM. The loading of the third RAM 220 and the fourth RAM 222 is performed by the write enable input of the third RAM 220 and the fourth RAM 222.
The RAM 220 and the fourth RAM 222 are controlled by the control of an address arithmetic unit (AOU) received respectively. Multiplexer 230 responds to the instruction of the address operation unit (AOU) control signal received at its control input by a third
The address output from the RAM 220 and the fourth RAM 222 is selectively routed to the NIPAR 232. NI
The PAR 232 loads the address received from the output of the multiplexer 230 and increments its content in response to an address operation unit (AOU) control signal received at its control input. In a preferred embodiment, NIPA
R232 stores the address of the next program instruction to be executed. The arithmetic unit 234 adds, subtracts, and / or subtracts the address received from the third RAM 220 and the fourth RAM 222 and / or the content of the NIPAR 232.
Perform arithmetic operations including increment and decrement. The address operation unit (AOU) crossbar switch 200 may selectively: 1) transfer the address from the memory 34 to the third RAM 220 and the fourth RAM 220;
2) route the result of the address calculation output by the arithmetic unit 234 to the memory 34 or the third RAM 220 and the fourth RAM 222; Address operation unit (AOU) crossbar switch 200
Is the address arithmetic unit (AOU) received at the control input unit
Perform a specific routing operation according to the control signal.
The address multiplexer 206 outputs an address from the third RAM 220 according to the instruction of the address arithmetic unit (AOU) control received at the control input unit, and outputs the address from the fourth RAM 2.
22 and the result of the address calculation output by the arithmetic unit 234 are stored in the address arithmetic unit (AO
U) to selectively route to the address output.

In the preferred embodiment, the third RAM 220 and the fourth RAM 222 each have a set of logical blocks (C
It is implemented using the data storage circuit existing in LB). Multiplexer 230 and address multiplexer 2
06 is preferably implemented using a data selection circuit that resides in each set of logic blocks (CLBs), and NIPAR 232 is implemented in a set of logic blocks (CLBs).
It is preferably implemented using the data storage circuit present in B). Arithmetic unit 234 is preferably implemented using logic function generators and circuits for mathematical operations within a set of logic blocks (CLBs). Finally, the address operation unit (AOU) crossbar switch 200 is preferably implemented in the manner already described.

FIG. 16 is a block diagram of a second exemplary embodiment of the address arithmetic unit (AOU) 66 configured for implementing the inner loop instruction set architecture (ISA). The inner loop instruction set architecture (ISA) requires hardware to perform a very limited number of address operations and to maintain at least one source address pointer and a corresponding number of destination address pointers. Requires hardware. Types of internal loop processing that require a very limited number of address operations or one address operation include block operations, raster operations, or serpentine operations on image data,
It includes a bit reversal operation, an operation on circular buffer data, and a variable-length data parsing operation. Here, one address operation, that is, an increment operation is considered. Those skilled in the art will recognize that hardware that performs an increment operation can inherently perform a decrement operation,
It will be appreciated that this provides yet another addressing capability. Address operation unit (AOU) 66
In a second exemplary embodiment of the storage / counting logic 202,
At least one source address register 252 having an input, an output, and a control input; at least one destination address register 254 having an input, an output, and a control input; And a data selector 250 having a control input and a number of outputs equal to the total number of existing source address registers 252 and destination address registers 254. Here, one source address register 252 and one destination address register 254 are considered. Therefore, the data selector 250 includes a first output unit and a second output unit. The address operation logic 204 includes a NIPAR 232 having an input, an output, and a control input, and a multiplexer 260 having an equal number of inputs as data selectors, a control input, and an output. . Here, the multiplexer 260 includes a first input unit and a second input unit. Address multiplexer 206 preferably includes a multiplexer having one more input than the data selector output, a control input, and an output. Therefore, here, the address multiplexer 20 is used.
6 includes a first input unit, a second input unit, and a third input unit. An address operation unit (AOU) crossbar switch 200 includes a conventional crossbar switch network having a bidirectional and a unidirectional crossbar coupling unit, and having an input unit and an output unit already described with reference to FIG. It is preferable to include. Address arithmetic unit (AO
U) For efficient production of the crossbar switch 200,
A multiplexer, a ternary buffer, and a logic block (C
LB) Includes a subset of such components coupled by base logic, direct wiring, or reconfiguration coupling. For the inner loop instruction set architecture (ISA), the address arithmetic unit (AOU) crossbar switch 200 is preferably implemented to maximize parallel address movement in the shortest amount of time, but supports inner loop opcodes. To this end, it also provides a maximum number of unique address move crossbar joiners.

The input of the data selector 250 is coupled to the output of an address operation unit (AOU) crossbar switch 200. The first and second output units of the data selector 250 are connected to the source address register 252, respectively.
And the input of the destination address register 254. The control inputs of the source address register 252 and the destination address register 254 are coupled via a second control line 72 to receive an address arithmetic unit (AOU) control signal. Source address register 2
The output of 52 is coupled to a first input of multiplexer 260 and a first input of address multiplexer 206. Similarly, the output of destination address register 254 is coupled to a second input of multiplexer 260 and a second input of address multiplexer 206.
The input of NIPAR 232 is coupled to the output of multiplexer 260, and the control input of NIPAR 232 is connected via a second control line 72 to an address arithmetic unit (AO).
U) NIPA coupled to receive control signals
The output of R232 is coupled to an address feedback input of an address operation unit (AOU) crossbar switch 200 and to a third input of an address multiplexer 206. The connection to the remaining inputs and outputs of the address operation unit (AOU) crossbar switch 200 is the same as that described above with reference to FIG.

In the operation, the data selector 250 receives the address received from the address arithmetic unit (AOU) crossbar switch in accordance with the register file (RF) address received at its control input section, and outputs the address to the source address register 2.
52 or to the destination address register 254. Source address register 252 loads an address present at its input in response to an address operation unit (AOU) control signal present at its control input. Destination address register 254 loads the address present at its input in a similar manner. Multiplexer 260
Is the address arithmetic unit (AO) received at the control input unit.
U) Route the address received from source address register 252 or destination address register 254 to the input of NIPAR 232 according to the control signal. NI
PAR 232 loads the address present at its input in response to an address operation unit (AOU) control signal received at its control input and increments or decrements its contents. Address arithmetic unit (AO
U) Crossbar switch 200 selectively: 1) routes the address from memory 34 to data selector 250, and 2) routes the contents of NIPAR 232 to memory 34 or data selector 250. Address operation unit (AOU) crossbar switch 200
Is the address arithmetic unit (AO) received at the control input unit.
U) Perform a specific routing operation according to the control signal. The address multiplexer 206 transfers the contents of the source address register 252, the destination address register 254, or the NIPAR 232 to the address output unit of the address arithmetic unit (AOU) according to the instruction of the address arithmetic unit (AOU) control signal received at the control input unit. Selectively route.

In the preferred embodiment, source address register 252 and destination address register 254 are each implemented using data storage circuits residing in a set of logic blocks (CLBs). NIPAR232 is 1
It is preferably implemented using increment / decrement logic and flip-flops within a set of logic blocks (CLBs). It is preferable that the data selector 250, the multiplexer 230, and the address multiplexer 206 are each implemented by using a data selection circuit existing in a set of logic blocks (CLB). Finally, the address operation unit (AOU) crossbar switch 200 is preferably implemented in the manner already described for the inner loop instruction set architecture (ISA). Those skilled in the art will recognize that in some applications, using an instruction set architecture (ISA) that relies on an inner loop address arithmetic unit (AOU) configuration with an outer loop data arithmetic unit (DOU) configuration,
Or vice versa (Internal loop address arithmetic unit (AOU)
It will be appreciated that an outer loop data processing unit (DOU) configuration with a configuration is advantageous. For example, Associative String Search Instruction Set Architecture (ISA)
It would be advantageous to utilize an inner loop data arithmetic unit (DOU) configuration with an outer loop address arithmetic unit (AOU) configuration. As another example, an instruction set architecture (ISA) for performing histogram operations is:
It would be advantageous to utilize an outer loop data arithmetic unit (DOU) configuration with an inner loop address arithmetic unit (AOU) configuration.

A limited number of reconfigurable hardware resources must be allocated between the components of the dynamic reconfiguration processor (DRPU) 32. Since the number of reconfigurable hardware resources is limited, for example, when these are assigned to the instruction fetch unit (IFU) 60, the data arithmetic unit (DO)
U) 62 and the maximum computational performance level achievable by the address operation unit (AOU) 64. An instruction fetch unit (IFU) 6
The method of allocating between 0, data operation unit (DOU) 62, and address operation unit (AOU) 64 depends on the type of instruction set architecture (ISA) implemented at any given moment. Instruction Set Architecture (IS
As A) becomes more complex, more and more reconfigurable hardware resources must be allocated to the instruction fetch unit (IFU) 60 in order to facilitate increasingly complex decoding and control operations. DOU) 62
Reconfigurable hardware resources that can be used between the AOU 64 and the address arithmetic unit (AOU) 64 are reduced. Therefore, the maximum calculation performance achievable by the data operation unit (DOU) 62 and the address operation unit (AOU) 64 is:
Decreases with increasing instruction set architecture (ISA) complexity. In general, the outer loop instruction set architecture (ISA) contains more instructions than the inner loop instruction set architecture (ISA), and therefore its implementation is significantly more complex in decoding and control circuits. For example, an outer loop instruction set architecture (ISA) defining a general purpose 64-bit processor would include more instructions than an inner loop instruction set architecture (ISA) used only for data compression.

FIG. 17A shows an instruction fetch unit (I) for an outer loop instruction set architecture (ISA).
FIG. 3 is a diagram showing an exemplary assignment of reconfigurable hardware resources among an FU) 60, a data arithmetic unit (DOU) 62, and an address arithmetic unit (AOU) 64. In an exemplary allocation of reconfigurable hardware resources for an outer loop instruction set architecture (ISA), an instruction fetch unit (IFU) 60, a data operation unit (DOU) 62,
Each address operation unit (AOU) 64 is allocated approximately one third of the available reconfigurable hardware resources. When the dynamic reconfiguration processor (DRPU) 32 is to be reconfigured to implement the inner loop instruction set architecture (ISA), the number of instructions and types of address instructions supported by the inner loop instruction set architecture (ISA) Instruction fetch device (IF
U) 60 and the address arithmetic unit (AOU) 64 require less reconfigurable hardware resources. FIG. 17B shows an instruction fetch unit (IFU) 6 for the inner loop instruction set architecture (ISA).
FIG. 4 is a diagram showing an exemplary assignment of reconfigurable hardware resources among a data operation unit (DOU) 62 and an address operation unit (AOU) 64. In an exemplary allocation of reconfigurable hardware resources for an inner loop instruction set architecture (ISA), an instruction fetch unit (IF
U) 60 is about 5-10% of reconfigured hardware resources
And the address operation unit (AOU) 64 is implemented using about 10 to 25% of the reconfigurable hardware resources. Therefore, about 70-80% of the reconfigured hardware resources are available for implementing the data processing unit (DOU) 62. This is because the data processing unit (D) associated with the inner loop instruction set architecture (ISA)
OU) 62 has a data processing unit (DO) associated with an inner loop instruction set architecture (ISA).
U) It can be more complex than the internal structure of 62, which means that it can exhibit much higher performance.

Those skilled in the art will recognize that in another embodiment, the dynamic reconfigurable processor (DRPU) 32 may exclude a data arithmetic unit (DOU) 62 or an address arithmetic unit (AOU) 64. For example, in another embodiment, the dynamic reconfiguration processor (DRPU) 32 includes an address arithmetic unit (AO).
U) 64 may not be included. In that case, the data operation unit (DOU) 62 performs an operation on both data and addresses. Regardless of the particular dynamic reconfiguration processor (DRPU) embodiment discussed (above), a finite number of reconfiguration hardware to implement each component of the dynamic reconfiguration processor (DRPU) 32 Resources must be allocated. Reconfigured hardware resources are
The instruction set architecture (IS) currently under consideration for the entire space of available reconfigurable hardware resources
Preferably, the allocation is such that optimal or near-optimal performance for A) is achieved.

Those skilled in the art will recognize that the instruction fetch unit (IFU) 60
It will be appreciated that the detailed structure of each component of the data operation unit (DOU) 62 and the address operation unit (AOU) 64 is not limited to the embodiment described above.
For a given instruction set architecture (ISA),
The corresponding configuration data set contains the instruction fetch device (IF
U) 60, data operation unit (DOU) 62, and internal structure of each component in address operation unit (AOU) 64 to maximize computational performance for available reconfigurable hardware resources. Preferably, it is determined.

FIG. 18 is a block diagram of a preferred embodiment of the T machine. The T machine 14 includes a second local time base device 300 and a shared interface control device (CIC).
U: Common Interface and Control Unit) 302,
A set of interconnected input / output devices 304. Second
The local time base device 300 includes a timing input forming the master timing input of the T machine. Common interface control unit (CICU) 302
Is coupled via a second timing signal line 310 to a timing output of the second local time base device 300, an address output coupled to the address line 44, and coupled to the memory input / output line 46. A first bidirectional control port, a bidirectional control port coupled to external control line 48, and a second bidirectional control port coupled to a bidirectional data port of each existing interconnected input / output device 304 via message transfer line 312. Data port. Each interconnect input / output device 304 has an input coupled to a general interconnect matrix (GPIM) 16 via a message input line 314, and a general interconnect matrix (G) via a message output line 316.
(PIM) 16.

The second local time base device 300 in the T machine 14 receives a master timing signal from the master time base device 22 and generates a second local timing signal. Second local time base device 300
Sends a second local timing signal to a common interface controller (CICU) 302, thereby providing a timing reference for the T-machine 14 in which it resides. Preferably, the second local timing signal is in phase synchronization with the master timing signal. System 1
0, the second local time base device 3 of each T machine
00 preferably operate at the same frequency. Those skilled in the art will recognize that in another embodiment, one or more second local time base devices 300 operate at different frequencies. Second local time base device 3
00 is preferably implemented using a conventional phase locked frequency conversion circuit including a logic block (CLB) based phase lock detection circuit. Those skilled in the art will recognize that in another embodiment, the second local time base device 300 can be implemented as part of a clock distribution tree.

Common interface control unit (CICU)
302 directs the transfer of messages between its corresponding S-machine 12 and a particular interconnected I / O device 304;
This message contains the command and possibly data. In a preferred embodiment, the designated interconnect I / O device 304 may reside in any T-machine 14 or I / O T-machine 18 that is internal or external to system 10. In a preferred embodiment, each interconnection I / O device 304 is preferably assigned an interconnection address that uniquely identifies the interconnection I / O device 304.
The interconnection address for the interconnection I / O device 304 in a given T machine is stored in the architecture description memory 101 of the corresponding S machine.

Common interface control unit (CICU)
302 receives data and commands from its corresponding S-machine 12 via memory input / output lines 46 and external control signal lines 48, respectively. Each command received
It preferably includes a target interconnect address and a command code that specifies the particular type of operation to be performed. In a preferred embodiment, the types of operations uniquely identified by the command code include: 1) a data read operation, 2) a data write operation, and 3) an interrupt signal transfer including a reconfigured interrupt transfer. I have. The destination interconnect address identifies the destination interconnect I / O device 304 to which data and commands should be transferred. Common interface control unit (CICU) 30
2, preferably transfers each command and associated data as a set of packet-based messages in a conventional manner, each message including a target interconnect address and a command code.

Common interface control unit (CICU)
302 receives a message from each interconnected I / O device 304 coupled to the message transfer line 312, in addition to receiving data and commands from its corresponding S-machine 12. In a preferred embodiment, the common interface controller (CICU) 302 converts the associated message group into a single command and data sequence. When a command is directed to a dynamic reconfiguration processor (DRPU) 32 in its corresponding S-machine 12, the common interface controller (CICU) 302 issues the command via the external control signal line. When a command is directed to the memory 34 in the corresponding S machine 12, the common interface controller (CICU) 30
2 issues an appropriate memory control signal via an external control signal line 48 and a memory address signal via a memory address line 44. Data is transferred via the memory input / output line 46. In a preferred embodiment, the common interface controller (CICU) 302
Includes logic block (CLB) based circuitry for performing operations similar to those performed by conventional SCI switching devices as defined in IEEE Standard 1596-1992.

Each mutual coupling input / output device 304 receives a message from the common interface control device (CICU) 302 and receives the message from the common interface control device (CICU) 3.
The message is transferred to another interconnection input / output device 304 via the general interconnection matrix (GPIM) 16 in accordance with the instruction of the control signal received from the communication device 02. In a preferred embodiment, the interconnected input / output device 304 comprises an ANSI /
It is based on the SCI node defined in IEEE Standard 1596-1992. FIG.
FIG. 4 is a configuration diagram of a preferred embodiment of the present invention. The interconnection input / output device 304 includes an address decoder 320 and an input FIFO.
Buffer 322 and bypass FIFO buffer 324
, Output FIFO buffer 326 and multiplexer 3
28. Address decoder 320 includes an input forming an input of the interconnected input / output device, and an input FIFO.
It includes a first output coupled to the O-buffer 322 and a second output coupled to the bypass FIFO buffer 324. The input FIFO buffer 322 includes an output coupled to a message transfer line 312 for transferring a message to a common interface controller (CICU) 302. The output FIFO buffer 326
It includes an input coupled to the message transfer line 312 for receiving a message from the common interface controller (CICU) 302, and an output coupled to a first input of the multiplexer 328. Bypass FIF
O-buffer 324 includes an output coupled to a second input of multiplexer 328. Finally, multiplexer 328 includes a control input coupled to message transfer line 312 and an output forming the output of the interconnected input / output device.

The interconnection input / output device 304 receives a message at the input of the address decoder 320. Address decoder 320 determines whether the target interconnect address specified in the received message is the same as the interconnect address of interconnect I / O device 304 in which it resides. If they are the same, the address decoder 320 routes this message to the input FIFO buffer 322. Otherwise, the address decoder 320 routes the message to the bypass FIFO buffer 324. In the preferred embodiment, the address decoder 320 comprises a decoder implemented using input / output blocks (IOB) and logic blocks (CLB) and a data selector.

The input FIFO buffer 322 transfers a message received at its input to the message transfer line 312.
Is a conventional FIFO buffer. Bypass FIFO buffer 324 and output FIFO buffer 326
Is a conventional FIFO buffer that forwards the message received at its input to the multiplexer 328. Multiplexer 328 controls the bypass FIFO buffer 3 according to the control signal received at its control input.
A conventional multiplexer that routes messages received from 24 or output FIFO buffer 326 to a general interconnect matrix (GPIM) 16. In the preferred embodiment, the input
O buffer 322 and bypass FIFO buffer 324
And the output FIFO buffer 326 are each implemented using a set of logic blocks (CLBs). The multiplexer 328 is preferably implemented using a set of logic blocks (CLB) and input / output blocks (IOB).

FIG. 20 is a block diagram of a preferred embodiment of the input / output T machine 18. As shown in FIG. The input / output T machine 18 includes a third local time base device 360, a common custom interface control device 362, and an interconnected input / output device 304
And Third local time base device 360
Include a timing input forming the master timing input of the input / output T machine. The interconnect input / output device 304 has an input coupled to the general interconnect matrix (GPIM) 16 via a message input line 314 and an output coupled to the general interconnect matrix (GPIM) 16 via a message output line 316. Department and contains. Common custom interface controller 36
2 is a timing input coupled to a timing output of a third local time base device 360 via a third timing signal line 370;
A first bidirectional data port coupled to the I / O device 20 and a set of couplings to the input / output device 20. In a preferred embodiment, a set of couplings to input / output device 20 is coupled to a second bidirectional data port coupled to the bidirectional data port of input / output device 20 and to an address input of input / output device 20. And a bidirectional control port coupled to the bidirectional control port of the input / output device 20. Those skilled in the art will readily recognize that the type of I / O device 20 to which the common custom interface controller 362 is coupled will determine the coupling to the I / O device 20.

The third local time base device 360
A master timing signal is received from the master time base device 22, and a third local timing signal is generated. The third local time base device 360 transmits the third local timing signal to the common custom interface control device 3.
62 to provide a timing reference to the I / O T-machine in which it is located. In a preferred embodiment, the third local timing signal is phase synchronized with the master timing signal. The third local time base device 360 of each I / O T-machine preferably operates at the same frequency. In another embodiment, one or more third local time base devices 360 can operate at different frequencies. The third local time base device 360
Preferably, it is implemented using a conventional phase lock frequency conversion circuit including a logic block (CLB) based phase lock detection circuit. In the same manner as the first local time base device 30 and the second local time base device 300,
In another embodiment, the third local time base device 360 can be implemented as part of a clock distribution tree.

The structure and function of the interconnected input / output device 304 in the input / output T machine 18 are preferably the same as those already described for the T machine 14. The interconnected I / O devices 304 in the I / O T-machine 18 are assigned unique interconnect addresses in a manner similar to each interconnected I / O device 304 in any T-machine 14.

The common custom interface control device 36
2 directs the transfer of a message between the I / O device 20 coupled to it and the interconnected I / O device 304, the message including a command and possibly data. The common custom interface controller 362 receives data and commands from its corresponding input / output device 20. Each command received from input / output device 20 preferably includes a target interconnect address and a command code specifying a particular type of operation to be performed. In the preferred embodiment, the types of operations uniquely identified by the command code include: 1) data request, 2) data transfer confirmation, and 3) interrupt signal transfer. The destination interconnect address identifies the destination interconnect I / O device 304 in the system 10 to which data and commands are to be transferred. The common custom interface controller 362 preferably forwards each command and associated data as a set of packet-based messages in a conventional manner, each message including a target interconnect address and a command code.

The common custom interface control device 36
2 receives a message from its associated I / O device 20 in addition to receiving data and commands from its corresponding I / O device 20. In a preferred embodiment, the common custom interface controller 362 converts the associated message group into a single command and data sequence according to the communication protocol supported by its corresponding input / output device 20. In the preferred embodiment, the common custom interface controller 362 is based on a logic block (CLB) for performing operations similar to those performed by conventional SCI switching devices as defined in ANSI / IEEE Standard 1596-1992. A logic block (CLB) based input / output device controller is coupled to the circuit.

General Interconnection Matrix (GPIM) 1
6 is a conventional interconnection mesh that facilitates point-to-point parallel message routing between interconnection input / output devices 304. In a preferred embodiment, the general interconnect matrix (GPIM) 16 is a wire-based k-ary n-cube static interconnect network. FIG. 21 shows a general interconnect matrix (GPI
M) is a block diagram of an exemplary embodiment of 16; In FIG. 21, a general interconnect matrix (GPIM) 16 includes a plurality of first communication channels 380 and a plurality of second communication channels 38.
2 is a k-ary 2-cube ring interconnected mesh comprising Each first communication channel 380 includes a plurality of node connections 384, and each second communication channel 382 as well. Each interconnected input / output device 304 of system 10 includes a message input line 314,
Preferably, the message output line 316 is coupled to a general interconnect matrix (GPIM) 16 to connect to the continuous node connection 384 within a predetermined first communication channel 380 and a second communication channel 382. In a preferred embodiment, each T machine 14 has an interconnected I / O device 304 coupled to the first communication channel 380 and an interconnected I / O device 304 coupled to the second communication channel 382 in the manner described above. Contains. T machine 1
4 common interface control unit (CICU) 302
Preferably facilitates routing information between its interconnected I / O devices 304 coupled to the first communication channel 380 and its interconnected I / O devices 304 coupled to the second communication channel 382. . Therefore,
The first communication channel 3 denoted by 380c in FIG.
Interconnect input / output device 304 coupled to 80;
For a T-machine 14 that includes an interconnected input / output device 304 coupled to a second communication channel 382 labeled c, the T-machine's common interface controller (CICU) 302 includes a first communication channel 380c and a Information routing to and from the second communication channel 382c can be easily performed.

Therefore, the universal interconnection matrix (G
The PIM 16 facilitates routing of multiple messages between interconnected I / O devices 304 arranged in parallel. The two-dimensional general interconnection matrix (GP
IM) 16, each T-machine 14 has one interconnected I / O device 304 for the first communication channel 380.
, And one interconnected input / output device 304 for the second communication channel 382. Those skilled in the art will recognize that in embodiments where the dimensions of the general interconnect matrix (GPIM) 16 are greater than two dimensions, it is preferred that the T machine 14 include more than two interconnected input / output devices 304. . A general interconnect matrix (GPIM) 16 includes a 16 bit data path
Preferably implemented as -ary two cubes.

In the above description, the various components of the present invention are preferably implemented using reconfigured hardware resources. Reconfigurable logic device manufacturers generally publish guidelines for implementing conventional digital hardware using reprogrammable or reconfigurable hardware resources. For example, 19
The 1994 Xilinx Programmable Logic Device Data Book (xilinx, Inc., San Jose, CA) includes the following application notes: That is, application note XAPP00
5.002 "Register based FIFO", application note XAPP044.00 "High performance RAM based FIFO", application note XAPP013.
001 "Use of carry-only logic in XC4000", application note XAPP018.00
"Estimation of XC4000 Adder and Counter Performance", Application Note XAPP028.0001, "Frequency / Phase Comparator for Phase Locked Loop", Application Note XAPP031.000, "XC400
Use of 0RAM ", Application Note XAPP0
36.001 "4-port DRAM control
La. . . Application Note XAPP039.
001 is an application note of “18-bit pipeline accumulator”. Materials published by Xilinx also include articles included in XCELL, a quarterly magazine for Xilinx programmable logic users. For example, the third issue of 1994 (the 14th edition) contains a detailed article on the implementation of a high-speed integer multiplier.

The system 10 described in this specification
Is an extensible, parallel computer architecture for dynamically implemented multiple instruction set architectures (ISAs). Every S machine 12 is another S machine 12
Independently of external hardware resources such as a computer and a host computer, it alone can execute the entire computer program. In any S-machine 12, a multiple instruction set architecture (ISA) is implemented continuously during program execution in response to reconfiguration interrupts and / or reconfiguration instructions embedded in the program. Since system 10 preferably includes multiple S-machines 12, it is preferred that multiple programs be executed simultaneously, and each program may be independent. Therefore, since the system 10 preferably includes multiple S machines 12, a multiple instruction set architecture (IS
A) is activated simultaneously (ie, in parallel) at any time except during system initialization or reconfiguration. That is, at any time, multiple sets of program instructions are executed simultaneously, and each set of program instructions is executed according to a corresponding instruction set architecture (ISA). Each such instruction set architecture (ISA) is unique.

The S machine 12 is composed of a plurality of T machines 14
, A general interconnect matrix (GPIM) 16 and each input / output T machine 18 to communicate with each other and with input / output devices 20. Each S-machine 12 is itself a complete computer, capable of performing independent operations, but any S-machine 12 can be any other S-machine 12 or system 1
0 can function as a master S-machine 12 and transfer data and / or commands to other S-machines 12 to one or more T-machines 16 to one or more I / O T-machines 18 , To one or more input / output devices 22.

Thus, the system 10 of the present invention is a system that can be spatially and temporally divided into one or more data parallel (sub) problems, such as image processing, medical data processing, calibrated color matching, database It is particularly useful for calculations, document processing, associative search engines, and network servers. For a computation problem with many operand strings, data can be in parallel if the algorithm can be applied so that efficient computation can be speeded up by the parallel computation method. The data parallel problem has a known complexity, which is
(N ^k ). The value of k depends on the problem. For example, k = 2 in image processing and k = 3 in medical data processing. In the present invention, each S-machine 12 is preferably used to exploit data parallelism at the level of a program instruction group. Since system 10 includes multiple S machines 12, system 10 is preferably used to exploit data parallelism at the level of the entire program.

The present invention can completely reconfigure the instruction processing hardware of each S machine 12 in order to optimize the calculation performance of such hardware for the calculation required at any moment. The system 10 provides a large amount of computing power. Each S machine 12 can be reconfigured independently of the other S machines 12. System 1
0 advantageously treats each configuration data set as a programmed boundary, or interface, between software and the reconfiguration hardware described herein, and thus each instruction set architecture (ISA). Further, the architecture of the present invention facilitates building reconfigurable hardware at a high level to selectively address real system problems in situ, where interrupts affect instruction processing. Methods, including the need for a decision latency response that facilitates real-time processing and computer performance, and the need for a selectable response to defect processing.

[0127] Unlike other computer architectures, the present invention discloses that silicon resources can be utilized to the full at all times. The present invention provides a parallel computer system that can be expanded to a desired size at any time, and a large parallel system including thousands of S machines 12 is possible. Such scalability of the architecture is possible because S-machine based instruction processing is intentionally decoupled from T-machine based data communication. This instruction processing / data communication separation model is
Very suitable for data parallel computing. The internal structure of the S machine hardware is preferably optimized for instruction time flow, while the internal structure of the T machine hardware is preferably optimized for valid data communication. The set of S machines 12 and the set of T machines 14 are separable and configurable components in the spatial and temporal divisions of data parallel computation, respectively.

Using the present invention, it may be possible to utilize future reconfiguration hardware to build a system with better computational performance while maintaining the overall structure described in this specification. . In other words, the system 10 of the present invention is technically scalable. Nearly all currently used reconfigurable logic devices use memory-based complementary metal oxide semiconductor (CMOS) technology. Advances in device capabilities have been following the trends in semiconductor memory technology. In future systems, the reconfigurable logic used to build the S-machine 12 will be:
It would include a partition of internal hardware resources according to the inner loop and outer loop instruction set architecture (ISA) described herein. Even large-scale reconfigurable logic devices simply provide the ability to perform more data parallel computations within a single device. For example, a larger functional unit 194 included in the second exemplary embodiment of the data operation unit (DOU) 63 described above with reference to FIG. 13 would include a larger size image processing kernel. One skilled in the art will recognize that the technical scalability provided by the present invention is not limited to CMOS-based devices and is not limited to field-programmable gate array (FPGA) -based implementations. Thus, the present invention provides technical scalability independent of the particular technique used to achieve reconfigurability or reprogrammability.

FIG. 22 is a flowchart of a preferred method for scalable, parallel, dynamic reconfiguration computation. FIG.
Is preferably executed in each S machine 12 in the system 10. The preferred method begins at step 1000 of FIG. 22, where the reconstruction logic 104 retrieves a configuration data set corresponding to an instruction set architecture (ISA). Next, in step 1002, the reconstruction logic 104 according to the configuration data set retrieved in step 1000, the instruction fetch unit (IFU) 60, the data arithmetic unit (DOU) 62, and the address arithmetic unit (AO)
U) 64, which provides a dynamic reconfigurable processor (DRPU) hardware organization for an instruction set architecture (ISA) implementation currently under consideration. After step 1002, step 100
At 4, the interrupt logic 106 retrieves the interrupt response signal stored in the architecture description memory 101 and corresponds to the transition control signal that determines how the current dynamic reconfiguration processor (DRPU) configuration responds to the interrupt. Generate a set. After that, the instruction set architecture (IS
A) 100 initializes program state information in step 1006. Then the instruction set architecture (IS
A) 100 starts an instruction execution cycle in step 1008.

Next, at step 1010, the instruction set architecture (ISA) 100 or the interrupt logic 1
06 determines if reconstruction is needed. When a reconfiguration instruction is selected during program execution, instruction set architecture (ISA) 100 determines that reconfiguration is required. Interrupt logic 106 determines that reconfiguration is required in response to the reconfiguration interrupt. If reconfiguration is required, the preferred method proceeds to step 1012, where the reconfiguration handler saves program state information. Preferably, the program state information includes a reference to a configuration data set corresponding to a current Dynamic Reconfiguration Processor (DRPU) configuration. After step 1012, the preferred method returns to step 1000 to retrieve the next set of configuration data referenced by the reconfiguration instruction or reconfiguration interrupt.

If no reconfiguration is required at step 1010, then at step 1014 the interrupt logic 106
Determines if a non-reconfiguration interrupt needs to be performed. If necessary, then, at step 1020, the instruction set architecture (ISA) 100 allows the transition from the current instruction state sequencer (ISS) state to the interrupt execution state in the instruction execution cycle based on the transition control signal. To determine if it is. When the transition to the interrupt execution state is not allowed, the instruction set architecture (ISA) 100 proceeds to the next state of the instruction execution cycle and returns to step 1020. The current instruction state sequencer (IS
When the transition from the S) state to the interrupt execution state is permitted, the instruction set architecture (ISA) 100 proceeds to the interrupt execution state in step 1024. At step 1024, the instruction set architecture (ISA)
100 saves program state information and executes program instructions to perform interrupts. Step 102
After 4, the preferred method returns to step 1008 to resume the current instruction execution cycle if it was not completed, and to start the next instruction execution cycle (if it was).

If it is not necessary to perform a non-reconfiguration interrupt at step 1014, this preferential method is
Proceeding to 016, it is determined whether the execution of the current program has been completed. If execution of the current program is to continue, the preferred method returns to step 1008 to begin another instruction execution cycle. Otherwise, the priority method ends.

The present invention incorporates a meta-addressing mechanism for performing the memory operations required by the architecture of the present invention. According to the invention, the T machine 14 is used as an addressing machine. The T-machine 14 performs interrupt handling, message queuing, meta-address generation, and control of the overall transfer of data packets. FIG. 23 is a configuration diagram of the data packet 1800 based on the present invention. Data packet 18
00 is a data part 1824 and a command part 1820
, A source geographic address 1816, a size separator 1812, a destination local address, and a destination geographic address 1804. The meta address 1828 is
A destination geographic address 1804 and a destination local memory address 1808 are included. Destination local memory address 1808 specifies where in local memory 34 the data of data packet 1800 is to be written. Destination geographic address, or interconnect address 1804, specifies which T-machine 14 should receive data packet 1800. Source geographic address 1816 specifies the T-machine 14 that generated the data packet 1800.

Any two pairs of source geographic addresses 1816
And destination (destination) geographic address 1804, 26
One path to the 4-bit local address space is uniquely determined. However, there are two or more such paths in the system and can operate in parallel. S machine 12 has a T coupled to it.
The number of machines 14 may be included, up to a number corresponding to the local memory bandwidth, or any number taking account of the matrix effect. Therefore, in the present invention, scalability by an indeterminate power of 2 is possible, the processors in the system may be uneven, and the number of unique paths to each S machine 12 can be arbitrarily expanded. can do. This type of scalability is important in many applications, such as distributed image processing, and the pyramids or trees of the dynamic reconstruction component can be configured to provide more communication bandwidth for the higher levels of the system. Maybe. If desired, implement this pyramid architecture by allowing more constant-speed T-machines 14 to access the higher levels of the pyramids of S-machines 12 to provide the S-machines 12 with the greatest need for addressability. Give this ability. This results in a cost-effective system because system resources can be concentrated on most processing and communication tasks.

In the preferred embodiment, the metaaddress is 80
Bit width. In this example, the geographic address is 16
Bits, and the local memory address is 64 bits wide. 65536 with a 16 bit geographic address
Individual geographic addresses can be specified. Each local memory 3 has a 64-bit local memory address.
Within 4 2 ⁶⁴ individually addressable bits can be specified. Each S-machine 12 includes a local memory 34 configured for a particular S-machine 12. Since the S machine 12 and the memory 34 are separated from each other, the sizes and structures of the memories do not need to be uniform, and it is not necessary to maintain coherency and consistency of the entire memory. The source S machine 12 program instructions are written with the architecture of the local memory 34 of the destination S machine 12 in mind, and are independent of their size and layout as long as the program instructions specify memory locations accurately. The local memory 34 of the destination S machine 12
Can be easily addressed. This modularity allows the architecture to be scaled up and down using a variety of components, independent of the problem handling. New S
The way machines are integrated has also been greatly simplified. When a new S-machine 12 is added to the system, a new geographical address is selected for the S-machine 12 and the program requesting use of the new S-machine 12 is given the new address. Once the new address is incorporated into a program designed to take advantage of the new S-machine 12, the S-machine 12 is integrated without any problems to solve and without having to perform any calculations.

FIG. 24 is a flowchart showing the flow of the processing of the S machine 12 of the present invention for requesting a remote operation. At step 1900, S machine 12 receives the instruction. In step 1904, S machine 12 determines whether the instruction requires remote computing. If this instruction does not require remote operation, step 1906
Executes this instruction. If the instruction requires remote operation, at step 1904 the remote operation information is stored in local memory. After proceeding to step 1920 as described below, the S-machine 12 determines that the instruction requires remote operation by examining the state of a flag in the instruction code that indicates whether remote operation is required. I do. A remote operation is an operation that requires the use of a different S-machine 12 to obtain a result. The remote operation information is provided by a program executed by the S machine 12 and stored in the local memory 34 when the execution of the remote operation is desired. Preferably, certain memory locations in local memory 34 are used to store remote operations, so that T-machine 14 has immediate access to information and does not need to obtain an address first.
The remote computing information generally includes a target geographic address 1804 of the remote T machine 14, a target local memory address 1808 for storing data on or retrieving data from the remote S machine 12, command information 1820, , Size information 1812 and data 1824
And All of this information is stored by the S-machine 12 in local memory 34 as soon as the instruction is determined to require remote operation.

In one embodiment, at step 1912 S
Machine 12 sends T to indicate that remote computing is required.
Issue unconditional instructions to the machine. An unconditional instruction is a unique command sequence designed to be recognized by the T machine 14. The unconditional instruction generally includes a memory address where the remote operation information is stored in the local memory 34, and a size delimiter indicating the size of the addressing information. This allows multiple remote operations to be requested at once by the program running by the S-machine 12, simply by specifying the starting address of the remote operation information and a series of size delimiters. At that time, the T-machine 14 can sequentially process different requests for information. Next, in step 1920, the S machine 12 determines whether there are any other instructions to execute. When an instruction exists, the next instruction is received and executed. Therefore, the S machine 12 can execute the instruction almost instantaneously regardless of the request for the remote operation regardless of the request. Since the T machine 14 performs the data transfer and the search, the processing capability of the S machine 12 can be concentrated only on the processing of the instruction. FIG. 25 is a flowchart of the processing of the T machine 14 that receives an unconditional instruction from the S machine 12. First, at step 2000, T machine 14 determines whether the command received from S machine 12 on control line 48 is an unconditional command. If the command is determined to be an unconditional command, the T machine retrieves the remote computation information from local memory 34 via memory / data line 46 in step 2004. The remote operation information is stored in the memory 34 so that the T machine 14 does not need to determine a new memory address each time the remote operation information is searched when searching for data.
It is preferable to be stored in a certain place. The remote operation information can be stored in any location of the local memory 34. However, in this case, the location of the information must be transmitted as part of the unconditional command. After retrieving the telecomputed information, the T-machine 14, and particularly the Common Interface Controller (CICU) 302 component of the T-machine 14, in step 2008 retrieves the meta-address 18 from the information.
28 is generated. Destination local memory address 1808
Is attached to destination geographic address 1804 to form meta-address 1828. Next, step 2112
At T, the T-machine 14 generates a data packet 1800 from the remaining telecomputation information and transmits the data packet 1800 to an interconnect device or general interconnect matrix (GPIM) 16 for transmission to the required destination.

The source geographic address 1816 may be specified by a program instruction, thus
4 may be stored in the local memory 34 for retrieval. The source geographic address 1816 is stored in an architecture description memory (ADM).
emory) 101. The architecture description memory (ADM) 101 is a changeable memory that stores the geographic address of the T machine 14 to which it is coupled. Architecture description memory (ADM) 1
01 can be used to explicitly change the geographic address of the entire system. In an embodiment of this system, T machine 14 has an architecture description memory (ADM) 101.
From the T18 machine
4. Make sure it is using its own newest source geographic address 1816. In an embodiment where multiple common interface controllers (CICUs) 302 are coupled to each S machine 12, each common interface controller (CICU)
The geographic address of 302 is stored in the architecture description memory (A
DM) 101.

FIG. 26 is a flowchart showing a process of the T machine 14 for receiving a data packet transmitted via the interconnection device. At step 2100, T machine 14 receives a data packet from the interconnection device. In step 2104, the T machine 14 sets the meta address 182
The data packet 1800 is decoded by analyzing the eight destination geographic address 1804 components.
As described above, the address decoder 320 of the T machine
Decrypts the data packet 1800. Step 21
At 08, the address decoder 320 sets the destination geographical address 18
04 and the associated geographic address. In an embodiment using a modifiable architecture description memory (ADM) 101, address decoder 320 receives received geographical address 1804 and architecture description memory (AD).
M) Compare with the address stored in 101. If the address decoder 320 determines in step 2112 that the geographic addresses match, the data packet 1800
Is transmitted to the location in memory 34 specified by local memory address 1808. Data packet 180
A 0 is parsed, the data is sent via a memory / data line 46, and the command is sent via a control line 48.
The address information is sent via an address line 44.
If the addresses do not match, an error message is transmitted through the bypass FIFO 324, the MUX 328, and the general interconnect matrix (GPIM) 16 to the T machine 14 identified by the source geographic address 1816 component of the data packet 1800.
The same process described above is used when the T-machine 14 receives an incorrectly addressed data packet 1800. When a new data packet 1800 is received and the CICU 304 is assembling or disassembling the data packet 1800, the T-machine 14 waits until the CICU 304 can receive and process the data.
Sends the data packet 1800 to the input FIFO 322 and waits.

In another embodiment, the T machine 14 is designed to recognize the priority of the message and interrupt the processing of the S machine 12 when it is appropriate to have the S machine process the new command. . In this embodiment, as shown in FIG. 27, a common interface control device (CI
The CU 302 further includes additional components including an interrupt logic 2200, a comparator 2204, and a recognizer 2208. FIG. 28 is a flowchart showing the interrupt processing capability of the common interface control device (CICU) 302. Step 2300
After recognizing the address by the address decoding 320, the recognizing device 2208 analyzes the data packet 1800 and identifies the parse command 1820. Step 23
At 04, the recognizer 2208 determines whether the command 1820 is an interrupt request. Data packet 180
If 0 is an interrupt request, command 1820 will include an interrupt ID. If the command 1820 does not include an interrupt ID, the data packet is sent to the common interface controller (CICU) 302 in step 2308 to perform the processing described above.

When the command 1820 includes an interrupt ID, the interrupt ID is sent to a comparator 2204 coupled to the memory 34. The memory 34 stores a list of interrupt IDs. Each S-machine preferably includes a list of interrupt IDs for which the S-machine is designed to be stored in its associated local memory 34. The list identifies the interrupt, specifies the priority of the interrupt, and includes instructions for executing the interrupt. In step 2312, the comparator 2204 compares the interrupt ID of the received command with the stored list of IDs. If the interrupt ID specified by the command does not match the ID in the list, then at step 2320 an error message is transmitted via bypass FIFO 324, MUX 328 to the destination specified by source geographic address 1816, and a general purpose interconnect via signal line 314. Binding matrix (GPI
M) 16. If the interrupt ID matches the stored ID, then in step 2324 the interrupt logic 2200 determines whether the local memory 3 associated with the stored ID
Processing the interrupt according to the information contained in the data packet 4 or according to the information contained in the data packet 1800;
The obtained command is sent to the S machine 12 via the control line 48.

When the priority can be compared, the interrupt logic 2200 determines the priority of the interrupt request and the current input F.
The priority of the data packet 1800 in the IFO 322 is compared. When the priority of the interrupt request is higher than the data packet 1800 of the FIFO 32, the interrupt request is placed before the data packet 1800 of the lower priority of the interrupt request.
In some cases, the interrupt request may require that the S machine 12 stop executing. In this case, the priority level is assigned to the process running on the S machine 12. When the priority of the interrupt request is higher than the priority of the currently executing process, the interrupt logic 2200
The S machine 12 sends a command to the S machine 12 via the control line 48 to terminate the current processing and start processing the interrupt request. Thus, a complete priority comparison and interrupt handling scheme is provided for the T machine 1 based on the architecture of the present invention.
4, the S machine 12 rarely needs to perform any additional processing.

Therefore, S machine 12 can execute the main instruction of the program because T machine 14 performs all the memory operation functions required by the computer system. Spatial memory and instruction execution operations
By separating in time, the processing power of a highly parallel system composed of multiple processors can be greatly optimized. Since no virtual memory or shared memory is used, there is no need to perform hardware consistency and coherence calculations. The S-machines 12 can operate at different rates, and the instruction set architecture (ISA) implemented by the dynamically reconfigurable S-machines 12 can be different. Further, a field programmable gate array (FPGA) for realizing the S machine 12
Are also optimized for specific tasks. For example, when calculating the embedded image, the S-machine 12 with the front panel LCD screen controller optimized for image processing
You don't have to. However, for every S machine 12 in the system, each S machine that needs to communicate with another S machine
Ensuring that the machine 12 is uniformly addressable is still highly desirable, and is obtained by the present invention as described above. The software is used to obtain coherency or consistency of the entire system, including the S machine 12 and the T machine 1
Conventional methods are used, such as a message transfer interface (MPI) run-time (run-time) library for H.4 and a run-time library for a parallel virtual machine (PVM). Both MPI and PVM function as a hardware abstraction layer (HAL). According to the present invention, HAL
Is a dynamically reconfigurable S machine 12 and a fixed T machine 1
For four. Since the memory operations are completely controlled by software, the system is dynamically reconfigurable and is not affected by complex hardware / software interactions. Thus, a fully scalable and architecturally reconfigurable computer system using independently separated memory and having separate addressing and processing machines is provided for use in highly parallel computing environments. Is done. By using meta-addresses, transparent and fine addressing is possible, and communication paths of a computer system can be assigned or reassigned as required by the system. By separating the addressing machine from the processing machine, the resources of the processing machine can be concentrated on processing only, the processing machine can utilize different instruction set architectures and operate at different rates, and Each of them can be implemented using optimized hardware. All of these significantly increase the processing power of the system.

The disclosure of the present invention is significantly different from other systems for reprogrammable or reconstructed calculations. In particular, the present invention is not equivalent to a downloadable microcode architecture, as such architectures generally rely on non-reconfigurable control means and non-reconfigurable hardware. The present invention provides an additional reconfigurable processor (AR) in which a set of reconfigurable hardware is coupled to a non-reconfigurable host processor or host system.
P) It is clearly different from the system. Additional reconfigurable processor (ARP) devices are subordinate to hosts that execute some programs. Thus, the silicon resources of the additional reconfigurable processor (ARP) device or the host are idle or inefficiently used when the host or the additional reconfigurable processor (ARP) device respectively operate on the data,
Available silicon resources are not fully utilized in the time frame of program execution. In contrast, each S machine 12 is an independent computer that can easily execute the entire program. Multiple S machine 12
Preferably, the programs are executed simultaneously. Thus, the present invention discloses that silicon resources are always maximized for both each program running on an individual S machine 12 and for multiple programs running on the entire system 10.

An additively reconfigurable processor (ARP) device provides a computational accelerator for a particular algorithm at a particular time and is implemented as a set of gates that are optimally interconnected for a particular algorithm. The use of reconfigurable hardware resources for general purpose operations such as managing instruction execution has been avoided in additively reconfigurable processor (ARP) systems. Further, additive reconfigurable processor (ARP) systems do not treat a given set of interconnections as easily reusable resources. On the other hand, the present invention discloses a dynamic reconfiguration processing means configured for efficient management of instruction execution according to an instruction execution model most suitable for a calculation need at a specific time. The S-machine 12 includes a plurality of reusable resources, such as an instruction state sequencer (ISS) 10
0, interrupt logic 106, and store / align logic 1
52. The present invention discloses the use of reconfigurable logic resources at the level of logic blocks (CLBs), input / output blocks (IOBs), and reconfiguration interconnects, rather than at the level of interconnect gates. Thus, the present invention does not disclose a single gate connection scheme useful for a single algorithm, but rather reconfigurable high level logic components useful for performing operations on all classes of computational problems. Disclose use.

Generally, an additional reconfigurable processor (AR)
The P) system is for translating a particular algorithm into a set of interconnected gates. Some additive reconfigurable processor (ARP) systems attempt to compile high-level instructions into an optimal gate-level hardware configuration, which is generally an NP hardware problem. In contrast, the present invention discloses the use of a compiler for dynamic reconfiguration computation that compiles high-level program instructions into assembly language instructions according to a variable instruction set architecture (ISA) in a very simple manner.

An additional reconfigurable processor (ARP) device generally cannot handle its host program as data, and cannot adapt itself to a computing environment. On the other hand, each S machine 12 of the system 10 can handle its own program as data, and thus can easily adapt itself to the computing environment. The system 10 can easily simulate itself by executing its own program. The present invention can also compile its own compiler.

According to the present invention, a single program includes the first program.
A first instruction group belonging to an instruction set architecture (ISA) and a second instruction set architecture (ISA)
And a third instruction group belonging to yet another instruction set architecture (ISA). . . Contains. The architecture disclosed herein executes each such instruction group using hardware that is configured at run time to implement the instruction set architecture (ISA) to which the instruction belongs. No prior art system or method provides a similar disclosure.

The present invention further provides that the interrupt latency, interrupt accuracy, and programmable state transition enabling are provided by an instruction set architecture (ISA) currently under consideration.
Discloses a reconfiguration interrupt scheme that varies according to Other computer systems do not share the same disclosure. The present invention further differs from prior art computer systems in that the reconstructed data path bit width,
A computer system having an address bit width and a reconfiguration control line width is disclosed.

Although the invention has been described using several preferred embodiments, those skilled in the art will recognize that various modifications may be made.

<Reference Material A> Instruction set 0, general-purpose external loop instruction set architecture (ISA) 1.0 Programmer's architecture model In this section, registers,
Instruction set architecture (I) that includes memory models, call conventions and interrupt models from high-level languages
3 shows the schematic concept of the programmer for the SA) 0 architecture.

1.1 Registers The instruction set architecture (ISA) 0 consists of 16 1
6-bit general register, 16 address registers, 2
Processor status registers and one interrupt vector register. The mnemonics of the data and address registers use hexadecimal numbers, so the last data register is df. And the last address register is af. One of the processor status registers, nipar (Next Instruction Program Address Registe
r) indicates the address of the next instruction to be fetched (fetched). The other status register, pcw (Processor
Control Word) includes flags and control bits used to perform program flow and interrupt processing. The bits are defined in Table 2. Undefined bits are reserved for future use. Four condition flags, Z, N, V and C, are set as side effects of various instructions. See Section 2.0 for an overview of which flags are affected by each instruction.

T (Trace Mode) and IM (Interrupt Ma
The sk) flag controls how the processor responds to interrupts and when traps are handled. The interrupt vector register ivec holds a 64-bit address of the interrupt service routine. Interrupts and traps are described in section 1.4 below.

[0154]

[Table 1]

1.2 Memory Access The value stored in the 64-bit address register is 1
Used by memory load / store instruction access memory in 6-bit and 64-bit increments (see Table 7). The address is a bit address. That is, address 16 is a word (word) starting at bit 16 in the memory.
Point to. Words can only be read on 16-bit boundaries, so the four LSBs (least significant bits) of the address register are ignored when reading memory. K
See [1] for details of the _ISA concept. 64
The bit values are stored as 16-bit words in little-endian order (the order in which the least significant 16 bits are stored at the least significant address).

[0156]

[Table 2]

1.3 Call Convention By convention, register af is used by the C program as a stack pointer, and register ae is used as a stack frame pointer. The mnemonics sp and fp are sometimes used as aliases for these registers. All other registers are free for general use. The stack grows downward.

Int is 16 bits, long is 64, and a is void *. The int value is returned at d0, and the values of long and void * are returned at a0. d0-d4 and a0-a3 are clovered by the function, and all other general purpose registers must be kept on the function call. Upon entry to the function, the stack pointer points to the return address, and thus the first argument is the address sp +
It starts with 64 (decimal).

1.4 Trap and Interrupts Instruction Set Architecture (ISA) 0 operates on one interrupt line, and software traps from two sources. All are the same control flow (flow
-of-control) Invoke the transfer mechanism.

Externally, there is a single INTR signal input and one iack output. iack is active while the interrupt mask bit in pcw is cleared by resetting pcw with the xpcw instruction or by returning from the interrupt and returning pcw to its original value with the rti instruction. Becomes The amount of time between the signaling of the interrupt by the external device and the servicing of the interrupt by the processor is:
It depends on the currently executing instruction and the existence of the software trap.

A software trap is triggered by an explicit trap instruction or by executing an instruction with the T (trace) flag set. In this case, T
After the first instruction following the setting of, control is transferred to the interrupt service routine. When the trap instruction is executed, the processor sets the T flag and enters the interrupt service routine as if the T flag had been set before executing the instruction. Interrupt service is not performed while the T flag is set. No more traps will occur until the T flag is cleared by resetting pcw with the xpcw instruction or resetting from the stack by returning from an interrupt with the rti instruction.

An interrupt is generated by the presence of an active signal in the intr external signal. When the im flag or the T flag is set, interrupts are masked and undetermined interrupts are ignored. When the im and T flags are cleared, control is transferred to the interrupt service routine after the first instruction following the assertion of intr. Upon entering the interrupt service routine, the im flag is set by the processor. xpcw instruction resets pcw or rti
No further interrupts will occur until the im flag is cleared by being reset from the stack by return from interrupt by instruction.

When an interrupt or trap occurs, the steps taken by the processor are as follows. 1. Complete all currently executing instructions. 2. The 16 data registers (d0 first), 16 address registers (a0 first), pcw, ivec and nipar are pushed onto the stack (pointed to by register af) in this order. The value of af pushed onto the stack is its value before the interrupt or trap service begins. 3. When this is an interrupt, the interrupt bit in pcw is set to mask further interrupts.
If this is a trap instruction, the T flag is set. If this is a trap generated by the T flag, pcw is not changed. 4. Loads the value in the ivec register into nipper. Execution of the instruction in the interrupt handler begins.

At the time of execution of the rti instruction, the following operation is performed. 1. A register is recovered from the stack in the reverse order that it was written. 2. Resume execution.

If the interrupt mask flag has not been cleared, it is cleared by the rti instruction. p
Unless the value of cw is changed on the stack, it was cleared when the service routine was entered. When the T flag is set by executing a trap instruction, it is cleared upon execution of rti for the same reason. If a trap occurs due to the T flag set before entering the service routine,
To confirm that a trap has occurred, it must be cleared by a service routine. When the interrupt mask flag is cleared by any means, the external output signal iack is active for one clock cycle to send a signal to the external device being interrupted.

2.0 Classification of Instructions by Function Notation conventions are as follows.

[0167]

[Table 3]

2.1 Operation of Register

[0169]

[Table 4]

2.2 Logical operation

[0171]

[Table 5]

2.3 Memory Load / Store

[0173]

[Table 6]

2.4 Arithmetic Operations

[0175]

[Table 7]

2.5 Control Flow

[0177]

[Table 8]

3.0 Alphabetic Reference Symbols The instructions set for Instruction Set Architecture (ISA) 0 are listed below in alphabetical order. The mnemonics are shown in a short description. Below that is the binary code of the instruction. Each row of the binary code is a 16-bit word. The affected flags are listed below. Unless otherwise specified, flags are set using data stored in the destination register. nipar assumes that it has already been incremented at the start of instruction execution. Finally, a text description of the meaning of the instruction is shown.

The notation conventions used for binary codes are summarized in the table below. Table 59 shows the condition codes.
Is defined in

[0180]

[Table 9]

[0181]

[Table 10]

The two data registers are added, and the result is left in the destination register.

[0183]

[Table 11]

The two data registers and the carry flag are added, and the result is left in the destination register.

[0185]

[Table 12]

An 8-bit signed (two's complement) constant is added to the data register and the result is left in the register.

[0187]

[Table 13]

Bitwise AND of two data registers
And leave the result in the destination register.

[0189]

[Table 14]

When the condition is true, (offset << K _isa )
Is added to nipar.

[0191]

[Table 15]

(Offset << K _isa ) is added to nipar.

[0193]

[Table 16]

Shift to right by 8 bits conditionally and mask. Used after the load instruction to align the 8-bit data read from the word offset. When the address contained in the source address register is on an 8-bit boundary (having 2 bits set), the value in the data register is shifted right by 8 bits. Address is 8
If not on a bit boundary, the upper 8 bits of the register are cleared.

[Note] The negative flag is set by bit 7 instead of bit 15. This facilitates code extension of an 8-bit amount.

[0196]

[Table 17]

By subtracting the source register from the destination register, a flag for comparing the absolute values of the two data registers is set, and only the flag is affected.

[0198]

[Table 18]

A signed division of a 32-bit signed integer is performed by a 16-bit signed integer, and a 16-bit signed quotient and remainder are returned. The 32-bit dividend is stored in two consecutive registers starting from the index of the destination register (little endian order). The 16-bit divisor is in the source register. The remainder is returned to the destination register,
The quotient returns to the register after the destination register (modulo 1
6). When the quotient exceeds 16 bits, an overflow occurs.

[0200]

[Table 19]

The data register is added to the address register, and the result is left in the address register.

[0202]

[Table 20]

The 8-bit signed constant is added to the address register, and the result is left in the address register.

[0204]

[Table 21]

By subtracting the source register from the destination register, a flag for comparing the absolute values of the two address registers is set, and only the flag is affected.

[0206]

[Table 22]

The two address registers are added, and the result is left in the destination register.

[0208]

[Table 23]

The source register is subtracted from the destination register, and the result is stored in the destination register.

[0210]

[Table 24]

The load is post-incremented in the address register. The memory is read from the address pointed to by the source register and placed in the destination register.
Next, the source register is incremented.

[0212]

[Table 25]

The address register is shifted right by one bit.

[0214]

[Table 26]

The data is stored from the address register. Write the 64-bit value in the source register to the memory location pointed to by the destination register. This value is written as four 16-bit words arranged in little endian order.

[0216]

[Table 27]

The store from the address register is pre-decremented. Decrement the destination register, then write the value in the source register to the memory location pointed to by the destination register. This value is written as four 16-bit words arranged in little endian order.

[0218]

[Table 28]

The data register is subtracted from the address register, and the result is left in the address register.

[0220]

[Table 29]

The source register is inverted and placed bit by bit in the destination register.

[0222]

[Table 30]

A conditional jump is made to an absolute address. See Table 59 for the definition of the condition code bits.

[0224]

[Table 31]

An unconditional jump to an absolute address is performed. The condition “always” is the same as jCC.

[0226]

[Table 32]

The destination register is first incremented and then the current nipar (pointing to the next instruction) is added to the address pointed to by the destination register (usually the stack pointer).
Is stored. Next, nipar is loaded with the address in the source register before fetching the next instruction.

[0228]

[Table 33]

Shift the data register to the left by a bit constant.

[0230]

[Table 34]

The data register is shifted right by a bit constant.

[0232]

[Table 35]

Load data register from memory.
Load the value pointed to by the source address register into the destination data register.

[0234]

[Table 36]

The load into the data register is post-incremented. The memory is read from the address pointed to by the source address register and stored in the destination data register. Next, the source register is incremented.

[0236]

[Table 37]

Load the 16-bit adjacent value into the data register.

[0238]

[Table 38]

The destination register is replaced by the bitwise inversion of the source register, and the destination register is added.

[0240]

[Table 39]

Put the value in the source data register into the destination data register.

[0242]

[Table 40]

The result of multiplying the value in the source register by the value in the destination register is stored in two consecutive registers starting with the destination register (little endian order).

[0244]

[Table 41]

Perform a bitwise OR of the two data registers and leave the result in the destination register.

[0246]

[Table 42]

The data register is shifted one bit to the left. Replace LSB (least significant bit) with the value of the carry flag. At the end of the instruction, the original MSB (most significant bit) is placed in the carry flag.

[0248]

[Table 43]

See section 1.4 above. Use the source register as a stack pointer.

[0250]

[Table 44]

Return from subroutine. Load nipar from the memory location pointed to by the destination register (usually the stack pointer). Next, the destination register is incremented.

[0252]

[Table 45]

Shift the destination register to the left by the number of bits specified by the value in the source register.

[0254]

[Table 46]

The destination register is shifted to the right by the number of bits specified by the value in the source register.

[0256]

[Table 47]

Data is stored from the data register.
Write the value in the source to the memory location pointed to by the destination register.

[0258]

[Table 48]

The store is pre-decremented from the data register. Decrement the destination register, then write the value in the source register to the memory location pointed to by the destination register.

[0260]

[Table 49]

The source register is subtracted from the destination register, and the result is stored in the destination register.

[0262]

[Table 50]

The source register is subtracted from the destination register, then the carry bit is subtracted, and the result is stored in the destination register.

[0264]

[Table 51]

Execute the interrupt handler. See section 1.4. Use the destination register as a stack pointer.

[0266]

[Table 52]

Unsigned division of a 32-bit signed integer by a 16-bit signed integer is performed, and a 16-bit signed quotient and remainder are returned. Store 32 bits in two consecutive registers starting from the index of the destination register (little endian order). The divisor is in the source register. The remainder is returned to the destination register, and the quotient is returned to the next register after the destination register. When the quotient exceeds 16 bits, an overflow occurs.

[0268]

[Table 53]

The result of multiplying the value in the source register by the value in the destination register is stored in two consecutive registers starting with the destination register (little endian order).

[0270]

[Table 54]

Transfer the value in the source address register to four consecutive data registers starting at the destination register. This value is stored in little endian order, and the destination register address is calculated by modulo 16 so that the destination register may be any register.

[0272]

[Table 55]

Transfer the little endian 64-bit values in four consecutive data registers into the destination address register. Modulo 16 source register address
And the destination register may be any register.

[0274]

[Table 56]

Perform a bitwise exclusive OR of the two data registers and leave the result in the destination register.

[0276]

[Table 57]

Exchange the value in the source data register with the pcw register.

[0278]

[Table 58]

Exchange the value in the source address register with the ivec register.

4.0 Condition Code The values from the table below are used in the condition code operation code subfield.

[0281]

[Table 59]

<Reference Material B> Instruction Set 1, Pipeline Multiply / Accumulate Instruction Set Architecture (ISA) IS
A1-Pipeline Convolution Engine for XC4013 Introduction Instruction Set Architecture (ISA) 1
Is a pipeline multiply-accumulate array capable of performing four simultaneous multiplications / accumulations per instruction cycle. One for each input to the four 8-bit × 8-bit multipliers, ie, eight 8-bit data registers (xd0-xd3 and yd0-y
d3) There is. The four multiplier outputs are summed through the pipelined summation array until one final 16-bit sum is available, and up to four 16-bit registers can store the result (m0-m4). Instruction Set Architecture (IS
A) The 1 architecture assumes a flow-through batch processing cycle in main memory. There is no feedback path through the multiplier accumulator data path to recycle the accumulation results. This is because emphasis is placed on memory data flow. No provision is made for overflow scaling or extended finite accumulation. The instruction set architecture (ISA) 1 assumes that the coefficients used for convolutional filtering give a result finiteness not exceeding 16 bits for all data sets. The multiplication array receives an 8-bit two's complement data input,
Produce a 6-bit two's complement result.

Access to memory is managed by two 16-bit address registers (a0 and a1), which can be considered compatible source and destination pointers. Program flow is managed by standard 64-bit NIPAR registers, with the 64-bit interrupt vector register being supported for single interrupts, such as frame or data ready interrupts (IVEC).

The instruction set architecture (ISA) 1 instruction set is very small, aligned to a 16-bit word size, corresponding to a K _ISA = 4 memory organization for the general purpose external loop processor instruction set architecture (ISA) 0. I have. Instruction Set Architecture (ISA)
Up to seven arithmetic operations can be instantiated in a single clock cycle at one, with production keeping the results at a rate of one per clock over a small window of clocks and indexing new source or destination addresses. To transfer register data from and to memory in parallel with calculations. Instruction set architecture (ISA) 1 instruction set Data move ld (reg-vector) 14-bit bitmap right justified in instruction word
According to the reg-vector, up to 14 registers are sequentially loaded from the memory.

St (reg-vector) 14-bit bitmap right-aligned in instruction word
According to the reg-vector, up to 14 registers are sequentially stored in the memory.

Ld (ivec-data) The 64-bit address following this instruction is loaded into the IVEC register, and NIPAR + = 5 pointing to the next instruction is executed.

Program control jmp (nipar-data) The 64-bit address following this instruction is loaded into the NIPAR register, and pointing to the next instruction is executed.

Arithmetic operation mac (m-reg) The multiplication result register indicated by the 2-bit m-reg code is the product and the sum (xd0 ^* yd0) + (xd1 ^* yd1) + (xd2 ^* yd2) + (xd
3 ^* yd3) to receive.

Macp (s-vec, d-vec) The multiplication result register indicated by the two bits of the 4-bit d-vec code is the product and the sum (xd0 ^* yd0) + (xd1 ^* yd1) + (xd2 ^*
yd2) + (xd3 ^* yd3). Every other bit of the d-vec code is selectively the result register address (a1)
And the remaining bits of the d-vec code select whether the address register a1 is incremented. The 8-bit s-vec is divided into four 2-bit groups, and whether data register xd0-xd3 is continuously read from memory at address (a0) and whether address register a0 is incremented Is specified. When reading or writing is designated, it is performed in parallel with the multiplication. The software must perform instruction processing pipeline alignment for each batch of data read from and stored in memory.

Reconfiguration reconf (ISA-vector) The instruction set architecture (ISA) 1 is de-contexted and the S machine reconfigures for the instruction set architecture (ISA) selected by the instruction set architecture (ISA) vector bit field in the instruction. Be composed.

Table 60 shows a pipeline convolution engine for XC4013 as a block configuration of ISA1.

[0292]

[Table 60]

[0293]

The present invention relates to a system and method for scalable, parallel, dynamic reconfiguration computation. The system comprises at least one S machine, a T machine corresponding to each S machine, and a universal interconnect matrix (G
PIM), a set of I / O T-machines, one or more I / O devices, and a master timebase device. In the preferred embodiment, the system includes multiple S machines. Each S machine includes an input and an output respectively coupled to the output and the input of the corresponding T machine. Each T machine includes a routing input and a routing output coupled to a general interconnect matrix (GPIM), and each input / output T machine includes them as well. The input / output T machine further
An input and an output are coupled to the input / output device. Finally, each S machine, T machine, and input / output T machine include a master timing input coupled to the timing output of the master time base device.

The meta-addressing system of the present invention provides bit addressing capabilities to processors in a network without requiring the processors themselves to perform processing-intensive address manipulation functions. Disclosed are separate processing and addressing machines that are optimized to perform their assigned functions. The processing machine executes the instructions, stores the data in the local memory, and retrieves the data from the local memory to determine when a remote operation is required. The addressing machine assembles a packet of data for transmission, determines the geographical or network address of the packet, and checks the address against incoming packets. In addition, the addressing machine can perform interrupt handling and other addressing operations.

In one embodiment, the T machine also provides the meta-addressing mechanism of the present invention. The metaaddress specifies the geographic location of the T machine in the system and specifies the location of the data in the local memory device. The local address of the meta-address is used to address each bit in the new device's memory, regardless of the device's actual memory size, as long as the device's addressable space is less than or equal to the number of bits in the local address. Used. Thus, a single meta-address can be used to address devices having different memory sizes and structures. Furthermore, because of the use of meta-addresses, the hardware within the multiprocessor parallel architecture does not need to guarantee coherency and consistency of the entire system.

The meta-address provides complete extensibility. When a new S machine or a new I / O device is added, a new geographic address is specified for this new device. In the present invention, the scalability may be irregular, and there is no requirement that a square expansion of the number of processors must be performed. Scalability is further enhanced by the ability to couple any number of addressing machines to each processing machine up to the available local memory bandwidth. This allows the system designer to arbitrarily specify the number of paths to each processing machine. With this flexibility, you can provide more bandwidth at higher levels of the system, and you can build a pyramidal processing architecture that is optimized to provide the most bandwidth for the most important functions of the system. it can.

As described above, according to the preferred embodiment, the T machine is an addressing machine that generates meta-addresses, handles interrupts, and queues messages. Thus, the S machine can concentrate its processing power only on the execution of program instructions, and can greatly optimize the overall efficiency of the multiprocessor parallel architecture of the present invention. The S-machine only needs to access the local memory component of the meta-address to find the desired data, and the geographic address is transparent to the S-machine. This addressing architecture works very well with distributed memory / distributed processor parallel computing systems. By choosing an architectural design that separates local memory, the hardware can operate independently and in parallel. According to the present invention, each S-machine can have a completely different reconfiguration instruction at runtime, even if all S-machines are directed in parallel. Also,
Not only may the instruction set architecture (ISA) implemented by the dynamically reconfigurable S-machine be different, but the actual hardware used to implement the S-machine may be optimized to perform certain tasks. It may be. Thus, the S machines in a single system may all operate at different rates, and each S machine can optimally perform its function while maximizing utilization of system resources.

In addition, a unique memory confirmation verifies that the correct geographic address is being transmitted, and does not provide confirmation of the local memory address. Further, this verification is performed by the addressing machine, not the processing machine. Since virtual addressing is not used,
No hardware / software interaction is required to translate virtual addresses to logical addresses. The address of the meta address is a physical address. Eliminating all such preventive and conservative functions greatly increases the overall system processing speed. Therefore,
In combination with a meta-addressing scheme, separating the "space" management of a computer system from the "time" management of a computer system provided by a separate processing machine to a separate addressing machine allows the A unique memory management and addressing system is provided. With the architecture of the present invention, the operation of the S-machines has great flexibility, and each S-machine can operate at its optimum rate while keeping the rate of the T-machine constant. Data communication throughout the system can reach farthest spaces and local instruction processing can be balanced in a very short time, thereby improving the approach to solving complex problems with highly parallel computer systems.

[Brief description of the drawings]

FIG. 1 shows a scalable, parallel,
FIG. 2 is a block diagram showing a preferred configuration example of a system for dynamic reconfiguration calculation.

FIG. 2 is a block diagram showing a preferred configuration example of an S machine of the present invention.

FIG. 3 is a schematic diagram of an exemplary program list including a reconfiguration instruction.

FIG. 4 is a flowchart of a prior art compilation operation performed during compilation of a series of program instructions.

FIG. 5 is a flowchart of a preferred compilation operation performed by a compiler for dynamic reconfiguration calculations.

FIG. 6 is a flowchart of a preferred compilation operation performed by a compiler for dynamic reconfiguration calculations.

FIG. 7 is a block diagram showing a preferred configuration example of a dynamic reconfiguration processing device (DRPU) of the present invention.

FIG. 8 is a block diagram showing a preferred configuration example of an instruction fetch unit (IFU) of the present invention.

FIG. 9 is a schematic diagram illustrating a preferred set of states supported by the instruction state sequencer (ISS) of the present invention.

FIG. 10 is a schematic diagram illustrating a preferred set of states supported by the interrupt logic of the present invention.

FIG. 11 is a block diagram showing a preferred configuration example of a data operation device (DOU) of the present invention.

FIG. 12 is a block diagram of a first exemplary embodiment of a data operation unit (DOU) configured to implement a general purpose external loop instruction set architecture (ISA).

FIG. 13 shows an inner loop instruction set architecture (IS
A) A data processing device (D
(OU) is a configuration block diagram of a second exemplary embodiment.

FIG. 14 is a block diagram showing a preferred configuration example of an address arithmetic unit (AOU) of the present invention.

FIG. 15 is a configuration block diagram of a first exemplary embodiment of an address arithmetic unit (AOU) configured to implement a general purpose external loop instruction set architecture (ISA).

FIG. 16 shows an inner loop instruction set architecture (IS
FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of an address arithmetic unit (AOU) configured to implement A).

FIG. 17 (a) shows an instruction fetch unit (IFU) for an outer loop instruction set architecture (ISA);
A data operation unit (DOU) and an address operation unit (AO)
And (b) shows an instruction fetch unit (IF) for an inner loop instruction set architecture (ISA).
FIG. 2 is a schematic diagram showing an exemplary assignment of reconfigurable hardware resources among a U), a data operation unit (DOU), and an address operation unit (AOU).

FIG. 18 is a block diagram illustrating a preferred configuration example of a T machine according to the present invention.

FIG. 19 is a block diagram showing a configuration example of a mutual coupling input / output device of the present invention.

FIG. 20 is a block diagram showing a preferred configuration example of an input / output T machine of the present invention.

FIG. 21 shows a general interconnect matrix (GPI) of the present invention.
It is a block diagram which shows the preferable example of a structure of M).

FIG. 22 is a flowchart of a preferred method for scalable, parallel, dynamic reconfiguration computation according to the present invention.

FIG. 23 is a schematic diagram showing a preferred configuration example of a data packet based on the present invention.

FIG. 24 is a flowchart of a preferred method for generating a data request according to the present invention.

FIG. 25 is a flowchart of a preferred method for sending data according to the present invention.

FIG. 26 is a flowchart of a preferred method for receiving data according to the present invention.

FIG. 27 is a block diagram showing a preferred configuration example of an interconnected input / output device that executes an interrupt processing operation according to the present invention.

FIG. 28 is a flowchart of a preferred method for handling interrupts according to the present invention.

[Explanation of symbols]

12 dynamic program processing machine (S machine) 14 addressing machine (T machine) 16 interconnection device (general-purpose interconnection matrix) 34 memory device, local memory (memory) 101 architecture description memory 106, 2200 interrupt logic 320 address decoder 1800 Data packet 1816 Geographic address 2208 Meta address 2208 Recognition device 2204 Comparator

Claims (15)

[Claims] A meta-addressing architecture for specifying a local memory destination for data packets for a network of dynamically re-programmable processing machines, each implementing an interrupt and storing a geographic address and a local address. A plurality of addressing machines having a unique geographical address for generating, transmitting, and waiting for each message, including a meta-address, wherein each of the plurality of addressing machines is coupled to at least one of the addressing machines and receives a local address. A plurality of dynamically reprogrammable processing machines for storing, retrieving, and processing data from a local memory device in response; a plurality of memory devices each associated with the dynamically reprogrammable processing machine; and the addressing machine. To the geo-address included in the meta-address. Meta address architecture for dynamic reconfiguration calculation comprising a mutual coupling device for routing data between said addressing machine one another depending on the address. 2. An address decoder for decoding at least one of the addressing machines into a geographical address and a local address, the dynamic reprogrammable processing machine; the local memory device; Coupled to an address decoder, retrieving meta-address information from the local memory in response to receipt of an unconditional instruction from the dynamic reprogrammable processing machine, assembling a data packet according to the retrieved meta-address, A controller for receiving a geographic address and a local address from a decoder and for transmitting a data packet to the dynamically reprogrammable processing machine in response to determining that the decoded geographic address corresponds to the associated geographic address. 2. A meta-addressing device for dynamic reconfiguration calculation according to claim 1. Architecture. 3. The system of claim 1, further comprising a plurality of architecture description memory devices coupled to said dynamically reprogrammable processing machine and storing said geographic address for said dynamically reprogrammable processing machine. Metaaddress architecture for dynamic reconstruction calculations. 4. The addressing machine further comprises an interrupt handler coupled to the input / output device, the interrupt handler comprising: a recognition device for identifying the interrupt request; and for verifying the validity of the interrupt request. And a comparator for comparing the identified interrupt request with a stored list of interrupt requests, and interrupt logic for processing the validated interrupt request according to the stored interrupt processing instructions. 2. A meta-address architecture for dynamic reconfiguration calculations according to item 2. 5. The meta-address architecture for dynamic reconfiguration calculations according to claim 1, wherein the meta-address is 80 bits wide, the geographic address is 16 bits wide, and the local address is 64 bits wide. 6. A parallel processor using a local addressing machine and a local processing machine coupled to a local memory, wherein the local addressing machine is identified by a unique geographic identification and interconnected by an interconnecting device. A method for processing instructions in an architecture, comprising: receiving a program instruction; determining whether the received program instruction requires a remote operation; An addressing method comprising: storing remote component information in said local memory; and issuing an unconditional instruction to said local addressing machine to initiate a remote operation. 7. The local addressing machine receives the unconditional instructions from the local processing machine, and stores the remote component information including a local geographic address, a remote geographic address, and a remote local memory address into the local addressing machine. Retrieving from a memory, generating a meta-address according to the retrieved remote component information, generating a data packet according to the generated meta-address, and sending the data packet to the interconnection device. 7. The method according to claim 6, wherein the method is performed. 8. An addressing method for addressing a memory in a parallel computing environment in which a local processing device is coupled to a local memory, a local address machine, and an interconnecting device, the local address machine comprising: Receiving the packet; decoding the data packet into a geographical address and a local address; comparing the geographical address with the associated geographical address; and transmitting the data packet to the local processor according to the geographical address matching the associated geographical address. Transmitting,
Addressing method to perform. 9. The method of claim 8, wherein transmitting a data packet to the local processor includes storing the data packet in a queue for processing by the local processor. 10. Receiving data from the local processor; retrieving remote operation data from the local memory in accordance with the received data; generating a meta-address from the retrieved data; Generating a data packet in response to: transmitting the data packet to the interconnection device;
9. The addressing method according to claim 8, comprising: 11. The addressing method of claim 10, wherein retrieving the remote computation data comprises retrieving a remote geographic address and a remote local memory address. 12. The method of claim 11, further comprising retrieving a source geographic address from said local memory. 13. The addressing of claim 12, further comprising using an architecture description memory coupled to each processor and storing a geographic address for the coupled local processor, and retrieving a source geographic address from the architecture description memory. Method. 14. A parallel processor using a local addressing machine and a local processing machine coupled to a local memory, wherein the local addressing machine is identified by a unique geographic identification and interconnected by an interconnecting device. A method for processing instructions in an architecture, wherein the local addressing machine receives an unconditional instruction from the local processing machine, and stores a local geographic address, a remote geographic address, and a remote local memory address. Retrieving the contained remote component information from the local memory; generating a meta-address according to the retrieved remote component information; generating a data packet according to the generated meta-address; Stage to send to interconnection device Addressing how to and, the provided. 15. An addressing method for addressing memory in a parallel computing environment in which a local processing unit is coupled to a local memory, a local address machine, and an interconnecting device, the local address machine comprising: Receiving data from a processor; retrieving remote operation data from the local memory according to the received data; generating a meta-address from the retrieved data; and generating a data packet according to the generated meta-address. And transmitting the data packet to the interconnection device.