JP2000242508A - Interruption arbitrating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the alteration of the interruption arbitrating circuit against the variation of the number of interruption request sources by inputting an initial value load signal to a count part when the count value matches a maximum count value. SOLUTION: The counter part 20 reads in an initial value set by a counter initial value setting part 21 with an initial value load signal outputted from a comparator part 23. Then the counter part 20 counts the clock input to its clock input terminal to increase in value. The output of the counter part 20 is taken out as a counter value output and inputted to the comparator part 23, which compares the count value with the maximum count set value from a maximum count value setting part 22. When the counter value matches the set value, the comparator part 23 outputs the initial value load signal to the counter part 20. Consequently, the counter increases in value repeatedly from the initial value (e.g. 0) to the maximum set value (e.g. 5).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interrupt arbitration circuit, and more particularly to an interrupt arbitration circuit using a programmable counter.

[0002]

2. Description of the Related Art In a computer system including a personal computer, a microprocessor or C
Many devices are connected to a PU (Central Processing Unit) via a bus. An arbiter (arbiter) is used in order to efficiently arbitrate requests from many of these devices to the processor and perform a smooth operation.

Conventional examples of such arbitration circuits or interrupt arbitration circuits are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 9-31594 and
It is disclosed in Japanese Patent Application Laid-Open No. 2-297944.

That is, the interrupt request source in which the interrupt factor has occurred is determined by the number assigned to itself among the unique numbers given to the plurality of interrupt request sources, and the count value output from the interrupt arbitration counter of the interrupt control unit. When they match, an interrupt request signal is output to the interrupt control unit. Upon detecting the interrupt request signal, the interrupt request source determines the interrupt request source from the value of the interrupt arbitration counter.

Alternatively, an interrupt arbitration counter is provided for each of the interrupt control unit and the interrupt request source, and a clock and a reset signal are output from the interrupt control unit to the interrupt request source.
All counters are incremented and initialized at the same timing. When the unique number assigned to the interrupt request source matches the counter value, the interrupt request source that has generated the interrupt factor outputs an interrupt request signal to the interrupt control unit, and causes the interrupt control unit to determine the interrupt request source. When an interrupt arbitration counter is used, such an arbitration method is generally used.

FIG. 8 shows a configuration diagram (A) of a conventional interrupt arbitration counter and an operation explanatory diagram (B) thereof. FIG. 8 (A)
As shown in (1), it is composed of an interrupt controller 80 and a plurality (n) of interrupt request sources 83a to 83n. The interrupt control unit 80 includes an interrupt arbitration counter 81 and an interrupt request reception 82. Interrupt control unit 80
The interrupt request sources 83a to 83n are connected by one interrupt request signal. Each of the plurality of interrupt request sources 83a to 83n has an individual number uniquely assigned to each request source. As shown in FIG. 8A, one interrupt request signal is transmitted to a plurality of interrupt request sources 8.
In the case of sharing by 3a to 83n, it is necessary to arbitrate and avoid conflict of interrupt requests. For this purpose, the timing of outputting the interrupt request signal is time-divided, and interrupt requests are sequentially received by the interrupt request sources 83a to 83n at the reception 82.

[0007] As shown in FIG.
The 0 interrupt arbitration counter 81 counts up to 0, 1, 2,... N. When it reaches n, it returns to 0 again and the count-up is repeated.

Next, referring to FIGS. 9A and 9B,
The operation when there are six interrupt request sources 83a to 83f will be described. FIG. 9B is a timing chart of the interrupt request signal output of FIG. 9A including the interrupt request sources 83a to 83f of the individual (or identification) numbers 0 to 5.
Shown in Interrupt request source 83 where the interrupt factor occurred
Compares the count value output from the interrupt arbitration counter 81 provided in the interrupt control unit 80 with the individual number given to itself. An interrupt request signal is output at the timing when the counter value matches the individual number ((a) and (b) in the timing chart of FIG. 9B).
reference).

FIGS. 10A and 10B show a decrease in the number of interrupt request sources 83 and a decrease in interrupt arbitration capability due to a change in the system configuration. In the case of FIG. 9, the number of interrupt request sources is 83
In FIG. 10, the number of interrupt sources has been reduced to four, 83a to 83d. The arbitration counter 81 increments 0 to 5 (counter up).
It is configured to be.

However, in the case of FIG. 10, the fact that 0 to 3 is sufficient and the counter times of 4 and 5 are wasted is shown in FIG.
This is shown in the timing chart of FIG. That is, in the case of FIG. 10, even if the interrupt arbitration counter 81 counts 4 and 5, since there is no individual number of the interrupt request source corresponding to the count value, it becomes a useless arbitration section, and the interrupt is performed accordingly. This means that the arbitration capability of the control unit 80 has decreased.

[0011]

According to the above-described conventional interrupt arbitration circuit, when the number of interrupt request sources is changed (decreased) due to a change in the system configuration or the like, a wasteful counter section is generated in the interrupt arbitration counter, and the arbitration capability is increased. Leads to a decrease in In other words, there has been a problem that the arbitration efficiency changes depending on the number of interrupt request sources or the system configuration.

Further, in the conventional interrupt arbitration circuit, another problem occurs when the interrupt request sources are divided into a plurality of groups. That is, if the interrupt request source is divided into a plurality of groups according to the priority of the interrupt request, and a unique individual number is given to each group, the arbitration counter simply increments, so that the arbitration counter can be operated for each group. Because it is impossible, it cannot be counted individually for each group. Even in this case, the system configuration changes,
When the number of interrupt request sources decreases, the arbitration efficiency decreases because the interrupt arbitration counter increments to an unnecessary count value.

Further, when there is a change in the system configuration in which the number of interrupt request sources increases, arbitration cannot be performed.

Accordingly, an object of the present invention is to provide an interrupt which does not cause arbitration failure or decrease in arbitration efficiency due to an increase or decrease in the number of interrupt request sources due to a change in the system configuration when the interrupt request sources are grouped. An arbitration circuit is provided.

Another object of the present invention is to provide an interrupt arbitration circuit capable of suppressing a change in the interrupt arbitration circuit in response to a change in the number of interrupt request sources.

[0016]

In order to solve the above-mentioned problems, an interrupt arbitration circuit according to the present invention employs the following characteristic configuration.

(1) In an interrupt arbitration circuit having an interrupt control unit including an interrupt arbitration counter for arbitrating interrupt requests from a plurality of interrupt request sources, a counter unit for counting clock inputs as the interrupt arbitration counter; A counter initial value setting unit for setting an initial value of the counter unit, a maximum count value setting unit for setting a maximum count value of the counter unit, and comparing the count value of the counter unit with the maximum count value. An interrupt arbitration circuit using a programmable interrupt arbitration counter including a comparator unit for inputting an initial value load signal to the counter unit.

(2) The interrupt arbitration circuit according to (1), wherein the plurality of interrupt request sources are grouped into two or more groups.

(3) A plurality of the counter initial value setting section and the maximum count value setting section of the programmable interrupt arbitration counter are provided according to the number of groups of the interrupt request source, and the interrupt of (2) is switched by a selector. Arbitration circuit.

(4) The interrupt arbitration circuit according to (2), wherein the grouping of the interrupt request sources is performed according to the priority.

(5) The interrupt arbitration circuit according to (3), wherein the count values of the interrupt request sources of the plurality of groups can be arbitrarily set by the counter initial value setting unit and the maximum count value setting unit.

(6) The interrupt arbitration circuit according to the above (3), wherein the control of the selector is performed according to the upper bit of the count value from the counter section.

(7) The interrupt arbitration circuit according to (1), wherein the counter section loads a set value from the counter initial value setting section every time the comparator section outputs an initial value load signal.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of an interrupt arbitration circuit according to the present invention; FIG.

First, a description will be given with reference to FIG. FIG.
FIG. 2A is a block diagram showing the basic principle of the interrupt arbitration circuit according to the present invention. This interrupt arbitration circuit includes an interrupt control unit 10 and a plurality (four in this case) of interrupt request sources 13a to 13d. The interrupt control unit 10 includes a programmable interrupt arbitration counter 11 and an interrupt request reception 12. Each of the interrupt request sources 13a to 13d, the programmable interrupt arbitration counter 11 and the interrupt request reception 12 are interconnected by one signal line.

The operation of the interrupt arbitration circuit shown in FIG.
As shown in the timing chart of FIG. 9B, it is the same as the conventional interrupt arbitration circuit of FIG. That is, for example, when an interrupt factor occurs at the interrupt request source 13d of the individual number 3, the programmable interrupt control counter 11 is incremented, and when the count value becomes 3, an interrupt request signal is generated. It should be noted here that the interrupt arbitration counter 11 is programmable. This programmable interrupt arbitration counter 11 has a system configuration
That is, the counter initial value (for example, 0) and the maximum value (for example, 3) can be freely programmed from the outside according to the number of interrupt request sources 13a to 13d.

FIG. 2 is a detailed configuration (A) and an operation timing chart (B) of the programmable interrupt arbitration counter 11 used in the interrupt control section 10 of the interrupt arbitration circuit of FIG. As shown in the block diagram of FIG. 2A, the programmable interrupt arbitration counter 11 includes a counter section 20, a counter initial value setting section 21, a maximum count value setting section 22, and a comparator section 23.

The counter section 20 reads the initial value set by the counter initial value setting section 21 in response to the initial value load signal output from the comparator section 23. Thereafter, the counter unit 20 counts the clock input input to the clock input terminal and increments (counts up).
I do. The output of the counter section 20 is taken out as a count value output and input to the comparator section 23. The comparator section 23 compares the count value from the counter section 20 with the set value from the maximum count value setting section 22. When the counter value matches the set value, the comparator unit 23 outputs the above-described initial value load signal to the counter unit 20. As a result, as shown in FIG. 2B, the value is repeatedly incremented from an initial value (for example, 0) to a maximum set value (for example, 5).

As can be easily understood from FIGS. 1 and 2,
The interrupt arbitration circuit according to the present invention can easily cope with a change in the system configuration. For example, in the example of the interrupt arbitration circuit of FIG. 1A, when there is a change in the system configuration to which the interrupt request source 13e of the individual number “4” is added, the maximum count value of the programmable interrupt arbitration counter 11 is “4”. ". Further, even when the interrupt request sources 13f, 13g... Of the individual numbers "5", "6"... Are added, the maximum count value of the programmable interrupt arbitration counter 11 is set to "5", "6". Is enough.

On the other hand, a case where the number of interrupt request sources 13 decreases will be described. For example, when the interrupt request source 13d is removed from the system, the maximum count value of the programmable interrupt arbitration counter 11 is set to “2”.
Conversely, when the interrupt request source 13a is removed,
If the initial count is set to “1” while the maximum count value remains “3”, the other interrupt request sources 13 b to 13
The operation is performed without changing the individual numbers “1” to “3” of d.

Next, a method of programming the count value of the programmable interrupt arbitration counter 11 of FIG. 2 will be described. The following two methods can be considered for this programming method. (1) A method of holding a count value in a memory or a register from a terminal device or the like via a data bus. (2) A method of using an external port to hold a count value by setting a switch or the like.

Next, a case where interrupt request sources are grouped into a plurality of groups according to the priority of the interrupt request and the like will be described with reference to FIG. FIG. 3 shows an example in which the programmable interrupt arbitration counters 11 ′ are grouped into two groups of a group A and a group B. The programmable interrupt arbitration counter 11 'includes a counter initial value setting unit 21a and a maximum count value setting unit 22a for the counter unit 20' group A,
Group B counter initial value setting unit 21b, maximum count value setting unit 22b, both counter initial value setting units 21
The selector 30 includes a selector 30 that switches between the maximum count value settings 22a and 22b, and a comparator unit 23 ′.

Next, the operation of the programmable interrupt arbitration counter 11 'of FIG. 3 will be described. The maximum count value setting units 22a and 22b set the maximum count numbers of the groups A and B, respectively. The set values a and b, which are the maximum count values for both groups A and B, are determined by the select 31 using the most significant bit of the count value as the select signal, and the maximum count set values a and b of either the group A or the group B are changed. It is selected and input to the comparator unit 23 '. The count value of the counter unit 20 'is compared with the set value a or b by the comparator value 23'.

Similarly, the counter initial value setting sections 21a, 21a
1b sets a set value c or a set value d which is an initial value of the interrupt arbitration counter for group A and group B, respectively. These set values c and d are similarly calculated by the comparator 2
The data is input to the counter unit 20 'via the selector 30 controlled by the most significant bit of 3'.

The interrupt arbitration counter outputs, for example, an initial value load signal, which is an output from the comparator unit 23 ', which is set by the selector 30 among the counter initial value setting units 21a, 21b. Load (input) according to. The counter section 20 'to which the set value c has been input is incremented from the set value c by the clock input. When the count value of the counter unit 20 'is incremented by the set value a set by the maximum count value setting unit 22a of the group A for the interrupt request source group A of the set value c, the initial value generated by the comparator unit 23' By the load signal, the second
, The counter initial value (set value d) set for the interrupt request source group B is loaded, and increment is started by clock input.

Next, when the count value of the counter section 20 'is incremented to the set value b, the comparator section 2'
In response to the 3 'initial value load signal, the counter unit 20' loads the set value c again and continues incrementing. Therefore, the counter unit 20 'repeats counting of c to a and d to b.

When the number of interrupt request sources is further divided into groups, the upper bits of the arbitration counter are selected as select signals for the counter initial value and the maximum count value for each group. Counter part 2
When 0 'is incremented to the maximum count value set for a certain group, the count initial value for the next group is loaded. While the counter unit 20 'is incrementing to the maximum count value for one group, the selector selects the initial counter value set for the next group. When the counter value of the counter section 20 'reaches the maximum count value set for the group, the counter initial value for the next group is loaded. When the maximum count value set for the last group is reached, the counter initial value for the first group is loaded and incremented.

Next, FIG. 4 illustrates the operation of a system having three interrupt request sources of group A and group B, respectively. Here, the individual numbers “00”, “01”, and “02” are assigned to the interrupt request sources 13a, 13b, and 13c belonging to the group A, respectively.
It is assumed that the request sources 13d, 13e, and 13f belonging to the group B are assigned the individual numbers "10", "11", and "12", respectively. The most significant bits 0 and 1 of the count value of the counter section are select signals for selecting the maximum count value for comparing the count values in the comparator section and for selecting the counter initial value to be loaded into the counter section.

In FIG. 4, the programmable interrupt arbitration counter 11 'of the interrupt control unit 10' increments the counter initial value "00" of the first interrupt requesting group A (13a to 13c) from "00" to "01" and "02". I do. At this time, the counter initial value “10” set for the second interrupt request source group B (13d to 13f) is selected as the counter initial value. Since the maximum count value for the first interrupt request source group A is "02", the programmable interrupt arbitration counter 11 '
Loads the counter initial value “10” of the second interrupt request source group B after the count value “02”, and sets “1”.
1 "and" 12 "are incremented. At this time, as the counter initial value, the counter initial value “00” already set for the first interrupt request source group has been selected.
When the count value of the arbitration counter 11 ′ reaches “12”, the maximum count value of the second interrupt request source group is “12”, so that the counter initial value of the first interrupt request source group A is “00”. And load "0
1 "and" 02 ". Hereinafter, the arbitration counter 11 'repeats the above operation.

Next, an example of the operation of the programmable interrupt arbitration counter 11 'when the interrupt request source group is different from the above example will be described with reference to FIGS.

FIG. 5 shows an example in the case of two groups, Group A and Group B, each having four interrupt request sources. At this time, the interrupt request source of group A is “0”.
Individual numbers 0, 01, 02, and 03 are assigned, and the interrupt request source of group B is 10
Individual numbers “11”, “12”, and “13” are assigned. Therefore, the arbitration counter 11 ′ has “00”,
After counting "01", "02" and "03", "1"
It shows a situation of incrementing to “0”, “11”, “12”, and “13”.

FIG. 6 shows a group A having an interrupt request source number 5 and individual numbers "00", "01", "02", "03", and "04", and an interrupt request source number 2 and an individual number "5". 1
This is the case of a system consisting of two groups of “2” and “13”.

FIG. 7 shows a group A having individual numbers "03", "04", and "05" with three interrupt request sources, and individual numbers "10", "11", and "1" with four interrupt request sources.
Group B of “2” and “13” and Group C of individual numbers “22”, “23” and “24” with three interrupt request sources
And the individual numbers "31" and "3"
This is the case of a system composed of four groups, ie, group D of “2”, “33”, “34”, and “35”. in this case,
The most significant bits 0 to 3 are select signals for the maximum count value and the counter initial value.

The configuration and operation of the preferred embodiment of the interrupt arbitration circuit according to the present invention have been described in detail. However, the present invention should not be limited only to such specific examples, and various modifications and alterations can be made according to specific applications without departing from the spirit of the present invention. I can understand.

[0045]

As is apparent from the above description, according to the interrupt arbitration circuit of the present invention, the following various remarkable effects not obtained in the prior art can be obtained.

That is, in the conventional arbitration circuit, arbitration cannot be performed when the number of interrupt requests increases due to a change in the system configuration. Conversely, when the number of interrupt requests decreases, a useless count section occurs as described above.

On the other hand, according to the present invention, independent arbitration can be performed for each group of interrupt request sources that are grouped. The reason is that the initial value and the maximum count of the counter can be set for each group, and the set value can be changed according to the system change.

Further, even if the number of interrupt request sources grouped is changed, it is possible to prevent the arbitration capability from lowering. The reason is that the initial value and the count number of the counter can be set for each group, so that useless counting time can be omitted.

Further, the change of the arbitration circuit accompanying the system change can be suppressed as much as possible. The reason is that since the count start value and the maximum count value of the arbitration counter can be set for each group, the influence of the system configuration change on the arbitration counter configuration is relatively small.

[Brief description of the drawings]

FIG. 1 shows the principle of an interrupt arbitration circuit according to the present invention;
(A) is a block diagram, and (B) is an operation timing chart.

2 shows a programmable interrupt arbitration counter included in the interrupt control unit shown in FIG. 1, wherein FIG. 2 (A) is a block diagram and FIG. 2 (B) is an operation timing chart.

FIG. 3 is a block diagram of a programmable interrupt arbitration counter of the interrupt arbitration circuit according to the present invention when interrupt request sources are grouped into a plurality of groups.

FIG. 4 is a block diagram of an interrupt arbitration circuit according to the present invention that uses the programmable interrupt arbitration counter shown in FIG.

FIG. 5 is an operation timing chart of the arbitration counter in the case of two groups A and B each having four interrupt request sources.

FIG. 6 is an operation timing chart of the arbitration counter in the case of two groups A and B in which the numbers of interrupt request sources are 5 and 2, respectively.

FIG. 7 shows that the number of interrupt request sources is 4, 4, 3, and 5, respectively.
5 is an operation timing chart of an arbitration counter in a case where the arbitration counter includes two groups A, B, C and D.

FIG. 8 is a configuration (A) of a conventional interrupt arbitration circuit and an operation timing chart (B) of a counter.

9 is an operation explanatory diagram of the conventional interrupt arbitration circuit shown in FIG.

10 is a diagram for explaining a problem of the conventional interrupt arbitration circuit shown in FIG.

[Explanation of symbols]

 10, 10 'Interrupt control unit 11, 11' Programmable interrupt arbitration counter 13 Interrupt request source 20, 20 'Counter unit 21, 21a, 21b Counter initial value setting unit 22, 22a, 22b Maximum count value setting unit 23, 23' Comparator Unit 30, 31 Selector

Claims (7)

[Claims] An interrupt arbitration circuit having an interrupt control unit including an interrupt arbitration counter for arbitrating interrupt requests from a plurality of interrupt request sources, wherein the interrupt arbitration counter counts a clock input; A counter initial value setting unit for setting an initial value of the counter unit, a maximum count value setting unit for setting a maximum count value of the counter unit, and comparing the count value of the counter unit with the maximum count value. An interrupt arbitration circuit using a programmable interrupt arbitration counter including a comparator unit for inputting an initial value load signal to the counter unit. 2. The interrupt arbitration circuit according to claim 1, wherein said plurality of interrupt request sources are grouped into two or more groups. 3. The programmable interrupt arbitration counter according to claim 1, wherein a plurality of said counter initial value setting units and a maximum count value setting unit are provided in accordance with the number of groups of said interrupt request source, and are switched by a selector. 3. The interrupt arbitration circuit according to 2. 4. The interrupt arbitration circuit according to claim 2, wherein said grouping of interrupt request sources is performed according to priority. 5. The interrupt arbitration according to claim 3, wherein the count values of the interrupt request sources of the plurality of groups can be arbitrarily set by the counter initial value setting unit and the maximum count value setting unit. circuit. 6. The interrupt arbitration circuit according to claim 3, wherein control of said selector is performed in accordance with an upper bit of a count value from said counter section. 7. The interrupt arbitration according to claim 1, wherein the counter section loads a set value from the counter initial value setting section every time the comparator section outputs an initial value load signal. circuit.