JP2000235519A - Cache system and cache processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize both of high speed data access and a high cache bit rate at high levels by improving the storing performance of a cache line having a high bit rate and the using efficiency of a cache memory space. SOLUTION: In a cache part obtained by combining an FSA type cache and a cache such as a DM type cache other than the FSA type, tag comparison is simultaneously executed by both the caches. When count values related to the numbers of cache hits of respective cache lines of the FSA type cache are stored and a certain cache line in the FSA type e.g. is hit, '1' is added to the count value of the cache line, and when both cache tables are mis-hit, '1' is simultaneously subtracted from the count values of all cache lines. Since the data of respective caches are managed/transferred by using the count values in accordance with respective cases, the overlap of data in both the caches is removed, a cache line of a high bit rate is stored in the FSA type cache and the FSA type cache of a high speed and a high bit rate can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an MPU (Micr
oProcessor Unit), CPU (Cent
The present invention relates to a cache system and a cache processing method which are applied to a data processing unit such as a ral processing unit (RL) and reduce an access time to an external memory such as a main memory.
A cache line other than the FSA (full set associative) system (a direct mapping system cache, a two-way associative system cache, a four-way associative system cache, an eight-way associative system cache, etc.) can hold a frequently used cache line. The present invention relates to a cache system and a cache processing method for improving a cache hit rate by adding an FSA cache.

[0002]

2. Description of the Related Art A cache (also referred to as a cache memory) is widely used in order to reduce the access time when an MPU, CPU, or the like, which executes data processing at high speed, accesses an external memory such as a main memory having a low data processing speed. Used. In particular, a hierarchical cache composed of a primary cache and a secondary cache is frequently used in order to increase the execution speed of programs such as MPUs and CPUs and to improve the throughput of a system including the MPUs and CPUs.
The cache memory generally includes a cache table that holds a plurality of tags and data corresponding to each tag, and tags separated from input data are compared with tags stored in the cache table. When the tags match, data corresponding to the matching tag is selected from the cache table and supplied to the MPU, CPU, and the like.
By such processing, the number of accesses to an external memory such as a main memory having a low data processing speed is suppressed, and the MP
High-speed data processing of a data processing unit such as U and CPU is realized.

As such caches, an FSA cache and a direct mapping cache are well known. Although the direct mapping cache can realize high-speed access with a small circuit scale, the cache hit rate is liable to be deteriorated. on the other hand,
Although the FSA cache has large power consumption and a complicated circuit scale, it can hold a cache line with a high hit rate. In addition, as a cache other than the FSA system having a function similar to the direct mapping system cache, a 2-way associative cache, a 4-way associative cache,
8-way associative caches are also well known.

FIG. 10 is a block diagram showing a typical conventional direct mapping cache. FIG.
The direct mapping cache includes a cache table 801 storing a plurality of tags and data corresponding to these tags, a comparator 802, an AND gate 803, and a data selector 804.
Each cache line of the cache table 801 has
An activation bit (valid bit) for indicating whether the cache line is active or inactive is provided.
The activation bit “1” indicates that the cache line is active, and the activation bit “0” indicates that the cache line is inactive. In the upper part of FIG. 10, "0000040" (1
Hexadecimal) is shown. The input address data includes a tag, an index, and an offset. For example, in the case of the input address data “0000040”, the tag is “00000” (for example, the first five digits of hexadecimal input address data), and the index Is "04"
(For example, the next two digits of hexadecimal input address data),
The offset is "0" (for example, the last digit of hexadecimal input address data).

FIG. 11 is a schematic diagram showing an example of a program realized by the CPU. The program in FIG. 11 includes a plurality of instructions (1), (2),... To be executed. In the main memory, a large number of instructions are stored in advance at corresponding addresses, and when the program in FIG. 11 is executed by the CPU, the CPU first inputs an input address corresponding to the first instruction (1) of the program. Refers to data (given from the program counter). The input address data “00000040” corresponding to the first instruction (1) indicates that this instruction (1) is stored in advance at the address “00000040” of the main memory. For the first instruction (1), FIG.
In the direct mapping cache 802, the tag “0000” extracted from the input address data “00000040” matches the tag stored in the cache line corresponding to the index “04” of the cache table 801 in FIG. Is determined. If they match, the data corresponding to the matching tag is read from the cache table 801 of the direct mapping cache and sent to the CPU (instruction decoder). If they do not match, the CPU accesses the main memory and sets the address “0” of the main memory.
This instruction (1) is fetched from "0000040".
In the case of a mismatch, the cache line corresponding to the index “04” is rewritten. That is, the data of the cache line corresponding to the index “04” is rewritten with the data fetched from the main memory,
The tag of the cache line is input address data "0
00000040 "is replaced with a tag" 00000 ". After that, the same processing is performed for the following instructions (2), (3),. By using such a direct mapping cache, the number of accesses to the main memory that requires a long access time by the CPU is reduced, and high-speed program execution (cache processing) by the CPU is realized.

FIGS. 12A and 12B are schematic diagrams showing an example of a state change of the cache table 801 of the direct mapping cache shown in FIG. 10 when the CPU executes the program shown in FIG. FIG. 12A shows a state immediately after the execution of the instruction (1), and FIG. 12B shows a state immediately after the execution of the instruction (5). Referring to FIG. 12A, immediately after the execution of the instruction (1), the cache line corresponding to the index “04” of the cache table 801 has the input address data “00000”.
040 "and the tag" 0000 "
0000 ”is stored. FIG.
Referring to FIG. 2B, immediately after the execution of the instruction (5), the tag “0” corresponding to the input address data “0000001040” is stored in the same cache line corresponding to the index “04” of the cache table 801.
0001 ”and data corresponding to the tag“ 00001 ”.

FIGS. 13 (a) and 13 (b) show that the CPU using this direct mapping cache is
FIG. 13A is a schematic diagram illustrating an access time when one program is executed twice, FIG. 13A illustrates a case of executing a first program, and FIG. 13B illustrates a case of executing a second program. . In the following description of the program execution time, the length of the data storage area of each cache line of the direct mapping cache is 4 words (16 bytes), and the length of each instruction of the program in FIG. 11 is 1 word (4 bytes). (That is, four instructions are stored in the data storage area of each cache line of the direct mapping cache). The access time required to fetch data (instruction) from main memory is 10 words in the first word.
Assume 0 ns and 30 ns each for each of the following three words. Therefore, the access time required to fetch four words of data (four instructions) from the main memory and store these data in one cache line of the direct mapping cache is 100 + 30 +
30 + 30 = 190 ns. Assuming that it takes 10 ns for the CPU to read and execute the instruction immediately after being stored in the cache line, four words of data (4
Access times required to execute the first instruction (1) stored in the direct mapping cache and fetching these instructions from the main memory are 190 + 10 = 200 ns.

In the initialization, all cache lines of the direct mapping cache are deactivated. That is, the activation bits of all the cache lines are reset to “0”. Immediately after this initialization, the activation bits V are all "0", so that there is substantially no data in the direct mapping cache. For this reason, the CPU transmits necessary data (commands (1) to (1) corresponding to the first index “04”).
(4)) is fetched from the main memory, and the fetched instructions (1) to (4) are written to the cache line corresponding to the index "04" of the direct mapping cache. By this data writing, the cache line corresponding to the index “04” is activated. That is, the activation bit V of this cache line is set to "1" (see FIG. 10). Then, C
The PU reads the instruction (1) from this cache line and executes it. In the first program execution shown in FIG. 13A, the CPU is executed after the startup routine.
100 + 30 + 30 to execute the first instruction (1)
+ 30 + 10 = 200 ns is required, and execution of the following instructions (2), (3), and (4) requires 10 ns each (230 ns). Thereafter, the CPU proceeds to address “0”.
Four instructions corresponding to “0000103” through “0000103C” are similarly executed (200 + 10 + 10 + 1).
0 = 230 ns).

Thereafter, when the CPU attempts to execute the instruction (5) corresponding to the above-mentioned index "04", the index "0" of the direct mapping cache is used.
In the cache line corresponding to "4", the instruction (1) has already been set.
And the tag “00000” corresponding to the instruction (1) are stored, so that the cache line corresponding to the index “04” has a mishit (“00001” ≠ “0”).
0000 ") occurs. Therefore, the CPU issues the instruction (5)
Is fetched from the main memory, and the instruction (5) and the corresponding tag “00001” are stored in the cache line corresponding to the index “04”. Due to this mishit, the execution of the instruction (5) is also 100 + 30 + 30 + 30 +
It takes 10 = 200 ns. Execution of the following three instructions also takes 10 ns each. Therefore, the total program execution time in the first program execution is 230 × 3 = 69.
0 ns.

At the time when the first program execution in FIG. 13A is completed, the cache line corresponding to the index "04" has the tag "" corresponding to the instruction (5) as shown in FIG. 00001 ”is stored.
Therefore, when the CPU attempts to execute the instruction (1) corresponding to the above-mentioned index “04” in the second program execution, the cache line corresponding to this index “04” is mis-hit (“00000” ≠) again.
"00001") occurs. Therefore, the CPU fetches the instruction (1) from the main memory again, and it takes 200 ns to execute the instruction (1) in the second program execution. Execution of the following three instructions also takes 10 ns each (230 ns). Thereafter, the CPU changes the address “00001030” to “0”.
000103C ”are executed using the cache data already stored in the cache line corresponding to the index“ 03 ”of the direct mapping cache (10 + 10 + 10 + 10 = 4).
0 ns). Thereafter, in the second program execution, the instruction (5) corresponding to the above-mentioned index “04” is
When U tries to execute, a similar mishit (“00001” ≠ “00000”) occurs again in the cache line corresponding to the index “04” (200).
ns). Each of the following three instructions is similarly executed for 10 ns.
This (230 ns). Therefore, the program execution time in the second program execution is 230 + 40 + 230
= 500 ns. Therefore, the program in FIG.
The total program execution time (access time) required to execute the program twice is 690 + 500 = 1190 ns.

As described above, the direct mapping cache has the advantage that high-speed access can be realized with a small circuit scale, but has the disadvantage that cache misses (miss hits) occur easily and repeatedly. Access to the main memory due to a mishit is, for example, 200 ns
Therefore, there is a problem that the program execution time of the CPU (access time for executing the program) becomes long.

In order to improve the cache hit rate and reduce the memory access time and the program execution time,
Hierarchical caches composed of a primary cache and a secondary cache have been widely used. For example, in the conventional example of the "cache memory control method" disclosed in Japanese Patent Application Laid-Open No. 61-241853,
And a main memory, and a secondary cache is provided between the primary cache and the main memory. When a cache hit occurs in the primary cache, necessary data stored in the primary cache is provided to the CPU as cache data. The primary cache misses,
When a cache hit occurs in the secondary cache, necessary data stored in the secondary cache is transferred to the primary cache, and then given to the CPU. In this case, if there is no inactive (unused) cache line capable of storing necessary data transferred from the secondary cache in the primary cache, the data stored in one cache line of the primary cache is replaced with the primary cache. And transferred to one cache line of the secondary cache. In this case, if there is no inactive (unused) cache line in the secondary cache that can store the data deleted from the primary cache, the data deleted from the primary cache can be stored.
Data stored in one cache line of the secondary cache is deleted from the secondary cache. If both the primary and secondary caches miss,
The required data is fetched from main memory and written to the primary cache. In a normal hierarchical cache, fetched data is written to both the primary cache and the secondary cache, but in this conventional example, it is not written to the secondary cache but is written only to the primary cache. By such an operation, the cache hit rate of the secondary cache is improved.

In the conventional example of the "hierarchical cache system" disclosed in Japanese Patent Laid-Open No. 5-73415,
Determines whether the required data exists in the primary cache or the secondary cache. If the primary cache misses and the secondary cache hits, the data hit in the secondary cache is transferred to the primary cache.
In this transfer, data to be removed from the primary cache is transferred to the secondary cache.

Further, in a conventional example of the "cache memory system" disclosed in Japanese Patent Application Laid-Open No. 6-012323,
The direct mapping cache is used for the primary cache, and the FSA cache is used for the secondary cache. Tag comparison for determining a cache hit is performed simultaneously in the primary cache and the secondary cache. Data fetched from the main memory is written to both the primary cache and the secondary cache in the same manner as in the conventional hierarchical cache technology. In this conventional example, a counter for counting the number of accesses (cache hits) to each cache line of the secondary cache (FSA cache) is proposed, and the count value of the counter of one cache line exceeds a predetermined number. If so, the cache line is loaded into the primary cache (direct mapping cache) for later access.

In a conventional example of a "data processing system having a cache memory of a plurality of levels" disclosed in Japanese Patent Application Laid-Open No. 6-250926, if the primary cache misses, the secondary cache is not accessed. Done. When the secondary cache hits the cache, the necessary data stored in the secondary cache is transferred to the primary cache (inactivated in the secondary cache) and given to the CPU. If there is a miss in the secondary cache, the main memory is accessed,
The required data is fetched from main memory. In one embodiment of this conventional example, if there is sufficient memory space in the primary cache, the data fetched from the main memory is registered only in the primary cache (not registered in the secondary cache), and If there is no sufficient memory space, the data fetched from the main memory is registered only in the secondary cache (not registered in the primary cache). In another embodiment, data fetched from main memory is registered directly in the primary cache only (not in the secondary cache). When data that cannot be registered in the primary cache occurs in direct data registration from the main memory to the primary cache, the data is transferred from the primary cache and registered in the secondary cache.

[0016]

As described above, in the conventional direct mapping type cache, it is impossible to hold a cache line having a high cache hit rate. Since the direct mapping cache memory can have only one cache line for one index, there is a problem that mishits occur frequently and repeatedly, thereby increasing the number of accesses to the main memory.

Although the use of a hierarchical cache having a primary cache and a secondary cache makes it possible to improve the cache hit rate, access to the secondary cache generally requires extra access time. There has been a problem that the program execution time of a data processing unit such as a CPU becomes longer. There has been a conventional example of a hierarchical cache in which tag comparison is simultaneously performed in both a primary cache formed by a direct mapping cache and a secondary cache formed by an FSA cache. There is still much room for improvement. In addition, there is a case where the same data is stored in both the primary cache (direct mapping cache) and the secondary cache (FSA cache), so that the use efficiency of the memory space of the cache memory is reduced, There is a problem that the amount of cache data that can be stored in the memory decreases, and the cache hit rate cannot be improved to the maximum.

The present invention solves the above-mentioned problems in the conventional technology, and combines an FSA cache and a non-FSA cache such as a direct mapping cache to provide a cache line having a high hit rate. And high efficiency of the cache memory space, thereby realizing both high-speed data access and a high cache hit rate at a high level.
It is an object of the present invention to provide a cache system and a cache processing method capable of minimizing the number of accesses to an external memory such as a main memory and the data access time of a data processing unit such as a PU and an MPU.

[0019]

According to a first aspect of the present invention, there is provided a cache system comprising a CPU (Central Processes).
sing Unit), MPU (MicroProce)
In a cache system for reducing the number of accesses to an external memory such as a main memory of a data processing unit such as a ssor unit, an FSA (full set associative) type cache capable of holding a cache line having a high cache hit rate is used. If the first tag extracted from the input address data matches one of the first tags stored in the active cache line of the FSA cache, the active tag corresponding to the matched first tag is used. An FSA cache in which data stored in a cache line is read as cache data by the data processing unit, and a tag comparison for determining a cache hit, which is provided in the cache system in combination with the FSA cache. An active cache line that is a non-FSA cache that is performed simultaneously with the FSA cache and whose second tag extracted from the input address data corresponds to an index extracted from the input address data of the non-FSA cache. A non-FSA cache in which data stored in an active cache line corresponding to the matched second tag is read as cache data by the data processing unit when the second tag stored in the cache matches. A cache hit count storage means provided corresponding to each cache line of the FSA cache and storing a cache hit count value relating to the number of cache hits occurring in the cache line; A cache hit count management unit that counts a cache hit of a line and manages and updates the cache hit count value stored in the cache hit count storage unit, and stores the cache corresponding to the index in the non-FSA cache. If there is no inactive cache line and there is one or more inactive cache lines in the FSA cache and both the FSA cache and the non-FSA cache miss-hit, the FSA cache is not used. Is transferred to one of the inactive cache lines of the FSA cache, and the data stored in a cache line corresponding to the index of the cache that has missed is transferred to one of the inactive cache lines. Data fetched from Kigaibu memory the FSA
The data is transferred to the cache line of the cache other than the FSA system which is the data transfer source to the system cache, and there is no inactive cache line corresponding to the index in the cache other than the FSA system, and the FSA system The FSA cache and the FS when the cache is full of active cache lines
If both of the caches other than the A-type cache miss-hit, the data stored in a certain cache line corresponding to the index of the cache other than the FSA-type cache becomes the minimum cache hit count value of the FSA-type cache. The data fetched from the external memory due to the mishit of both the caches is transferred to one of the cache lines having the non-FSA type cache which is the data transfer source to the FSA type cache. In the case where both the FSA cache and the non-FSA cache miss-hit when there is an inactive cache line corresponding to the index in the cache other than the FSA cache, Both Data fetched from the external memory by mishit Yasshu are those to be written to the non-active cache line corresponding to the index of the cache other than the FSA method.

According to a second aspect of the present invention, in the cache system according to the first aspect, the FSA
When a cache line in a cache system has a cache hit, the cache hit count management means increments the cache hit count value of the cache line by one, and both the FSA cache and the non-FSA cache are updated. In the case of a miss hit, the cache hit count management means decrements the cache hit count value of all the cache lines of the FSA type cache by one at a time.

According to a third aspect of the present invention, in the cache system according to the first aspect, the FSA
The cache hit count management means increments the cache hit count value of the cache line by one when a cache line of the cache system has a cache hit. The hit count management means decrements the cache hit count value of all the cache lines of the FSA cache by one at a time.

According to a fourth aspect of the present invention, in the cache system according to the first aspect, the FSA
When a cache line in a system cache has a cache hit, the cache hit count management means increments the cache hit count value of the cache line by one.

A cache system according to a fifth aspect of the present invention is the cache system according to any one of the first to fourth aspects, wherein a direct mapping cache is used as a cache other than the FSA cache.

A cache system according to a sixth aspect of the present invention is the cache system according to any one of the first to fourth aspects, wherein an N-way set associative cache (N =
2, 4, 8,...) Are used.

A cache system according to a seventh aspect of the present invention is the cache system according to any one of the first to sixth aspects, wherein the cache system is provided corresponding to each cache line of the FSA cache. The system further includes a cache hit date and time storage unit for storing data relating to the date and time of the latest cache hit that has occurred, wherein the inactive cache line corresponding to the index does not exist in a cache other than the FSA system and the FSA system cache is The FSA cache and the FS when the active cache line is full
In the case where both of the caches other than the system A have a mishit, the cache line having the minimum cache hit count value of the FSA system cache based on the data stored in the cache hit date and time storage means. The cache line with the oldest cache hit is selected, and the selected cache line is
This is specified as a transfer destination of the data transfer to the SA system cache.

The cache system according to claim 8 is the cache system according to claim 6, wherein the cache system is provided corresponding to each index, and the latest cache hit among the N cache lines corresponding to the index is the oldest. LRU (Le for indicating a cache line)
L that stores the value of the last recently used value
RU storage means, wherein the inactive cache line corresponding to the index does not exist in the N-way set associative cache and the FSA
In the case where both the FSA cache and the N-way set associative cache miss-hit when one or more inactive cache lines are present in the cache, the N misses of the N-way set associative cache have occurred. A cache line specified by the LRU value is selected from the cache lines, and data stored in the selected cache line is transferred to one of the inactive cache lines of the FSA cache. The data fetched from the external memory due to the mishits of the two caches is written to the selected cache line of the N-way set associative cache from which data is transferred to the FSA cache; When there is no inactive cache line corresponding to the index in the N-way set associative cache and the FSA cache is full of active cache lines, both the FSA cache and the N-way set associative cache have a miss. In this case, the cache line specified by the LRU value is selected from the N missed cache lines of the N-way set associative cache, and the data stored in the selected cache line is deleted. Data transferred to one of the cache lines of the FSA cache having the smallest cache hit count value and fetched from the external memory due to a mishit in both caches is An inactive cache line corresponding to the index is written to the selected cache line of the N-way set associative cache that has become a data transfer source transfer source to the expression cache. In the above case, when both the FSA cache and the N-way set associative cache miss-hit, the data fetched from the external memory due to the miss-hit of both the caches is stored in the N-way set associative cache. The data is written to one of the inactive cache lines corresponding to the index.

A cache system according to a ninth aspect of the present invention is the cache system according to any one of the first to eighth aspects, wherein the FSA cache and the FSA cache are provided.
A secondary cache is further provided in addition to a primary cache including a cache other than the SA system.

[0028] The cache processing method according to claim 10 is
Using a combination of an FSA (full set associative) cache capable of holding a cache line with a high cache hit rate and a cache other than the FSA cache that performs tag comparison for cache hit determination simultaneously with the FSA cache, CentralP
processing Unit), MPU (Micro
In a cache processing method for reducing the number of accesses to an external memory such as a main memory of a data processing unit such as a processor unit, a first tag extracted from input address data is an active cache line of the FSA type cache. A first tag comparison step of comparing the first tag stored in the first tag with the first tag and determining that the FSA cache has a cache hit when there is a match of the first tag; And the second tag extracted from the input address data is stored in one or more active cache lines corresponding to the index extracted from the input address data in the non-FSA cache. Compared with the stored second tag, if there is a match of the second tag A second tag comparison step in which a cache other than the FSA cache is determined to have a cache hit, and a cache hit occurring in each cache line of the FSA cache are counted and correspond to each cache line of the FSA cache. A cache hit count management step of managing and updating the cache hit count value for each cache line stored in the cache hit count storage means provided in the cache memory; A first cache data reading step in which the data stored in the cache line corresponding to the matched first tag in the FSA cache is read as cache data by the data processing unit; In the second tag comparison step, when a cache hit of the non-FSA system cache hits, the data stored in the cache line corresponding to the second tag that matches the index of the non-FSA system cache is deleted. A second cache data reading step in which the data processing unit reads the cache data as cache data; and there is no inactive cache line corresponding to the index in the cache other than the FSA system, and one or more non-active cache lines are stored in the FSA system cache. If both the FSA cache and the non-FSA cache miss-hit when an active cache line exists, the cache is stored in a certain cache line corresponding to the missed index of the non-FSA cache. The data that has been fetched from the external memory due to the mishits of both caches is transferred to one of the inactive cache lines of the FSA A first data transfer step of writing to the cache line of the non-FSA cache, and the inactive cache line corresponding to the index does not exist in the non-FSA cache and the FSA cache becomes active. If both the FSA cache and the non-FSA cache miss-hit when the cache line is full,
The data stored in a certain cache line corresponding to the index in which the cache hit other than the SA type has hit is transferred to one of the cache lines having the minimum cache hit count value of the FSA type cache. The data fetched from the external memory due to the cache mishit of
The FSA from which data is transferred to the A-type cache
A second data transfer step in which data is written to the cache line of the non-FSA cache, and when there is an inactive cache line corresponding to the index in the non-FSA cache, the FSA cache and the non-FSA cache are used. If both cache misses, the data fetched from the external memory due to both cache misses is
And a third data transfer step of writing data to an inactive cache line corresponding to the index of the cache other than the scheme.

The cache processing method according to claim 11 is
11. The cache hit count managing step of the cache processing method according to claim 10, wherein, when a cache hit occurs in a cache line of the FSA cache, the cache hit count value of the cache line is incremented by one, and When both the system cache and the non-FSA system cache miss, the cache hit count value of all the cache lines of the FSA system cache is decremented by one at a time.

The cache processing method according to claim 12 is
11. The cache hit count managing step of the cache processing method according to claim 10, wherein when a cache line of the FSA type cache has a cache hit, the cache hit count value of the cache line is incremented by one, and When the system cache misses, the cache hit count value of all the cache lines of the FSA system cache is decremented by one at a time.

A cache processing method according to claim 13 is
11. The cache hit count managing step of the cache processing method according to claim 10, wherein when a cache hit occurs in a certain cache line of the FSA cache, the cache hit count value of the cache line is incremented by one. It was done.

The cache processing method according to claim 14 is
The cache processing method according to any one of claims 10 to 13, wherein a direct mapping cache is used as the cache other than the FSA cache.

The cache processing method according to claim 15 is
14. The cache processing method according to claim 10, wherein an N-way set associative cache (N = 2, 4, 8,...) Is used as the cache other than the FSA scheme. It was done.

The cache processing method according to claim 16 is
16. The cache processing method according to claim 10, wherein data relating to the date and time of the latest cache hit occurring in each cache line of the FSA cache is provided corresponding to each cache line. A cache hit date / time storing step of storing the data in the cache hit date / time storing means, and in the second data transfer step, the FSA cache based on the data stored in the cache hit date / time storing means. The cache line having the oldest cache hit is selected from among the cache lines having the minimum cache hit count value, and the selected cache line is assigned to the FS.
It is designed to be designated as a transfer destination of the data transfer from a cache other than the A system to the FSA system cache.

The cache processing method according to claim 17 is
16. The cache processing method according to claim 15, wherein an LRU (LeastRecently Use) for indicating a cache line in which a latest cache hit indicates an oldest cache line among N cache lines corresponding to each index.
d) an LRU storing step of storing a value in an LRU storing means provided corresponding to each index, wherein in the first data transfer step, N number of misses of the N-way set associative cache are stored. A cache line specified by the LRU value is selected from the selected cache lines, and data stored in the selected cache line is transferred to one of the inactive cache lines of the FSA type cache. And the data fetched from the external memory due to the mishit of both the caches is
The data is written to the selected cache line of the N-way set associative cache that has been the data transfer source to the SA system cache. The cache line specified by the LRU value is selected from the cache lines that have missed, and the data stored in the selected cache line has the minimum cache hit count value of the FSA cache. The data transferred to one of the lines and fetched from the external memory due to a mishit in both caches is selected by the N-way set associative cache from which data was transferred to the FSA cache. In the third data transfer step, the data fetched from the external memory due to the mishits of the two caches is stored in the non-cache corresponding to the index of the N-way set associative cache. The data is written to one of the active cache lines.

The cache processing method according to claim 18 is
The cache processing method according to any one of claims 10 to 17, wherein both the FSA cache and the non-FSA cache miss-hit the FSA cache and the non-FSA cache. And a secondary cache access step for accessing a secondary cache provided in addition to the primary cache.

A machine-readable recording medium according to any one of claims 19 to 27, wherein the computer-readable recording medium stores a program for causing a computer to execute a cache process according to the cache processing method according to any one of claims 10 to 18. It is.

[0038]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of a cache unit 15 of a cache system according to a first embodiment of the present invention, and FIG. 2 is a first embodiment of the present invention.
1 is a block diagram showing an example of a computer system to which a cache system according to the present invention is applied.

The computer system shown in FIG.
(Central Processing Unit)
50, a secondary cache 20, and a main memory 21. The secondary cache 20 is provided outside the CPU 50. The secondary cache 20 is, for example, a synchronous SRAM having a tag RAM and a data RAM.
And a memory having a page ROM. The type of the secondary cache 20 (whether or not a full set associative method is used) is not particularly limited. The computer system shown in FIG. 2 includes an address bus 1 for connecting the CPU 50, the secondary cache 20, the main memory 21, and the like.
And the data bus 2 are provided.
Are an address bus 1 and a data bus 2 external to the CPU 50.
At the same time as the secondary cache 20.

The CPU 50 has a bus interface (I /
F) unit 3, write buffer 4, control register 5,
MMU (Memory Management Uni)
t) Register 6, ALU (arithmetic lo)
gic operation unit) 7, GPR (G
It has a register 8, a multiplier 9, a barrel shifter 10, a program counter 11, a clock generator 12, a cache unit 15, and the like. This cache unit 15
Is provided in the CPU 50 as a primary cache of the cache system of the present embodiment, and the cache unit 15 is also connected to the address bus 1 and the data bus 2.

The clock generator 12 multiplies the frequency of the applied master clock signal to generate a clock signal for the computer system, and supplies the clock signal to each component of the computer system. The write buffer 4 is a buffer for temporarily storing system data to be written to the main memory 21 or the secondary cache 20, and is connected to the address bus 1 and the data bus 2 via the bus I / F unit 3. ing. The writing of the system data is performed according to the control data supplied to the bus I / F unit 3. The control register 5 and the MMU register 6 are similarly connected to the address bus 1 and the data bus 2. The control register 5 stores data relating to basic settings of the CPU 50, such as the frequency multiple of the clock generator 12, and the MMU register 6 stores data for address conversion between a virtual address and a physical address. ALU7, GPR register 8, Multiplier 9,
A unit for executing each instruction including the barrel shifter 10 and the program counter 11 is also connected to the address bus 1 and the data bus 2. The parts 7 to 11
Are hereinafter referred to as an instruction execution unit.

Referring to FIG. 1, a cache unit 1 as a primary cache of the cache system according to the present embodiment.
5 is a full set associative (FSA) type cache table TA, a direct mapping (DM) type cache table TB, comparators 30A and 30
0B, AND gates 31A and 31B, OR gate 3
2 and a data selector 33.

As shown in FIG. 1, the primary cache of this embodiment, that is, the cache unit 15, is constituted by a combination of a full set associative (FSA) type cache memory and a direct mapping (DM) type cache memory. Although FIG. 1 shows only one comparator 30A and one AND gate 31A, specifically, the comparator 30A is provided for each cache line of the FSA type cache table TA.
And an AND gate 31A, and a logical sum (OR) of the outputs of the AND gates 31A of all the cache lines is obtained by using one or more OR gates (not shown).

In the upper part of FIG. 1, "0000040" (hexadecimal) is shown as an example of the input address data. This input address data includes tag # 2, index, and offset. This tag # 2 is
Tag # 1, which is a tag used for DM cache table TB and another tag used for FSA cache table TA, is tag # 2.
(Tag # 1 = tag # 2 + index). For example, in the case of the input address data "00000040", the tag # 2 is "000
00 (for example, the first five digits of hexadecimal input address data), the index is "04" (for example, the next two digits of hexadecimal input address data), and tag # 1 is "0000".
004 "(for example, the first seven digits of hexadecimal input address data) and the offset is" 0 "(for example, the last one digit of hexadecimal input address data).

Each cache line of the FSA system cache table TA is provided with an access count area AC for indicating the number of accesses (cache hits) made to the cache line. By managing the access frequency of each cache line using the access count area AC by a method to be described later, it is possible to hold a cache line with a high access frequency (high cache hit rate) in the FSA cache table TA. . Note that an access counter for managing the access count area AC of all cache lines in the FSA cache table TA is, for example,
This is realized by an instruction execution unit having the above-described components 7 to 11. A program for controlling the operation of the cache system according to the present embodiment is stored in a recording medium such as a ROM (not shown), and the operation of the cache system described in detail later is performed according to the program.

The comparator 30A compares the tag # 1 extracted from the input address data with the tag # 1 stored in each cache line of the FSA cache table TA. If there is a match for tag # 1,
The comparator 30A outputs a high level (1) comparison signal to A
Output to ND gate 31A. The activation bit V1 (1/0) indicating whether the cache line corresponding to the matching tag # 1 is active or inactive is input from the FSA cache table TA to the AND gate 31A. If both the comparison signal from the comparator 30A and the activation bit V1 from the FSA cache table TA are "1", a cache hit signal (high level (1)) is output. As described above, FIG. 1 shows one comparator 30A and one AND gate 31A.
A comparator 30A and an AND gate 31A are provided for each cache line of the SA type cache table TA, and the logical sum (OR) of the outputs of the AND gates 31A of all the cache lines is obtained.

In parallel with the comparison of the tags in the FSA cache, the comparator 30B in the DM cache reads the tag # 2 extracted from the input address data and the DM # 2 corresponding to the index extracted from the input address data. The tag is compared with the tag # 2 stored in the cache line of the cache table TB. If the tag # 2 matches, the comparator 30B
Outputs a high-level (1) comparison signal to the AND gate 31B. An activation bit V2 (1/0) indicating whether the cache line corresponding to the matched tag # 2 is active or inactive is input from the DM cache table TB to the AND gate 31B. If both the comparison signal from the comparator 30B and the activation bit V2 from the DM cache table TB are “1”, a cache hit signal (high level (1)) is output.

The OR gate 32 outputs an activation signal (high level (1)) when a high level (1) cache hit signal is input from the AND gate 31A or 31B. When a high-level (1) activation signal is input from the OR gate 32, the data selector 33 sets the FSA cache table TA
Alternatively, a part of the data stored in the hit cache line of the DM cache table TB is selected based on the offset of the input address data, and the selected data is sent to the instruction decoder or the GPR register 8 (not shown) of the CPU 50. .

In this embodiment, when a cache hit occurs, one of the FSA cache table TA and the DM cache table TB occurs. That is, the FSA cache table TA
There is no case where a cache hit occurs in both the cache table and the DM cache table TB.

Although the FSA cache table TA (FSA cache memory) shown in FIG. 1 consumes more power than the DM cache table TB (DM cache memory) and has a complicated circuit configuration, It is possible to hold a cache line with a high hit rate. On the other hand, the DM cache table TB (DM cache memory) can be accessed at high speed for a small circuit scale, but has a disadvantage that the hit ratio is easily deteriorated. The primary cache (cache unit 15) of the cache system according to this embodiment is:
It is configured by combining the FSA cache table TA and the DM cache table TB having such features.

Hereinafter, the operation of the cache system according to the first embodiment of the present invention will be described in detail. FIG.
5 is a flowchart showing an operation of the cache system according to the first embodiment of the present invention. In this embodiment, the cache unit 1 as a primary cache
In the case where 5 is missed, data fetched from the main memory 21 or the secondary cache 20 is stored and registered in the DM cache table TB, and is not registered in the FSA cache table TA. If the cache unit 15 misses (that is, if both the FSA cache table TA and the cache line of the DM cache table TB corresponding to the index extracted from the input address data miss hit), the DM cache Data stored in the cache line corresponding to the index in the table TB is deleted (or deactivated) in the DM cache table TB and transferred to the FSA cache table TA.

The CPU 50 starts the instruction fetch process according to the input address data supplied from the program counter 11 (step S10). In the FSA cache memory, the comparator 30A shown in FIG. 1 (specifically, a plurality of comparators 30A provided corresponding to each cache line of the FSA cache table TA) has a tag # extracted from the input address data.
1 (the part other than the offset of the input address data);
The tag is compared with the tag # 1 stored in each cache line of the FSA cache table TA. If there is a match of the tag # 1 (Step S11: Yes), the comparator 30A outputs the high-level (1) comparison signal to A
Output to ND gate 31A. The output of the comparator 30A and the activation bit V of the cache line corresponding to the hit tag # 1 of the FSA cache table TA
If both are “1” (step S12: Ye
s), the AND gate 31A shown in FIG.
A plurality of AND gates 31A provided corresponding to each cache line of the A-system cache table TA and one or more OR gates for obtaining a logical sum (OR) of outputs of the plurality of AND gates 31A are at a high level. The cache hit signal of (1) is output to the OR gate 32. This cache hit signal indicates that a valid cache hit has occurred in the FSA cache table TA. If the extracted tag # 1 does not match any tag # 1 in the FSA cache table TA (step S11: No), or if the activation bit V1 of the hit cache line is “0” (step S12) : No), the output of the AND gate 31A becomes "0" (step S13).

At the same time, tag comparison for determining the presence or absence of a cache hit is also performed in the DM cache memory. In the DM cache memory, an index (two digits following tag # 2, which is the first five digits of hexadecimal input address data) is extracted from the input address data, and a cache corresponding to the index in the DM cache table TB is read. A line is selected and specified (step S14). Comparator 30B shown in FIG.
Is the tag # 2 extracted from the input address data (the part other than the index and offset of the input address data) and the tag # 2 stored in the selected cache line corresponding to the index in the DM cache table TB. Compare with If the tag # 2 matches (step S15: Yes), the comparator 30B outputs a high-level (1) comparison signal to the AND gate 31B. If both the output of the comparator 30B and the activation bit V2 of the hit cache line are “1” (step S16: Yes), the AND gate 31B
Outputs a high-level (1) cache hit signal to the OR gate 32. This cache hit signal is DM
Indicates that a valid cache hit has occurred in the scheme cache table TB. When the tag # 2 does not match (step S15: No), or when the activation bit V2 of the hit cache line is “0” (step S16: No), the output of the AND gate 31B is “0”. (Step S17).

If the cache hit signal from the AND gate 31A or the cache hit signal from the AND gate 31B is "1", the OR gate 32 shown in FIG. 33. Otherwise (when both cache hit signals are “0”), the OR gate 32 outputs a low-level (0) activation signal to the data selector 33. As described above, in this embodiment, the FSA cache tables TA and D
There is no case where a cache hit occurs in both of the M type cache tables TB. That is, the AND gate 31A
There is no case where the cache hit signal from both the AND gate 31B is "1".

If the activation signal output from the OR gate 32 is "0" (indicating that the cache unit 15 has miss-hit) (step S18: No), the CPU 50
Accesses the main memory 21 via the secondary cache 20, and obtains necessary data from the main memory 21 (when the secondary cache 20 has a mishit) or from the secondary cache 20 (when the secondary cache 20 has a cache hit). Fetch. In this case, the data (tag # 2 and data) stored in the cache line corresponding to the mis-hit index in the DM cache table TB is transferred to the FSA cache table TA (deleted in the DM cache table TB). Or deactivated), the main memory 21
Alternatively, data fetched from the secondary cache 20 is stored in the cache line of the DM cache table TB (step S19). In this case, D
When an inactive (active bit V2 is “0”) cache line corresponding to the index exists in the M-type cache table TB, the data is not transferred to the FSA-type cache table TA and the main memory 21 is not transferred. Alternatively, the data fetched from the secondary cache 20 is stored in an inactive cache line corresponding to the index of the DM cache table TB (step S19). Thereafter, the CPU 50 reads the data from the cache line of the DM cache table TB, and performs processing relating to the data (data or instruction) (step S21).

When the activation signal output from the OR gate 32 is "1" (indicating that the cache unit 15 has hit the cache) (step S18: Yes), the data selector 33 sets the FSA cache table T
A part of the data stored in the hit cache line of the A or DM cache table TB is selected and extracted based on the offset of the input address data (step S20), and the CPU 50 selects the selected data (data or instruction). ) Is performed (step S21).

Hereinafter, the operations of the FSA cache table TA and the DM cache table TB will be described in detail.

During initialization (when the computer system of FIG. 2 is reset or the power is turned on), all the cache lines of the FSA cache table TA and the DM cache table TB are deactivated. That is, the activation bits V1 and V2 of all the cache lines
Is reset to “0”. Thereafter, the FSA cache table TA or the DM cache table T
Each time data is written or transferred to a cache line with B, that cache line is activated.
That is, the activation bit V1 or V2 of the cache line is rewritten from "0" to "1".

When the cache unit 15 makes a mishit (that is, the FSA cache table TA and the DM
When both the cache line corresponding to the index of the system cache table TB and the cache line are mishit, the DM
The data (data and tag # 2) stored in the cache line of the system cache table TB is
It is transferred to the inactive cache line of the scheme cache table TA. By this transfer, the cache line of the DM cache table TB is deactivated (that is, the data stored in the cache line is deactivated or substantially deleted), and the cache of the FSA cache table TA is deactivated. The line is activated. Data fetched from the main memory 21 or the secondary cache 20 is written to the inactivated cache line of the DM cache table TB, and the cache line is activated again. As described above, when there is an inactive cache line corresponding to the index in the DM cache table TB, the data is not transferred to the FSA cache table TA and the main memory 21 is not transferred.
Alternatively, data fetched from the secondary cache 20 is written to an inactive cache line corresponding to the index of the DM cache table TB.

The active cache line of the FSA cache table TA is managed and controlled using the access count value stored in the access count area AC of each cache line. Note that the number of bits of access count area AC in this embodiment is set to, for example, 2 bits. FSA cache table TA
When data is written to a certain cache line, the access count value of that cache line is reset to "0" by the access counter (not shown). Each time a cache hit occurs in a certain cache line in the FSA cache table TA, the access counter (not shown) increments the access count value of the cache line by one.
If the cache unit 15 has a miss (ie, FS
When both the A-type cache table TA and the cache line corresponding to the index of the DM-type cache table TB miss-hit), the access counter simultaneously increases the access count values of all the cache lines of the FSA-type cache table TA by one. Decrement by. The minimum and maximum values of the access count value in this embodiment are 0 and 3 in decimal. That is, the access count value is not decremented to less than 0 and incremented to 4 or more.

In the above description, the simultaneous decrement of the access count value is performed when the cache unit 15 mishits. However, when the FSA cache table TA mishits (ie, FS
Simultaneous decrement of the access count value may be performed when all cache lines of the A-method cache table TA miss-hit). In this case, even when the DM cache table TB hits the cache and the FSA cache table TA misses, the access count value is simultaneously decremented. Is performed with a higher probability.

The following is a summary of such access count values. Substantial number of accesses to the AC cache line (number of cache hits) 0 0 or less 1 1 2 3 3 or more

When one or more inactive cache lines exist in the FSA cache table TA, the cache line is shifted from the missed cache line in the DM cache table TB to the FS cache line as described above.
It is regarded as a transfer destination when transferring data to the A-system cache table TA. Therefore, there is no inactive cache line corresponding to the index in the DM cache table TB.
If there is a miss hit in the cache unit 15 when there is one or more inactive cache lines in the cache, the data (data and tag # 2) stored in the missed cache line in the DM cache table TB is stored in the FSA cache. It is transferred to one of the inactive cache lines of the table TA.

On the other hand, the FSA cache table TA
Is full with active cache lines, FS
A cache line (one or more) having the minimum access count value in the A-type cache table TA
From the cache line of the DM system cache table TB that has missed the FSA system cache table T
A is considered as a transfer destination when data is transferred to A. Therefore, (there is no inactive cache line corresponding to the index in the DM cache table TB) FS
If the cache unit 15 misses while the A-type cache table TA is full of active cache lines, the data (data and tag # 2) stored in the mis-hit cache line of the DM type cache table TB is FSA. The data is transferred to one of the cache lines having the minimum access count value in the scheme cache table TA. In this case, the transfer destination may be randomly selected from one or more cache lines having the minimum count value, but the cache line having the oldest cache hit is selected from the cache lines and the cache line is selected. It is also possible to regard it as a transfer destination. Such selection of the cache line having the oldest cache hit can be realized, for example, by providing an area for storing the access date and time in each cache line of the FSA cache table TA.

If the cache unit 15 misses while the DM cache table TB has an inactive cache line corresponding to the index, the data fetched from the main memory 21 or the secondary cache 20 is , DM cache table T
B is written to the inactive cache line corresponding to that index. In this case, the above-mentioned DM cache table TB to FSA cache table T
No data transfer to A is performed.

In the following, the execution time of the cache processing will be described.

FIG. 4 is a schematic diagram showing an example of a program executed by the CPU 50. FIG. 4 is the same as FIG. 11 referred to in the description of the prior art. Referring to FIG. 4, this program has instructions (1), (2),... To be executed. CPU
50 is first supplied from the program counter 11;
The input address data related to the instruction (1) is referred to. Input address data "000" corresponding to the first instruction (1)
"0000040" indicates that this instruction (1) is stored in advance at address "00000040" in the main memory. As described above, the input address data “0000”
0040 "is the tag # 2 (00000), index (04) and offset (0) (and tag # 1 (0
000004)). This tag # 1, tag #
2. The input address data including the index and the offset is supplied to the cache unit 15, and the process for determining a cache hit is performed as described above. C
The PU 50 obtains necessary data (instruction (1)) from the FSA cache table TA, the DM cache table TB or the main memory 21 (or the secondary cache 20) according to the result of the cache hit determination process, and executes the instruction (1 ). After that, similar processing is performed for the following instructions (2), (3),.

FIGS. 5A and 5B are schematic diagrams showing access times when the CPU 50 using the cache system of this embodiment executes the program of FIG. 4 twice, and FIG. FIG. 5B shows the case of the first program execution, and FIG. 5B shows the case of the second program execution. FIG. 6 is a schematic diagram showing the states of the FSA cache table TA and the DM cache table TB immediately after the execution of the instruction (5) of the program in FIG.

The following description of the program execution time will be made under the same assumption as in the description of the prior art. That is, the FSA cache tables TA and D
The length of the data storage area of each cache line of the M type cache table TB is 4 words (16 bytes),
The length of each instruction of the program of FIG. 4 is 1 word (4 bytes) (that is, four instructions are stored in the data storage area of each cache line of the FSA cache table TA and the DM cache table TB). Shall be). The access time required to fetch data (instruction) from main memory is 10 words in the first word.
0 ns, and 30 ns for each of the following three words. Therefore, the access time required to fetch four words of data (four instructions) from the main memory 21 and store these data in one cache line of the DM cache table TB is 100 + 30 + 3.
0 + 30 = 190 ns. In addition, the CPU 50
It is assumed that it takes 10 ns to read and execute the instruction immediately after being stored in the cache line of the system cache table TB. When the cache unit 15 has a miss hit, data is fetched from the main memory 21 (the secondary cache 20 does not hit the cache).
It is assumed that the data processing time of the secondary cache 20 is zero. The cache size of the DM cache table TB is, for example, 4 kbytes.

In the initialization, all the cache lines of the FSA cache table TA and the DM cache table TB are deactivated. That is, the activation bits V1 and V2 of all the cache lines are reset to “0”. Immediately after this initialization, the activation bit V
Since 1 and V2 are all "0", there is substantially no data in the FSA cache table TA and DM cache table TB. For this reason, the CPU 50 fetches necessary data (the instructions (1) to (4) corresponding to the first index) from the main memory 21 and transfers the fetched instructions (1) to (4) to the DM.
The data is written to the cache line corresponding to the index “04” of the scheme cache table TB. By this data writing, the cache line corresponding to the index “04” of the DM cache table TB is activated. That is, the activation bit V2 of this cache line is set to "1" (see FIG. 1). Then, C
PU 50 reads the first instruction (1) from the cache line.
Is read and executed.

In the first program execution shown in FIG. 5A, 100 + 30 + 30 + 30 + 10 = 200 ns is required for the CPU 50 to execute the first instruction (1) after the startup routine of the computer system, and the subsequent instruction (2 ), (3), and (4) each require 10 ns (230 ns). Then C
The PU 50 stores addresses “00001030” to “00”
Similarly, four instructions corresponding to "00103C" are executed (200 + 10 + 10 + 10 = 230 ns).

When the CPU 50 attempts to execute the instruction (5) corresponding to the above-mentioned index “04”, the instruction (1) and this instruction (1) are already stored in the cache line corresponding to the index “04” in the DM cache table TB. Since the tag “00000” corresponding to the instruction (1) is stored, the cache line corresponding to the index “04” has a mishit (“00001” ≠ “0000”).
0 ") occurs. In the first program execution, F
The SA cache table TA also misses. Therefore, the instruction (1) and the tag # 2 (00000) stored in the cache line corresponding to the index “04” of the DM cache table TB are added to the inactive cache line of the FSA cache table TA (or The tag # 2 (00001) corresponding to the instruction (5) transferred from the cache line having the minimum access count value and fetched from the main memory 21 is stored in the cache line corresponding to the index “04” in the DM cache table TB. Written. Due to such a mishit, the execution of instruction (5) is also 100 + 30 +
It takes 30 + 30 + 10 = 200 ns. The execution of the following three instructions also takes 10 ns each (230 ns).
Therefore, the total program execution time in the first program execution is 230 × 3 = 690 ns.

When the first program execution of FIG. 5A is completed, all instructions of the program of FIG.
It is stored in the scheme cache table TA or the DM scheme cache table TB. For example,
When the CPU 50 attempts to execute the instruction (1) (corresponding to the above-mentioned index “04”) in the second program execution, this instruction (1) is already in the FSA cache table TA as shown in FIG. , And no mishit occurs in the second execution of the instruction (1). In this manner, in the second program execution of FIG. 5B, each instruction takes only 10 ns to execute, and the program execution time in the second program execution is 10 × 12 = 120 ns. Therefore, the total program execution time (access time) required to execute the program of FIG. 4 (FIG. 11) twice is 690.
+ 120 = 810 ns.

As described above, when the conventional direct mapping cache is used, two program executions require a total program execution time of 1190 ns. Therefore, the use of the cache system of the present embodiment has reduced the program execution time of 380 ns.

As described above, in the cache system according to the first embodiment of the present invention, the cache unit 15 combining the FSA cache table TA and the DM cache table TB is used as the primary cache of the cache system. Tag comparison for hit judgment is FSA cache table TA
And in the DM cache table TB at the same time. Therefore, in the cache unit 15 as the primary cache, high-speed tag comparison is performed at a higher cache hit rate, and the number of accesses to the (secondary cache 20 or) the main memory 21 of the CPU 50 and the data access time are reduced. Thus, high-speed program execution of the CPU 50 is realized.

Further, in the present cache system, data management / transfer is performed as follows.
The number of times of access (cache hit) to each cache line (access count value) of the FSA cache table TA is stored in the access count area AC of each cache line. When a cache hit occurs in a certain cache line of the FSA cache table TA, the access count value of the cache line is incremented by 1 and the cache unit 15 mishits (or the FSA cache table TA mishits). ), The access count values of all the cache lines in the FSA cache table TA are simultaneously decremented by one.

When there is no inactive cache line corresponding to the index in the DM cache table TB and one or more inactive cache lines exist in the FSA cache table TA, the cache unit 1
In the case where the 5th hit occurs, the data (data and tag # 2) stored in the missed cache line of the DM cache table TB is deleted from the inactive cache lines of the FSA cache table TA. And transferred to the main memory 21 (or the secondary cache 20) due to a mishit in the cache unit 15.
Is fetched from the cache line in the DM cache table TB (the data (data and tag # 2) are transferred to the FSA cache table TA).

If there is no inactive cache line corresponding to the index in the DM cache table TB and the FSA cache table TA is full of active cache lines, and a mishit occurs in the cache unit 15, , DM cache table T
The data (data and tag # 2) stored in the cache line with the miss hit B is transferred to one of the cache lines having the minimum access count value in the FSA cache table TA. Main memory 21 (or secondary cache 2)
0) is fetched from the (FSA cache table TA) of the DM cache table TB.
The data (data and tag # 2) has been transferred to the cache line. Preferably, the cache line having the oldest cache hit is selected from the cache lines having the minimum access count value in the FSA cache table TA, and the selected cache line is stored in the FSA cache table TB from the DM cache table TB. It is specified as a transfer destination when transferring data to the table TA.

If a miss hit of the cache unit 15 occurs when there is an inactive cache line corresponding to the index in the DM cache table TB, the miss hit of the cache unit 15 causes the main memory 21 (or the secondary cache). The data fetched from 20) is written to the inactive cache line corresponding to the index in the DM cache table TB.

By such data management / transfer, the FS
Update of the cache line held by the A-type cache table TA is performed based on the access count value (substantial hit count) of each cache line. As a result, the holding performance of a cache line with a high hit rate in the FSA cache table TA is improved, and the cache hit rate of the cache unit 15 is improved. Further, the data FSA cache tables TA and DM
Duplication in the scheme cache table TB is completely prevented. That is, the same data is not stored in both the FSA cache table TA and the DM cache table TB. Therefore, the memory spaces of the FSA cache table TA and the DM cache table TB can be completely and effectively used, and the amount of cache data that can be stored in the cache unit 15 having a limited data storage capacity is maximized. Can be. As a result, the cache hit rate of the cache unit 15 can be more effectively increased, and the number of accesses to the main memory 21 (or the secondary cache 20) of the CPU 50 can be minimized. Can be done.

Although the cache system according to the first embodiment has been described as including the secondary cache 20,
The effects of the first embodiment can be obtained even when the secondary cache 20 is not provided in the cache system as in the example shown in FIG. By adding the secondary cache 20, the effect of the cache system described above can be further increased.

Embodiment 2 FIG. 8 is a block diagram showing a configuration of the cache unit 15A of the cache system according to the second embodiment of the present invention. Cache unit 1 shown in FIG.
5A is used in the computer system shown in FIGS. 2 and 7 in Embodiment 2 instead of the cache unit 15 in FIG. Cache unit 1 in FIG.
The FSA cache table TA of 5A has an access count area AC of a larger size in FIG. Specifically, the size of the access count area AC of each cache line is set to, for example, 16 bits. This 16-bit wide access count area AC
Can count from 0 to 65535 (decimal), for example, as compared to the 2-bit access count area AC of Embodiment 1 which counts from 0 to 3 (decimal). .

In the second embodiment, the access counter (not shown) manages the access count area AC by a slightly different method. When a cache hit occurs in a certain cache line in the FSA cache table TA, the access counter (not shown) increments the access count value of this cache line by 1, as in the first embodiment. However, even if a mishit occurs in the cache unit 15A, simultaneous decrement (−1) of the access count values of all the cache lines in the FSA cache table TA is not performed. Therefore, in the second embodiment, the access count value stored in the access count area AC of each cache line of the FSA cache table TA is only incremented. The data transfer from the DM cache table TB to the FSA cache table TA is performed in the same manner as in the first embodiment.

In the first embodiment using the 2-bit width access count area AC, the number of cache lines having the minimum access count value (for example, 0) tends to increase, but in the second embodiment, the number of cache lines is reduced. Can be reduced. Therefore, according to the cache system of the second embodiment, the difference in the number of hits of the cache line can be more directly taken into the process of holding the high hit rate (high hit count) cache line of the FSA cache table TA. it can.

Embodiment 3 FIG. 9 is a schematic diagram showing a 4-way set associative cache table TC used as a cache table other than the FSA (full set associative) method in the cache unit 15B of the cache system according to the third embodiment of the present invention. In the first and second embodiments, the DM (direct mapping) type cache table TB is used as a cache table other than the FSA type in the cache unit (15, 15A). However, the cache unit 15B in the third embodiment is used. Is the FSA cache table T
A 4-way set associative cache table TC shown in FIG. 9 is used as a cache table other than the FSA scheme combined with A.

Referring to FIG. 9, this 4-way set associative cache table TC has four cache lines for each index. Each of the four cache lines corresponding to one index has an activation bit V2 and a tag #, as in the case of the DM cache table TB in the first and second embodiments.
2 and three areas for storing data. 4
At the left end of the line consisting of cache lines,
An LRU area for storing (least recently used) values is provided. The LRU value is the least recently used cache hit among the four cache lines corresponding to one index, that is, the least recently used cache hit.
y used) Used to indicate a cache line. The size of this LRU area is set to, for example, 2 bits so as to be able to represent four cache lines.

The DM cache table TB is set to 1 for one index (corresponding to one tag # 2).
The 4-way set associative cache table TC can store four pieces of data (corresponding to four tags # 2) for one index, as compared with storing only four pieces of data. Therefore, the cache hit ratio of the 4-way set associative cache table TC is higher than the cache hit ratio of the DM cache table TB.

Hereinafter, operations of the FSA cache table TA and the 4-way set associative cache table TC in the cache unit 15B of the cache system according to the third embodiment will be described in detail. The tag comparison for the cache hit determination in the 4-way set associative cache table TC is performed using the index extracted from the input address data and the tag # 2 as in the case of the DM cache table TB. In the case of the 4-way set associative cache table TC (4-way set associative cache memory), four tag comparisons are simultaneously performed for one index and one tag # 2 extracted from one input address data. Operations of the cache system according to the third embodiment other than those described below are almost the same as those of the cache system according to the first embodiment.

During initialization (when the computer system is reset or the power is turned on), all the cache lines in the FSA cache table TA and the 4-way set associative cache table TC are deactivated. That is, the activation bits V1 and V2 of all the cache lines are reset to “0”. Then, F
Each time data is written or transferred to a certain cache line in the SA type cache table TA or the 4-way set associative cache table TC, the cache line is activated, that is, the activation bit V1 or V2 of the cache line is set to " It is rewritten from "0" to "1".

The number of accesses (cache hits) to each cache line (access count value) of the FSA cache table TA is stored in the access count area AC of each cache line. When a cache hit occurs in a certain cache line of the FSA cache table TA, the access count value of the cache line is incremented by 1 and the cache unit 15B misses (or the FSA cache table TA misses). ), The access count values of all the cache lines in the FSA cache table TA are simultaneously decremented by one.

When the inactive cache line corresponding to the index does not exist in the 4-way set associative cache table TC and one or more inactive cache lines exist in the FSA cache table TA, the cache hit of the cache unit 15B is performed. Occurs (four cache lines corresponding to the indexes of the FSA cache table TA and the index of the 4-way set associative cache table TC cause a miss), the four misses of the 4-way set associative cache table TC. The data stored in one of the hit cache lines (data and tag #
2) is transferred to one of the inactive cache lines of the FSA cache table TA. 4 at this time
The selection from the missed cache line is performed based on the LRU value stored in the LRU area of the row corresponding to the index, and the cache line specified by the LRU value is stored in the 4-way set associative cache table TC. Is selected as a transfer source for data transfer from the FSA type cache table TA to the FSA type cache table TA. The main memory 21 due to a mishit in the cache unit 15B
The data fetched from the (or the secondary cache 20) is written to the selected cache line of the 4-way set associative cache table TC (the data (data and tag # 2) have been transferred to the FSA cache table TA). It is.

When there is no inactive cache line corresponding to the index in the 4-way set associative cache table TC and the FSA cache table TA is full of active cache lines, and a mishit occurs in the cache unit 15B. In the four-way set associative cache table TC, the data (data and tag # 2) stored in the cache line specified by the LRU value among the four missed cache lines in the four-way set associative cache table TC is stored in the FSA cache table TA. Is transferred to one of the cache lines having the minimum access count value. At this time, the transfer destination can be randomly selected from the cache lines having the minimum access count value. It can also be considered first. Such a selection is performed, for example, by setting an area for storing the access date and time in the FSA cache table TA.
Can be realized by providing each cache line.
Main memory 2 due to mishit in cache unit 15B
The data fetched from 1 (or the secondary cache 20) is specified by the LRU value of the 4-way set associative cache table TC (data (data and tag # 2) transferred to the FSA cache table TA). Written to the cache line.

When one or more inactive cache lines corresponding to the index exist in the 4-way set associative cache table TC, the cache unit 15B
If a mis-hit occurs, the cache unit 15B
The data fetched from the main memory 21 (or the secondary cache 20) due to the mishit is written to one of the inactive cache lines corresponding to the index in the 4-way set associative cache table TC.

As described above, according to the cache system according to the third embodiment of the present invention, each effect of the first embodiment can be obtained, and in addition to the use of the 4-way set associative cache table TC, a cache other than the FSA system can be used. You can increase the hit rate of the table,
Cache unit 15B with higher cache hit rate
Can be realized. In particular, when the CPU 50 executes a program with many branches, that is, when the CPU 50 executes many instructions corresponding to the same index, 4
The effect of improving the cache hit rate of the way set associative cache table TC is remarkably exhibited. Therefore, the cache system according to the third embodiment is particularly effective for a computer system that executes a complicated program having many branches.

In the third embodiment, a 4-way set associative cache is used as a cache other than the FSA system combined with the FSA system cache. Of course, it is also possible to use a cache or the like.

Further, the access count area AC having a large size as used in the second embodiment is used for the F in the third embodiment.
It is also possible to provide an access counter (not shown) for each cache line of the SA type cache table TA to perform the same operation as in the second embodiment. In this case, the same effect as in the second embodiment can be obtained.

In the first and third embodiments, description will be made on the assumption that the initial value of the access count value stored in the access count area AC of each cache line of the FSA cache table TA is "0". However, this initial value is not limited to “0”. For example, it is possible to have a larger initial value to prevent the access count value from being concentrated on "0". In such a case, the size (number of bits) of the access count area AC is set slightly larger.

[0099]

As described above, in the cache system and the cache processing method of the present invention, a cache (T) other than the FSA type such as the DM type cache (TB) is used.
B, TC) and the FSA cache (TA) are combined, and tag comparison for cache hit determination is performed simultaneously in both caches. The number of cache hits generated in each cache line of the FSA cache (TA) is counted by an access counter (not shown), and the access count value related to the number of cache hits is stored in the access count area AC of each cache line. For example, when a certain cache line of the FSA cache (TA) has a cache hit, the access count value of the cache line is incremented by one. Are decremented by one at a time.

In order to improve the cache hit rate of the cache system including the FSA type cache (TA) and the non-FSA type caches (TB, TC), data management / transfer of each cache is performed using the access count value. Is performed as follows.

Caches other than the FSA system (TB, T
When there is no inactive cache line corresponding to the index in C) and one or more inactive cache lines exist in the FSA cache (TA), the FSA cache (TA) and the non-FSA cache (T
B, TC), the data stored in a certain cache line corresponding to the missed index of the non-FSA cache (TB, TC) becomes inactive in the FSA cache (TA). Transfer to one of the cache lines, and an external memory (2
The data fetched from (0, 21) is written to the cache line of the non-FSA type cache (TB, TC) which is the data transfer source to the FSA type cache (TA).

Caches other than the FSA system (TB, T
If no inactive cache line corresponding to the index exists in C) and the FSA cache (TA) is full of active cache lines, the FSA cache (T
If both A) and the non-FSA caches (TB, TC) have a mishit, the data stored in a certain cache line corresponding to the mis-hit index of the non-FSA cache (TB, TC) F
The data transferred to one of the cache lines having the smallest cache hit count value of the SA type cache (TA) and fetched from the external memory (20, 21) such as the CPU due to the mishit of both caches is FSA. The data is written to the cache line of the non-FSA type cache (TB, TC) which has been the data transfer source to the type cache (TA).

Caches other than the FSA system (TB, T
When an inactive cache line corresponding to the index exists in C), the FSA cache (TA) and the FS
If both the caches (TB, TC) other than the A type have a mishit, the data fetched from the external memory (20, 21) such as the CPU due to the mishits of both caches will not be used. TC)
Is written to the inactive cache line corresponding to the index of.

By managing / transferring data using such an access count value (cache hit count value), the holding performance of a cache line having a high cache hit rate of the FSA cache (TA) is improved, and the cache hit rate is reduced. Be improved. FS of the same data
Duplication between the A-type cache (TA) and the non-FSA type caches (TB, TC) is completely prevented, the use efficiency of the memory space of the cache system is improved to the maximum, and the cache hit ratio is improved to an extremely high level. It becomes possible. Thereby, the cache hit ratio and the data access speed can be improved at an extremely high level.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cache unit 15 of a cache system according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a computer system to which the cache system according to the first embodiment of the present invention is applied;

FIG. 3 is a flowchart showing an operation of the cache system according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram showing an example of a program executed by a CPU shown in FIG.

FIG. 5 is a schematic diagram showing an access time when a CPU using the cache system according to the first embodiment of the present invention executes the program of FIG. 4 twice; FIG. (B) shows the case of the second program execution.

FIG. 6 shows a state immediately after execution of an instruction (5) of the program in FIG.
FIG. 2 is a schematic diagram showing states of an FSA cache table TA and a DM cache table TB shown in FIG. 1.

FIG. 7 is a block diagram showing a case where another example of the cache system according to the present invention is applied to a computer system.

FIG. 8 is a block diagram showing a configuration of a cache unit of a cache system according to a second embodiment of the present invention.

FIG. 9 is a schematic diagram showing a 4-way set associative cache table TC used as a cache table other than the full set associative method in the cache unit of the cache system according to the third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a typical conventional direct mapping cache.

FIG. 11 is a schematic diagram illustrating an example of a program realized by a CPU.

12 is a schematic diagram showing an example of a state change of the cache table of the direct mapping cache of FIG. 10 when the CPU executes the program of FIG. 11;
(A) shows the state immediately after the execution of the instruction (1), and (b) shows the state immediately after the execution of the instruction (5).

13A and 13B are schematic diagrams showing access times when a CPU using a conventional direct mapping cache executes the program of FIG. 11 twice, wherein FIG. 13A shows the first program execution and FIG. Indicates the case of the second program execution.

[Explanation of symbols]

15 Cache unit (primary cache) 20 Secondary cache (external memory) 21 Main memory (external memory) 50 CPU (data processing unit) AC access count area (cache hit count storage means) TA FSA type cache table (full set associative type) Cache) TB DM cache table (cache other than direct mapping cache and full set associative cache) TC 4-way set associative cache table (cache other than N way set associative cache and full set associative cache)

Claims (27)

[Claims] 1. A CPU (Central Processes)
sing Unit) (50), MPU (MicroP)
external unit (2) such as a main memory (21) of a data processing unit (50) such as a processor unit.
A cache system for reducing the number of accesses to (0, 21) is a full set associative (FSA) cache (TA) capable of holding a cache line having a high cache hit rate, and is extracted from input address data. The first tag (# 1) is the FSA cache (T
When a match is found with one of the first tags (# 1) stored in the active cache line of A), the data is stored in the active cache line corresponding to the matched first tag (# 1). Data is stored in the data processing unit (5).
FSA read as cache data by 0)
And a non-FSA cache (TA) which is provided in combination with the FSA cache (TA) in the cache system and performs a tag comparison for cache hit determination simultaneously with the FSA cache (TA). TB, TC), and the second tag (# 2) extracted from the input address data is an active tag corresponding to the index extracted from the input address data of the cache (TB, TC) other than the FSA system. When the data matches the second tag (# 2) stored in the cache line, the data stored in the active cache line corresponding to the matched second tag (# 2) is stored in the data processing unit. A cache other than the FSA system read as cache data by (50) ( TB, T
C) a cache hit count storage means (AC) provided corresponding to each cache line of the FSA cache (TA) and storing a cache hit count value relating to the number of cache hits occurring in the cache line; A cache hit count managing means for counting cache hits of each cache line of the FSA cache (TA), and managing and updating the cache hit count value stored in the cache hit count storing means (AC); When there is no inactive cache line corresponding to the index in the cache other than the FSA system (TB, TC) and one or more inactive cache lines exist in the FSA system cache (TA), the FSA system cache is used. (TA) If both caches other than the FSA method (TB, TC) has mishit, the F
Data stored in a certain cache line corresponding to the index in which the mishit has occurred in the non-SA cache (TB, TC) is transferred to one of the inactive cache lines of the FSA cache (TA). Then, the data fetched from the external memories (20, 21) due to the mishits of the two caches are transferred to the non-FSA type caches (TB, T) which are the data transfer source to the FSA type cache (TA).
C), the cache line (TB, TC) other than the FSA system has no inactive cache line corresponding to the index, and the FSA system cache (TA) is full of active cache lines. When the FSA cache (TA) and the non-FSA cache (TB, T
C), when both misses occur, the data stored in a certain cache line corresponding to the missed index of the cache (TB, TC) of the non-FSA cache becomes the minimum of the FSA cache (TA). And the data fetched from the external memories (20, 21) due to the mishits of the two caches is transferred to the FSA cache (TA).
An inactive cache line corresponding to the index is written to the cache line of the non-FSA type cache (TB, TC) that has become a data transfer source to the non-FSA type cache (TB, TC). The FSA cache (TA) and the F
If both the caches (TB, TC) other than the SA scheme miss-hit, the data fetched from the external memory (20, 21) due to the miss-hit of both caches will cause the caches (TB, TB, non-FSA scheme) to fetch. T
C) A cache system wherein data is written to an inactive cache line corresponding to the index of C). 2. When a cache hit occurs in a certain cache line of the FSA cache (TA),
The cache hit count management means increments the cache hit count value of the cache line by one. 2. The cache system according to claim 1, wherein said cache hit count management means decrements said cache hit count value of all the cache lines of said FSA cache (TA) by one at a time. 3. When a cache line in the FSA cache (TA) has a cache hit,
The cache hit count management means increments the cache hit count value of the cache line by one. 2. The cache system according to claim 1, wherein the cache hit count values of all the cache lines are decremented by one at a time. 4. When a cache line hits a certain cache line in the FSA cache (TA),
2. The cache system according to claim 1, wherein said cache hit count management means increments the cache hit count value of the cache line by one. 5. A cache other than the FSA system (T
The cache system according to any one of claims 1 to 4, wherein a direct mapping cache (TB) is used as (B, TC). 6. The cache other than the FSA system (T
5. An apparatus according to claim 1, wherein an N-way set associative cache (TC) (N = 2, 4, 8,...) Is used as (B, TC).
The cache system according to the item. 7. A cache hit date and time storage means provided corresponding to each cache line of the FSA type cache (TA) and storing data relating to the date and time of the latest cache hit occurring in the cache line, When there is no inactive cache line corresponding to the index in the cache (TB, TC) other than the FSA type cache and the FSA type cache (TA) is full of active cache lines, the FSA type cache (TA) and the aforementioned Caches other than the FSA system (TB, T
C) In the case where both of the misses occur, the cache line having the minimum cache hit count value of the FSA type cache (TA) is determined based on the data stored in the cache hit date and time storage means. , A cache line having the oldest cache hit is selected, and the selected cache line is designated as a transfer destination of the data transfer from the non-FSA cache (TB, TC) to the FSA cache (TA). The cache system according to any one of claims 1 to 6, wherein the cache system is executed. 8. An LRU (Least Recently) provided for each index, wherein a latest cache hit among the N cache lines corresponding to the index indicates the oldest cache line.
Further comprising an LRU storage unit for storing a value of the N-way set associative cache (TC).
When there is no inactive cache line corresponding to the index and one or more inactive cache lines exist in the FSA cache (TA).
In the case where both the A-type cache (TA) and the N-way set associative cache (TC) have missed, the LRU is selected from the N missed cache lines of the N-way set associative cache (TC). The cache line specified by the value is selected, and the data stored in the selected cache line is stored in the FSA cache (TA).
And the data fetched from the external memories (20, 21) due to the mishits of both caches is the data transfer source to the FSA type cache (TA). Said N-way set associative cash (T
C) written to the selected cache line of the N-way set associative cache (TC)
When there is no inactive cache line corresponding to the index and the FSA cache (TA) is full of active cache lines, both the FSA cache (TA) and the N-way set associative cache (TC) In the case where
The N-way set associative cache (TC)
A cache line specified by the LRU value is selected from the N number of missed cache lines, and the data stored in the selected cache line is stored in the minimum cache of the FSA type cache (TA). The data transferred to one of the cache lines having a hit count value and fetched from the external memories (20, 21) due to the mishits of both caches are transferred to the FSA cache (T
A) is written to the selected cache line of the N-way set associative cache (TC) from which data is transferred to A), and the N-way set associative cache (TC) is written.
When one or more inactive cache lines corresponding to the index exist in the FSA cache (T
In the case where both A) and the N-way set associative cache (TC) miss-hit, the external memory (2
7. The data fetched from (0, 21) is written to one of the inactive cache lines corresponding to the index of the N-way set associative cache (TC). Cache system. 9. A secondary cache (20) provided in addition to a primary cache (15) comprising the FSA cache (TA) and the non-FSA cache (TB, TC). The cache system according to any one of claims 1 to 8, wherein 10. An FSA (full set associative) cache (TA) capable of holding a cache line having a high cache hit rate and an FSA scheme for performing a tag comparison for cache hit determination simultaneously with the FSA cache (TA). Other caches (TB, TC)
CPU (Central Pr)
processing Unit) (50), MPU (Mi
In a cache processing method for reducing the number of accesses to an external memory (20, 21) such as a main memory (21) by a data processing unit (50) such as a croProcessor Unit), the first data extracted from input address data Tag (# 1)
Is compared with a plurality of first tags (# 1) stored in an active cache line of the FSA cache (TA), and when there is a match of the first tags (# 1), A first tag comparing step in which it is determined that the FSA cache (TA) has a cache hit; and a second tag (# 2) which is performed simultaneously with the first tag comparing step and is extracted from the input address data. Is the F
1 corresponding to the index extracted from the input address data of the cache (TB, TC) other than the SA system
The second tag (# 2) stored in the active cache line is compared with the second tag (# 2). If there is a match of the second tag (# 2), the cache (T
(B, TC) is determined to have a cache hit, and a cache hit occurring in each cache line of the FSA cache (TA) is counted.
A cache hit count storage means (A provided for each cache line of the A-type cache (TA)
C) a cache hit count management step in which the cache hit count value for each cache line stored in C) is managed and updated; and if the FSA cache (TA) has a cache hit in the first tag comparison step, The FS
A first cache data read in which data stored in a cache line corresponding to the matched first tag (# 1) of the A-system cache (TA) is read as cache data by the data processing unit (50). And if the cache (TB, TC) other than the FSA scheme has a cache hit in the second tag comparison step, the second index that matches the index of the cache (TB, TC) other than the FSA scheme. The data stored in the cache line corresponding to the tag (# 2)
A second cache data reading step of being read as cache data by the data processing unit (50); and an inactive cache line corresponding to the index does not exist in a cache (TB, TC) other than the FSA system, and the FSA If there is one or more inactive cache lines in the system cache (TA) and both the FSA system cache (TA) and the non-FSA system caches (TB, TC) miss-hit,
Data stored in a certain cache line corresponding to the missed index of the cache (TB, TC) other than the SA type cache is transferred to one of the inactive cache lines of the FSA type cache (TA). Then, the data fetched from the external memories (20, 21) due to the mishits of the two caches are transferred to the FSA cache (TA) by the non-FSA caches (TB, T).
C) a first data transfer step of writing to the cache line; and the non-FSA cache (TB, TC) has no inactive cache line corresponding to the index and the FSA cache (TA). Is full of active cache lines, the FSA cache (TA) and the non-FSA cache (TB, T
C), the data stored in a certain cache line corresponding to the mis-indexed cache (TB, TC) of the non-FSA cache (TB, TC) is the minimum of the FSA cache (TA). And the data fetched from the external memory (20, 21) due to the mishit of both caches is transferred to the FSA cache (TA).
A second data transfer step of writing to the cache line of the non-FSA-based cache (TB, TC) from which data has been transferred to the cache, and the index corresponding to the non-FSA-based cache (TB, TC) The FSA cache (TA) and the FSA cache when there is an inactive cache line
If both of the caches (TB, TC) other than the SA scheme miss-hit, the data fetched from the external memory (20, 21) due to the miss-hit of both caches causes the caches (TB, TC, TC) other than the FSA scheme. T
C) a third data transfer step of writing data to an inactive cache line corresponding to the index of C). 11. In the cache hit count managing step, when a cache line in the FSA cache (TA) has a cache hit, the cache hit count value of the cache line is incremented by one. If both the cache (TA) and the caches (TB, TC) other than the FSA system have miss-hits, the cache hit count values of all the cache lines of the FSA system cache (TA) are decremented by one at a time. 11. The method according to claim 10, wherein
The cache processing method described. 12. In the cache hit count management step, when a cache line in the FSA cache (TA) has a cache hit, the cache hit count value of the cache line is incremented by one. 11. The cache processing method according to claim 10, wherein when the cache (TA) has a mishit, the cache hit count values of all the cache lines of the FSA cache (TA) are decremented by one at a time. . 13. In the cache hit count managing step, when a cache hit occurs in a cache line of the FSA cache (TA), the cache hit count value of the cache line is incremented by one. The cache processing method according to claim 10, wherein 14. A cache other than the FSA system (T
14. A cache processing method according to claim 10, wherein a direct mapping cache (TB) is used as (B, TC). 15. The cache other than the FSA system (T
14. The method according to claim 10, wherein an N-way set associative cache (TC) (N = 2, 4, 8,...) Is used as (B, TC). Cache processing method. 16. A cache hit which stores data relating to the date and time of the latest cache hit occurring in each cache line of said FSA type cache (TA) in a cache hit date and time storage means provided corresponding to each of said cache lines. A date / time storage step, wherein the second data transfer step has the minimum cache hit count value of the FSA cache (TA) based on the data stored in the cache hit date / time storage means. The cache line with the oldest cache hit is selected from the cache lines, and the selected cache line is transferred from the cache (TB, TC) other than the FSA system to the F line.
11. The data transfer method according to claim 10, wherein the transfer destination is specified as a transfer destination of the data transfer to an SA system cache.
6. The cache processing method according to any one of 5. 17. An LRU (Least R.R.L.) for indicating that the latest cache hit indicates the oldest cache line among the N cache lines corresponding to each index.
LRU storing means for storing a newly used (U.S. recent used) value in an LRU storing means provided corresponding to each index. In the first data transfer step, N number of N-way set associative caches (TC) are provided. A cache line specified by the LRU value is selected from the cache lines that have been hit, and the data stored in the selected cache line is stored in the FS.
The data transferred to one of the inactive cache lines of the A-type cache (TA) and fetched from the external memories (20, 21) due to the mishit of both the caches is transferred to the FSA type cache (T
A) The data is written to the selected cache line of the N-way set associative cache (TC) that has been the data transfer source to A), and in the second data transfer step, the N-way set associative cache (TC) A cache line specified by the LRU value is selected from the N missed cache lines, and data stored in the selected cache line is stored in the FS.
Data transferred to one of the cache lines having the minimum cache hit count value of the A-type cache (TA) and fetched from the external memories (20, 21) due to both cache mishits is The data is written to the selected cache line of the N-way set associative cache (TC) that has been a data transfer source to the FSA type cache (TA). In the third data transfer step, both of the caches are written. The external memory (20, 2)
16. The cache according to claim 15, wherein the data fetched from 1) is written to one of the inactive cache lines corresponding to the index of the N-way set associative cache (TC). Processing method. 18. When both the FSA cache (TA) and the non-FSA caches (TB, TC) have a mishit, the FSA cache (TA) and the non-FSA caches (TB, TC). T
18. The method according to claim 10, further comprising a secondary cache access step for accessing a secondary cache (20) provided in addition to the primary cache (15) comprising C). The cache processing method according to claim 1. 19. An FSA (full set associative) cache (TA) capable of holding a cache line having a high cache hit rate and an FSA scheme for performing a tag comparison for determining a cache hit simultaneously with the FSA cache (TA). Other caches (TB, TC)
CPU (Central Pr)
processing Unit) (50), MPU (Mi
machine reading that stores a program for causing a computer to execute a cache process for reducing the number of accesses to an external memory (20, 21) such as a main memory (21) of a data processing unit (50) such as a croProcessor Unit (50). The cache processing is a possible recording medium, wherein a cache hit occurring in each cache line of the FSA cache (TA) is counted,
A cache hit count storage means (A provided for each cache line of the A-type cache (TA)
C) a cache hit count management step of managing and updating the cache hit count value of each cache line stored in C), and, when the FSA cache (TA) has a cache hit, the cache hit count of the FSA cache (TA). A first cache data reading step in which the data stored in the cache line having the cache hit is read as cache data by the data processing unit (50); and a cache (TB, TC) other than the FSA type cache hit In this case, the data stored in the cache line corresponding to the index extracted from the input address data in the cache (TB, TC) other than the FSA system is stored in the data processing unit (50). Yo A second cache data reading step to be read as cache data; and an inactive cache line corresponding to the index does not exist in the non-FSA cache (TB, TC), and one or more in the FSA cache (TA). When both the FSA cache (TA) and the non-FSA cache (TB, TC) miss-hit when there is an inactive cache line of
Data stored in a certain cache line corresponding to the missed index of the cache (TB, TC) other than the SA type cache is transferred to one of the inactive cache lines of the FSA type cache (TA). Then, the data fetched from the external memories (20, 21) due to the mishits of the two caches are transferred to the FSA cache (TA) by the non-FSA caches (TB, T).
C) a first data transfer step of writing to the cache line; and the non-FSA cache (TB, TC) has no inactive cache line corresponding to the index and the FSA cache (TA). Is full of active cache lines, the FSA cache (TA) and the non-FSA cache (TB, T
C), the data stored in a certain cache line corresponding to the mis-indexed cache (TB, TC) of the non-FSA cache (TB, TC) is the minimum of the FSA cache (TA). And the data fetched from the external memory (20, 21) due to the mishit of both caches is transferred to the FSA cache (TA).
A second data transfer step of writing to the cache line of the non-FSA-based cache (TB, TC) from which data has been transferred to the cache, and the index corresponding to the non-FSA-based cache (TB, TC) The FSA cache (TA) and the FSA cache when there is an inactive cache line
If both of the caches (TB, TC) other than the SA scheme miss-hit, the data fetched from the external memory (20, 21) due to the miss-hit of both caches causes the caches (TB, TC, TC) other than the FSA scheme. T
C) a third data transfer step of writing data to an inactive cache line corresponding to the index of (C). 20. In the cache hit count managing step, when a cache line in the FSA cache (TA) has a cache hit, the cache hit count value of the cache line is incremented by one. If both the cache (TA) and the caches (TB, TC) other than the FSA system have miss-hits, the cache hit count values of all the cache lines of the FSA system cache (TA) are decremented by one at a time. The method of claim 19, wherein
The machine-readable recording medium according to the above. 21. In the cache hit count managing step, when a cache line in the FSA cache (TA) has a cache hit, the cache hit count value of the cache line is incremented by one. 20. The machine-readable machine according to claim 19, wherein, when the cache (TA) has a mishit, the cache hit count value of all cache lines of the FSA cache (TA) is decremented by one at a time. Recording medium. 22. In the cache hit count managing step, when a cache hit occurs in a cache line of the FSA cache (TA), the cache hit count value of the cache line is incremented by one. The machine-readable recording medium according to claim 19, wherein: 23. A cache other than the FSA system (T
The machine-readable recording medium according to any one of claims 19 to 22, wherein a direct mapping cache (TB) is used as (B, TC). 24. A cache other than the FSA system (T
23. The method according to claim 19, wherein an N-way set associative cache (TC) (N = 2, 4, 8,...) Is used as (B, TC). A machine-readable recording medium. 25. The cache processing, wherein data relating to the date and time of the latest cache hit generated in each cache line of the FSA cache (TA) is stored in a cache hit date and time storage means provided for each cache line. A cache hit date and time storing step, wherein in the second data transfer step, the minimum cache hit count of the FSA cache (TA) is based on the data stored in the cache hit date and time storage means. The cache line having the oldest recent cache hit is selected from the cache lines having the values, and the selected cache line is transferred from the cache (TB, TC) other than the FSA system to the F line.
20. The transfer destination of the data transfer to the SA type cache (TA) is designated.
5. The machine-readable recording medium according to any one of 4. 26. The cache processing according to claim 17, wherein an LRU (Least Recently Used) value for indicating a cache line whose latest cache hit is the oldest among N cache lines corresponding to each index is associated with each index. An LRU storing step of storing the LRURU value in the provided LRU storing means, wherein in the first data transfer step, the LRURU value is selected from N mis-hit cache lines of the N-way set associative cache (TC). Is selected, the data stored in the selected cache line is transferred to one of the inactive cache lines of the FSA type cache (TA), and both of the cache lines are selected. Of the external Mori (20, 21)
The data fetched from the cache is written to the selected cache line of the N-way set associative cache (TC) that has been a data transfer source to the FSA type cache (TA). In the second data transfer step, The cache line specified by the LRU value is selected from the N missed cache lines of the N-way set associative cache (TC), and the data stored in the selected cache line is stored in the FS.
Data transferred to one of the cache lines having the minimum cache hit count value of the A-type cache (TA) and fetched from the external memories (20, 21) due to both cache mishits is The data is written to the selected cache line of the N-way set associative cache (TC) that has been a data transfer source to the FSA type cache (TA). In the third data transfer step, both of the caches are written. The external memory (20, 2)
25. The machine of claim 24, wherein the data fetched from 1) is written to one of the inactive cache lines corresponding to the index of the N-way set associative cache (TC). A readable recording medium. 27. The cache processing according to claim 27, wherein both the FSA cache (TA) and the non-FSA cache (TB, TC) have a miss hit.
A primary cache (1) comprising an SA cache (TA) and a cache (TB, TC) other than the FSA cache.
Secondary cache (20) provided in addition to 5)
The machine-readable recording medium according to any one of claims 19 to 26, further comprising a secondary cache access step in which access is made to the storage medium.