JP2000232457A - Radio communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption when radio communication is executed by a frame containing a control slot part and a data slot part and a processor processes a signal received through a slot in accordance with clock speed. SOLUTION: In the slave station of a radio LAN system, a control part 15 as a radio communication control means controls each of processing parts 11-14 and signal is communicated with a master station through a slot in a frame. A CPU 30 as a detection means executes a control program and detects a break between a control slot part and a data slot part based on the type of the received slot. The CPU 30 as a clock speed control means executes the control program, switches the clock speed of a clock oscillator 35. Clock speed is reduced in the break to the data slot part and clock speed is speeded up in the break to the control slot part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication apparatus for performing wireless communication using a frame including a control slot section and a data slot section and processing a received signal by a processor according to a clock speed. The present invention relates to a wireless communication device that keeps low.

[0002]

2. Description of the Related Art For example, in a wireless LAN system or a portable telephone system, TDMA (Time Divisio
n Multiple Access) / TDD (Time Division Duple)
2. Description of the Related Art Wireless communication of signals using frames in the x) format has been performed. Such a frame includes, for example, a control slot portion for transmitting a control signal and a data slot portion for transmitting a data signal, and a slave station or a master station processes a signal received through a slot by a microprocessor. Thus, the wireless communication between the two is controlled based on the control signal.

In the above-described system, for example, a plurality of slave stations provided in the system are divided into several groups, and a multi-frame composed of a plurality of frames corresponding to each group is used for communication. The slave station monitors only a specific frame corresponding to a group to which the slave station belongs, and performs reception processing to reduce power consumption. Specifically, for example, the slave station determines whether there is a signal to be processed by turning on the power at the timing of the frame corresponding to the group to which the slave station belongs,
If there is a signal to be processed, the signal is processed while the power is on, while if there is no signal to be processed, the power of each unit is turned off and waiting for the next frame, Attempts to reduce power consumption have been made.

[0004]

However, for example, in the above-mentioned slave station, the power control can be performed in units of frames in the receiving process by using the multi-frame as described above, but in a more detailed unit. Since power consumption control could not be performed, there was a problem that power consumption was not sufficiently reduced. Also,
In general, in a wireless communication device such as the above-mentioned slave station or the like, by reducing power consumption, it is possible to obtain effects such as a reduction in cost for power consumption and a reduction in size of the device due to a reduction in size of a battery. There is always a strong demand to further reduce the power consumption of the device.

The present invention has been made to solve such a conventional problem, and performs wireless communication using a frame including a control slot section and a data slot section, and transmits a signal received via the slot. It is an object of the present invention to provide a wireless communication device that can reduce power consumption when processing is performed by a processor according to a clock speed. More specifically, in the wireless communication device of the present invention,
By controlling the power consumption within the frame,
For example, it is possible to further reduce the power consumption as compared with the case where only the power supply control is performed in units of frames as shown in the above-described conventional example.

[0006]

In order to achieve the above object, a wireless communication apparatus according to the present invention performs wireless communication using a frame including a control slot section and a data slot section, and receives a signal via a slot. When a signal is processed by the processor according to the clock speed, the clock speed is controlled as follows. That is, when wirelessly communicating a signal via a slot by the wireless communication means, the detecting means detects a break between the control slot part and the data slot part based on the type of the received slot,
In response to the detection by the detection means, the clock speed control means reduces the clock speed at the break from the control slot to the data slot, while decreasing the clock speed at the break from the data slot to the control slot. Enhance.

Here, in the present invention, as an example, a frame of TDD communication shown in FIG. 8 can be used. In this frame configuration, one frame is composed of a plurality of types of control slots B, A1 to A4, R1 to R4. R12, a control slot section composed of G1 to G4 and a plurality of data slots DS1 to DS
S3 and a data slot section composed of DL, and one frame is divided into a first half control slot section and a second half data slot section. In the configuration of the frame shown in FIG. 8, a plurality of frames including such a control slot section and a data slot section are continuously arranged.

The control slots of the above-mentioned types, that is, control slot B, control slots A1 to A4, control slots R1 to R12, and control slots G1 to G4 are respectively a broadcast signal, a reception confirmation signal, a request signal, and a permission signal. The data slots DS1 to DS3 and DL are slots corresponding to the channel of the data signal. For example, one data slot DL has a longer slot length than the other data slots DS1 to DS3. Have been.

A burst header (BH) for performing, for example, bit synchronization is attached to the beginning of each slot, and each type of signal is included after the burst header. In the frame configuration shown in FIG. 8, various types can be used for the number of control slots of each type, the length of each data slot, and the like. Further, the configuration of the above-described frame will be described in more detail in embodiments described later.

In the wireless communication apparatus of the present invention, when wireless communication is performed using the above-described frame, for example,
The signal received by the wireless communication means is fetched into the memory by direct memory access (DMA), and the signal fetched into the memory is processed by the processor, thereby, for example, when the clock speed of the processor is low. This also guarantees the speed of loading the received signal into the memory to a practically effective level. In addition,
For example, the same security can be obtained even in a configuration in which a sub-processor that performs processing for storing a received signal in a memory separately from the above-described processor is provided in the device.

In the wireless communication apparatus of the present invention, as an example of the above-described control of the clock speed, when the detecting means detects the burst header of the control slot B located at the head of the control slot part, the control means starts the data slot part. When the clock speed control means increases the clock speed on the assumption that a break to the control slot has been detected, and when the detection means detects the control slot G4 located at the end of the control slot, the control slot changes to the data slot. The clock speed control means decreases the clock speed assuming that a break of the clock is detected.

In a wireless communication device, for example, it is required to control the current wireless communication in real time. Therefore, each type of control signal received through a control slot is transmitted by a data signal received through a data slot. Although the processor is required to process at a higher speed than that of the above, even if the processor processes the data signal at a relatively low speed, it does not cause a delay in communication control or the like. For this reason, in the wireless communication device, for example, in a control slot portion in which a control signal to be processed by the processor is received at a relatively short time interval, the clock speed is increased to perform high-speed processing by the processor, while the control slot portion and the next Even if the clock speed is reduced in the data slot portion between the control slot portion and the low-speed processing by the processor, the wireless communication as a whole does not cause a problem.

As described above using an example of the embodiment of the present invention, in the present invention, the clock speed is set to be relatively high in a time zone where relatively high-speed signal processing is required in one frame. On the other hand, the clock speed is set to be relatively low during a time period in which no trouble occurs even with relatively low-speed signal processing, so that, for example, the clock speed is lower than when the clock speed control process according to the present invention is not performed. And the power consumption when the processing speed of the processor is reduced by lowering the power consumption can be reduced. As a result, the power consumption of the entire apparatus can be reduced as a whole.

If the clock speed control processing according to the present invention is used together with the power supply control processing in units of frames shown in the above-mentioned conventional example, the effect of further reducing power consumption can be obtained. The specific configuration example and the like of the wireless communication device of the present invention described above will be described in more detail in the embodiments described later.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described with reference to the drawings. In this example, a case is shown in which the wireless communication device according to the present invention is applied to a slave station (UM: User Module) of a wireless LAN system. FIG. 1 shows a configuration example of a wireless LAN system including slave stations 2a to 2c to which the present invention is applied. In this wireless LAN system, a master station (CM:
Control Module) 1, slave stations 2a to 2c, backbone network 3 connected to master station 1, and slave stations 2a to 2
c and data processing devices P1 to P3 connected via PC card bus interfaces F1 to F3.

Here, each of the data processing devices P1 to P3 is composed of, for example, a node type personal computer having a PC card slot.
1 to P3 are connected to the respective slave stations 2a to 2c by the PC card bus interfaces F1 to F3 through the PC card slots.
2c is connected one-to-one.

In the wireless LAN system shown in FIG. 1, for example, TDMA is used between the master station 1 and the slave stations 2a to 2c.
Wireless communication is performed using a frame of the / TDD format. In this example, the frame shown in FIG. 8 is used as this frame. As described above, in the frame configuration of the present example shown in the drawing, one frame is divided into two by the control slot part in the first half and the data slot part in the second half. Are consecutively arranged. The control slot section includes one broadcast slot B, four reception confirmation slots A1 to A4, twelve request slots R1 to R12, and four permission slots G1.
To G4 are included in the order of description, and the data slot portion includes four data slots DS1 to DS3 and DL in the order of description.

In broadcast slot B, master station 1 to slave stations 2a-
A notification signal is transmitted to the slave station 2a.
To 2c. In the reception acknowledgment slots A1 to A4, a reception acknowledgment signal is transmitted from a station that has received the data signal or the like to a station that has transmitted the data signal or the like, and the reception acknowledgment signal is, for example, an ACK indicating that the signal has been normally received. It is composed of a signal containing data or NAK data indicating that signal reception was not performed normally.

In the request slots R1 to R12, the slave stations 2a to 2a
A request signal is transmitted from the base station 2c to the master station 1, and this request signal is used to assign a slot for performing wireless communication (ie, uplink communication) from the slave stations 2a to 2c to the master station 1 for example. From the signal containing the data requested for

In the permission slots G1 to G4, a permission signal is transmitted from the master station 1 to the slave stations 2a to 2c. The permission signal is used, for example, to permit wireless communication in response to a request signal received from the slave stations 2a to 2c. Notifying the slave stations 2a to 2c of a signal including data to be notified to the slave stations 2a to 2c or performing wireless communication (ie, downlink communication) from the master station 1 to the slave stations 2a to 2c. Signal containing data to be
Further, it is composed of a signal including data for notifying the slave stations 2a to 2c of the slot position assigned to the wireless communication performed between the master station 1 and the slave stations 2a to 2c.

In the data slots DS1 to DS3 and DL, data signals are transmitted from the master station 1 and the slave stations 2a to 2c to the other stations (ie, the slave stations 2a to 2c and the master station 1).
The data signals include, for example, various data signals communicated between the data processing devices P1 to P3 connected to the slave stations 2a to 2c and other data processing devices. In this example, the slot length of one data slot DL is set longer than the other three data slots DS1 to DS3.

In the frame of this embodiment, each of the control slots B, A1 to A4, R1 to
R12, each of the data slots DS1 to DS3, D included in the data slot portion is compared with the slot length of G1 to G4.
The slot length of L is set relatively long.

Further, as described above, each slot B, A1
~ A4, R1 ~ R12, G1 ~ G4, DS1 ~ DS3,
In the DL, a burst header is added to the head of each type of signal, and a burst header having a configuration common to all slots, for example, is used. Specifically, in this example, the burst header includes, for example, a guard time signal for securing time for the master station 1 and the slave stations 2a to 2c to switch the communication direction (transmission / reception) for each slot, and a bit synchronization signal. , A channel synchronization signal for establishing channel synchronization, and the like.

Further, each slot B, A1 to A4,
R1 to R12, G1 to G4, DS1 to DS3, and DL include, for example, a burst header and type information indicating the type of the slot in each type of signal, and an identifier assigned to the station that is the transmission source of the signal ( ID) and information on an identifier assigned to a station to which the signal is to be transmitted.

Using the above-described TDD communication frame, between the master station 1 and the slave stations 2a to 2c in this example, the master station 1 notifies the existence of the slave stations 2a to 2a through the notification slot B, for example.
2c, while the slave station 2a receives the notification.
2c to request slots R1-R
12 and notifies the master station 1 of the request.
Assigns a slot to be used for communication with the slave stations 2a to 2c, and assigns the slot corresponding to the assignment.
To the corresponding slave stations 2a to 2c through G4 to G4 so that the assigned data slots DS1 to DS3, D
A data signal is transmitted from the slave stations 2a to 2c to the master station 1 via L.

In the wireless communication from the master station 1 to the slave stations 2a to 2c, for example, the master station 1 allocates slots to be used for the wireless communication and sets the permission slots G1 to G4 corresponding to the allocation and the start of the communication. By notifying the slave stations 2a to 2c via the data slots DS1 to DS2.
A data signal is transmitted from master station 1 to slave stations 2a to 2c via DS3 and DL. As described above, in this example, the master station 1 manages the identifiers and the like of the slave stations 2a to 2c existing in the communicable area and allocates slots used for communication, etc. Wireless communication is performed.

In the wireless LAN system of the present embodiment, a plurality of master stations 1 are connected via a backbone network 3, and the master station 1 not only communicates with the slave stations 2a to 2c accommodated by itself, but also For example, a data signal wirelessly received from the slave stations 2a to 2c is transmitted to another master station accommodating the slave station serving as a destination of the signal via the backbone network 3, while the data signal addressed to the slave station 2a to 2c accommodated by the self station is transmitted. A data signal is received from another master station via the backbone network 3, and the received data signal is transmitted to the corresponding slave station 2a to 2b.
2b is wirelessly transmitted.

In the slave stations 2a to 2c of this embodiment, for example, data signals received from the connected data processing devices P1 to P3 via the PC card bus interfaces F1 to F3 are addressed to other slave stations. 1, while transmitting data signals wirelessly received from the master station 1 to the connected data processing devices P1 to P3 via the PC card bus interfaces F1 to F3.

Next, specific configuration examples and operation examples of the slave stations 2a to 2c and the master station 1 will be described with reference to the drawings. Each slave station 2a provided in the wireless LAN system according to the present embodiment.
Since the configurations and operations of 2c to 2c are the same, for convenience of explanation, these will be collectively referred to as the slave station 2 and described below. Similarly, in this example, the configurations of the PC card bus interfaces F1 to F3 are the same, and the configurations of the data processing devices P1 to P3 are the same. F and the data processing device P will be described.

FIG. 2 shows an example of the configuration of the above-mentioned slave station 2. The slave station 2 has an antenna unit 11 having an antenna or the like and a B which performs error correction processing of a radio communication signal.
A B section (baseband processing section) 12, an IF section 13 for performing modulation / demodulation processing of a baseband signal, an RF section 14 for performing transmission / reception processing of a radio signal, and control of these sections 11 to 14 and signal processing; And a control unit 15 for performing the control.

The antenna section 11 includes a 6-sector antenna section T1 composed of, for example, six sector antennas having a directivity of 60 °, and a switch section 21 for switching between these sector antennas. Six sector antennas cover wireless communication in a 360 ° area. In this example, when the wireless communication between the slave station 2 and the master station 1 is started, for example,
Among the sector antennas of the sector antenna unit T1, an antenna having a good communication state is switched and used for wireless communication.

The BB section 12 includes a communication control section 22 for controlling transmission / reception, a transmission processing section 23 for performing error correction processing of a signal to be transmitted, and a reception processing section for performing error correction processing and the like of a received signal. 24 are provided. For example, in the process of transmitting a signal, the communication control unit 22 inputs a signal to be transmitted as a parallel signal from the FIFO unit 33 of the control unit 15, controls the transmission of the input signal, converts the signal into a serial signal, and then performs the transmission process. The transmission processing unit 23 performs error correction processing using an FEC encoder or the like, encryption processing using a scrambler, processing for adding a synchronization signal using a logic circuit, and the like to the input signal. The signal subjected to these processes is converted into a parallel signal and output to the modulation / demodulation unit 25 of the IF unit 13. In the scrambler processing, for example, zero suppression of a baseband signal and secrecy are ensured.

For example, in the process of receiving a signal, the reception processing unit 24 inputs a signal wirelessly received by the antenna unit 11 from the modem unit 25 of the IF unit 13 as a parallel signal, and converts the input signal into a serial signal. And store it in a buffer, detect a synchronization signal by a logic circuit, and perform a decryption process by a descrambler, an error correction process by an FEC decoder, etc. on the signal stored in the buffer, and perform these processes. The applied signal is output to the communication control unit 22.
Then, reception control of the input signal is performed based on the result of the synchronization detection described above, whereby the signal is converted into a parallel signal and output to the FIFO unit 33 of the control unit 15.

In the BB section 12 of this embodiment, the IF section 13
From the communication control unit 22 to the control unit 1
5 has a function of performing a transfer process by direct memory access (DMA transfer process) in accordance with an instruction from the CPU 30 when outputting the data to the FIFO unit 33 of the first FIFO unit 33 by a first-in first-out (FIFO) method. The data of the received signal output from the BB unit 12 is directly transmitted to and stored in a memory such as the RAM 31 without passing through the CPU 30.

In the BB section 12 of the present embodiment, for example, the reception processing section 24 detects the bit synchronization signal or the channel synchronization signal of the burst header added to the slot, thereby establishing the synchronization of the reception signal. The communication control unit 22 has a function of causing the CPU 30 of the control unit 15 to generate an interrupt (transfer start interrupt). Further, in the BB unit 12 of the present embodiment, for example, when the above-described DMA transfer is completed for a signal received through a slot,
The communication control unit 22 has a function of generating an interrupt (transfer end interrupt) for the communication control unit 30. The processing of the CPU 30 performed by these interrupts will be described later.

The IF unit 13 includes a modulation / demodulation unit 25 for performing modulation / demodulation processing of a baseband signal (digital signal in this example).
And an oscillating unit 26 that oscillates a signal for generating a communication carrier. The oscillating unit 26 includes, for example, an oscillator and a PLL (Phase Lock Loop), and outputs a signal oscillated from the oscillator to the PLL. The signal is output to the modulation / demodulation unit 25 and the carrier generation unit 27 of the RF unit 14 via the communication unit.

For example, in the process of transmitting a signal, the modulation / demodulation unit 25 modulates the signal to be transmitted, which is input from the transmission processing unit 23 of the BB unit 12, with a modulator and sends the modulated signal to the mixing / separating unit 28 of the RF unit 14. Output is done. For example, in the process of receiving a signal, the modem unit 2
In 5, the signal wirelessly received by the antenna unit 11 is transmitted to the RF unit 1.
4 is input from the mixing / separating unit 28, and the input signal is demodulated by the demodulator and output to the reception processing unit 24 of the BB unit 12. The modulation / demodulation unit 25 of the present embodiment includes, for example, a switch that switches between transmission processing and reception processing, and performs modulation processing and demodulation processing according to the communication state of a signal oscillated from the oscillator of the oscillation unit 26 and a wireless signal. Is controlled.

The RF section 14 includes a carrier generation section 27 for generating a communication carrier (for example, a millimeter wave) and a mixing section for mixing and separating a modulated baseband signal (modulated signal) and a communication carrier. A transmission / reception switching unit 29 for switching transmission / reception processing is provided. Here, the carrier generation unit 27 generates a communication carrier by multiplying the frequency of the signal oscillated from the oscillation unit 26 of the IF unit 13 by a multiplier using a constant, and amplifies the generated communication carrier by an amplifier through a filter. The output to the mixing / separating unit 28 is performed.

For example, in the process of transmitting a signal, the mixing / separation unit 28 mixes the modulated signal to be transmitted input from the modulation / demodulation unit 25 of the IF unit 13 with a communication carrier, and performs the communication process after the mixing process. The carrier is output to the transmission / reception switching unit 29, and the transmission / reception switching unit 29 switches to transmission processing by a switch,
Is output to the antenna unit 11, and a signal to be transmitted is wirelessly transmitted as an electric wave from the antenna of the antenna unit 11 by such processing.

In a process of receiving a signal, for example, the transmission / reception switching unit 29 switches to a reception process, inputs a signal wirelessly received by the antenna unit 11 as a modulated communication carrier, and inputs the received communication carrier. mixture·
The output to the separation unit 28 is performed, and the mixing / separation unit 28
Then, a received signal (that is, a modulated signal) is separated from the input communication carrier, and the separated signal is separated into an IF unit 1.
3 is output to the modulation / demodulation unit 25.

Here, in this example, the BB unit 1 described above is used.
2, the IF unit 13, the RF unit 14, and the antenna unit 11 perform wireless communication of signals with the master station 1 via each slot under the control of the control unit 15, thereby wirelessly communicating signals via the slots. Wireless communication means is configured.

The control unit 15 includes a CPU 30 for executing various arithmetic processes, a RAM 31 for storing data to be processed, and a ROM 32 for storing control programs and the like.
And the communication control unit 2 of the BB unit 12 by the first-in first-out method.
2 and a PC card interface unit 34 connected to the PC card bus interface F. Here, the PC card interface unit 3
Reference numeral 4 includes, for example, a RAM as a buffer, and has an interface function of transmitting and receiving data signals and the like to and from a data processing device P connected via a PC card bus interface F.

In the present embodiment, the above-described ROM 32 is constituted by, for example, a flash ROM, and stores a control program for executing various processes performed in the slave station 2. Further, in this example, the CPU 30 has a ROM
By executing the control program stored in the RAM 32 in the RAM 31 and executing the same, various processes are performed in accordance with the control program, thereby controlling, for example, the processing units 11 to 14 as described above, The control of the wireless communication process with the station 1 is performed.

Here, the CPU 30 of this embodiment is configured as, for example, a microprocessor (MPU).
Various processes by the PU 30 are performed according to the speed (clock speed) of the operation clock signal oscillated from the clock oscillator 35 built in the CPU 30. Further, the clock oscillator 35 of the present embodiment has a function of changing the speed of the operation clock signal oscillating according to the control of the CPU 30. In the CPU 30 of the present embodiment, for example, when the clock speed is increased, the processing speed is also increased. When the clock speed is reduced, the processing speed is also reduced and the power consumption is reduced.

As the control of the above-mentioned radio communication processing, specifically, the CPU 30 receives the control signal received from the master station 1 via the notification slot B and the permission slots G1 to G4 in the frame shown in FIG. It analyzes the slot and the like allocated to the communication, and sends a request for wireless communication to the master station 1 through the request slots R1 to R12.
Wirelessly transmitted to the reception
The reception status of the signal with the master station 1 via A4 is checked. The CPU 30 transmits a data signal received from the master station 1 via the data slots DS1 to DS3 and DL from the PC card interface unit 34 to the external data processing device P, or transmits the data signal from the data processing device P to the PC card. Data slot DS1 to which the data signal received via interface unit 34 is assigned
To perform wireless transmission to the master station 1 via DS3 and DL.

Here, the CPU 30 of the present embodiment uses the B
In response to detecting the transfer start interrupt performed by the B unit 12, the type of the slot corresponding to the signal for which synchronization has been established by the BB unit 12 is determined, and the transfer address corresponding to the determined slot type is determined. By setting the transfer size and instructing the BB unit 12, the BB unit has a function of activating the DMA transfer process described above. The CPU 30 of the present embodiment causes the RAM 31 to store, for example, data of a signal received subsequent to a burst header in various slots in accordance with the instruction to the BB unit 12.

Further, the CPU 30 of the present embodiment uses the BB
In response to the detection of the transfer end interrupt performed by the unit 12, the DMA transfer process of the BB unit 12
A function of determining the slot type of the data stored in No. 1 (that is, the slot type of the signal that received the data) and analyzing the data (that is, the signal received via the slot) according to the determined slot type have.

In such data analysis processing, for example, since the CPU 30 controls the wireless communication processing in real time, if the CPU 30 completes the analysis of the reception data corresponding to a certain slot, the following processing is performed. When the DMA transfer processing of the reception data corresponding to the slot is completed, the reception data corresponding to the next slot may be missed. In order to avoid such a problem, the CPU 30 of the present embodiment
The analysis of data received via a certain slot must be completed before a transfer end interrupt occurs for the next data to be analyzed.

As an example, FIG. 3 conceptually shows the timing of occurrence of an interrupt in a frame, and as shown in FIG.
H), the transfer start interrupt is generated and the transfer end interrupt is generated by the end of the DMA transfer of the various data (channel data) in the slot, and the CPU 30 analyzes certain received data. The processing must be completed before a transfer end interrupt for the next received data to be analyzed occurs.

Here, as described above, in this example, the data received through the broadcast slot B, the reception confirmation slots A1 to A4, and the permission slots G1 to G4 are received through the data slots DS1 to DS3 and DL. It is required that the CPU 30 perform processing at a higher speed than data. For this reason, a control slot unit in which control data (control signal) requiring relatively high-speed analysis processing is received at short time intervals is compared with a data slot unit in which control data is received at relatively long time intervals. It is necessary to increase the operation speed of the CPU 30.
Even if the analysis processing is performed at a relatively low speed by 30, no problem occurs in the communication control.

In the slave station 2 of the present embodiment, the power consumption is reduced by utilizing the above-described features.
Has a function of switching the speed of the operation clock signal oscillated from the clock oscillator 35 between high speed and low speed according to the control program. Specifically, the CPU 30 of this example
In the above, the slot type determined in response to the detection of the above-described transfer start interrupt is the notification slot B (that is,
(The first slot in the control slot section), the speed of the operation clock signal is switched to high speed, and the slot type determined in response to the detection of the transfer end interrupt is the fourth permission slot G4. (That is,
(The last slot in the control slot section), the speed of the operation clock signal is switched to a low speed.

In this example, the positions of the notification slot B and the fourth permission slot G4 are regarded as the position of the boundary between the control slot portion and the data slot portion based on the slot type determined by the CPU 30 as described above. Detecting means for detecting a break between the control slot section and the data slot section based on the type of the received slot.

The method of detecting the break is not particularly limited, and is not limited to a mode in which all the types of each slot in the frame are determined to detect the break as in this embodiment. When the slot configuration in a frame is constant as in the example, the break is monitored by monitoring the time lag and the bit number lag from the slot based on the specific slot whose type is determined in the frame. It can also be detected. Further, the type of the slot is determined based on, for example, type information included in the slot.

In this embodiment, the CPU is operated as described above.
30 switches the speed of the operation clock signal to high speed in response to the detection of the break in the notification slot B, while switching the speed of the operation clock signal to low in response to the detection of the break in the fourth permission slot G4. Thus, in response to the detection by the detection means described above, the clock speed is reduced at the boundary between the control slot portion and the data slot portion, while the clock speed is increased at the boundary between the data slot portion and the control slot portion. Speed control means is provided. The speed of the operation clock that can be switched between low speed and high speed may be set to any speed as long as the processing of the control signal and the data signal is performed without delay.

With the above configuration, in the slave station 2 of this example, signals are wirelessly communicated with the master station 1 using a frame including a control slot section and a data slot section, and various control slots are controlled. The CPU 30 processes the signals received through the CPU 30 and the data slots according to the clock speed.

FIG. 4 shows an example of the configuration of the above-described master station 1. The master station 1 has an antenna section 41 and a BB section substantially similar to those provided in the slave station 2 described above. 42, an IF unit 43, an RF unit 44, and a control unit 45 for controlling these units 41 to 44 are provided. Here, the antenna section 41 of the master station 1 of this example includes a 12-sector antenna section T2 composed of 12 sector antennas having a directivity of 30 °, for example, and a switch section 51 for switching these sector antennas. And a 360 ° service area (communicable area) is formed by 12 sector antennas.

The BB unit 42, the IF unit 43, and the RF unit 44 of the master station 1 of the present embodiment have the respective processing units 12 of the slave station 2 described above.
Functional units 52 to 5 substantially similar to those provided in
9 are provided, and the processing units 42 to 4 of the master station 1 are provided.
4 and the processing operation performed by the antenna unit 41 are the same as in the case of the slave station 2 described above, and a description thereof will be omitted in this example.

The control section 45 of the master station 1 of this embodiment includes a CPU 60 for executing various arithmetic processing, a RAM 61 for storing data to be processed, a ROM 62 for storing a control program and the like. Communication control unit 52 of BB unit 42
And a LAN interface unit 64 connected to the backbone network 3.

With the above configuration, in the master station 2 of the present embodiment, for example, the CPU 60 expands the control program stored in the ROM 62 into the RAM 61 and executes the control program to control the wireless communication processing and the like. Wireless communication with the slave station 2 existing in the
It transmits and receives data signals and the like to and from another master station or the like connected by the backbone network 3 via the interface unit 64.

Next, an example of the procedure of the above-described clock speed control process performed by the slave station 2 of the present embodiment will be described with reference to the drawings. FIG. 5 shows an example of a procedure of the reception transfer start interruption process performed by the CPU 30 of the control unit 15 in response to the occurrence of the transfer start interruption in the BB unit 12 described above.

That is, when the reception / transfer activation interrupt processing is started (step S1), the CPU 30 determines the type (channel type) of the slot for which synchronization has been established by the burst header (step S2). Is determined to be the notification slot B (Bch: B channel), the speed of the operation clock signal oscillated from the clock oscillator 35 is switched to a high speed and set (step S5), and then the type of the slot B is determined. The transfer address and transfer size are set according to the
Starts the DMA transfer (step S3), and ends the interrupt processing (step S4).

On the other hand, if it is determined by the above determination that the slot type is other than the notification slot B, the transfer address and the transfer size are determined according to the type of the slot without switching the speed of the operation clock signal. Is set, and the BB unit 12 starts the DMA transfer (step S3), and terminates the interrupt processing (step S3).
4).

FIG. 6 shows that the CPU 3 of the control unit 15 responds to the occurrence of the transfer end interrupt in the BB unit 12 described above.
0 shows an example of the procedure of the reception transfer end interrupt processing performed by 0. That is, when the reception transfer end interruption processing is started (step S11), the CPU 30 determines the type (channel type) of the slot for which the DMA transfer has been completed (step S12), and thereby the fourth slot is permitted. When it is determined that the slot G4 is the slot G4 (G4ch: G4 channel), the speed of the operation clock signal oscillated from the clock oscillator 35 is switched to a low speed and set (step S15). The data of the received signal is analyzed (step S13), and the interrupt processing ends (step S14).

On the other hand, if it is determined by the above determination that the slot type is other than the permitted slot G4, the speed of the operation clock signal is not switched and the signal received according to the type of the slot is not changed. The data is analyzed (step S13), and the interrupt process ends (step S14).

FIG. 7 schematically shows the switching of the clock speed within a frame realized by performing the above-described interrupt processing. As shown in FIG. In CP 2, during the period from when the synchronization is established by the burst header in the broadcast slot B to when the DMA transfer of the data of the fourth permission slot G4 is completed, the CP
By increasing the operating clock of U30, the CP
While the processing speed of U30 is increased, the operation of the CPU 30 is performed until the synchronization of the notification slot B in the next frame is established after the DMA transfer of the data of the fourth permission slot G4 is completed. By reducing the clock, the processing speed of the CPU 30 is reduced.

As described above, in the slave station 2 of the present embodiment, the clock speed is set relatively high in the time zone where relatively high-speed signal processing is required in the frame, while the relatively low-speed signal is set. Since the clock speed is set relatively low in a time zone in which no trouble occurs even in the processing, the clock speed is set low and the power consumption in the time zone in which the processing speed of the processor (the CPU 30 in this example) is reduced is suppressed. As a result, it is possible to reduce the power consumption as a whole and reduce the cost as a whole. Further, such a clock speed control process can be used together with, for example, the power supply control process in units of frames shown in the above-described conventional example, so that the effect of further reducing power consumption can be obtained.

In the present embodiment, as a preferable mode, a frame divided into two by a control slot section and a data slot section is used as a frame for wireless communication performed by the slave station 2. The switching process of the clock speed need only be performed once in one frame, and such a switching process can be performed efficiently. Further, in the present example, as a preferable mode, a signal wirelessly received by the slave station 2 is stored in a memory by DMA transfer. For example, even when the processing speed of the CPU 30 is reduced, the communication processing of the wireless signal is performed. Can be performed without any trouble.

When the present invention is applied to a wireless communication device incorporating a battery, a battery, or the like, for example, by reducing power consumption as described in the above embodiment, a battery or the like provided in the device can be reduced in size. Can also be
Thus, the size of the apparatus can be reduced.

Here, in the above embodiment, as an example of a mode of switching the clock speed by detecting a boundary between the control slot portion and the data slot portion in the frame, the synchronization of the first slot in the control slot portion is established. The clock speed is switched between the time when the transfer is performed and the time when the DMA transfer of the last slot is completed. However, if the processing of the control signal and the data signal is performed without any trouble, the timing of switching the clock speed may be slightly changed. It may be set to be shifted back and forth. In short, the power consumption can be reduced by lowering the clock speed at a predetermined portion in the frame to lower the processing speed of the processor.

The structure of the frame used for the wireless communication does not necessarily have to be the structure shown in FIG. 8, for example, the number of control slots of each type, the number of data slots, the slot length, etc. Various configurations can be used for. Further, in the above embodiment, a case where a microprocessor is used as a processor for processing signals has been described. However, various processors may be used. In short, the processing speed is reduced by lowering the clock speed. It suffices if the power consumption can be reduced by reducing the power consumption.

In the above embodiment, the processor executes the control program in the hardware resources including the processor and the memory, so as to control the wireless communication processing and the clock speed switching processing. In the present invention, the configuration of each functional means for performing these processes is, in short, a configuration in which a clock speed can be switched at a boundary between a control slot portion and a data slot portion in a frame by performing wireless communication. If so, any configuration may be used.

In the above embodiment, the case where the wireless communication apparatus according to the present invention is applied to a slave station of a wireless LAN system has been described. However, the present invention is not necessarily limited to a slave station of a wireless LAN system. It can be applied to various wireless communication devices, for example, it can be applied to a wireless communication device provided in a public wireless access service system such as a mobile phone system, or, for example, wireless communication that performs one-to-one wireless communication It can also be applied to devices.

[0073]

As described above, according to the radio communication apparatus of the present invention, radio communication is performed using a frame including a control slot section and a data slot section, and a signal received via a slot is processed by a processor. When processing according to the clock speed, the clock speed is switched at the boundary between the control slot portion and the data slot portion, thereby causing the processor to execute low-speed processing in a time zone where high-speed processing is relatively not required. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a wireless LAN system including a slave station to which the present invention has been applied.

FIG. 2 is a diagram illustrating a configuration example of a slave station.

FIG. 3 is a diagram showing the occurrence of an interrupt within a frame.

FIG. 4 is a diagram illustrating a configuration example of a master station.

FIG. 5 is a diagram illustrating an example of a procedure of a reception transfer activation interrupt process.

FIG. 6 is a diagram illustrating an example of a procedure of a reception transfer end interruption process.

FIG. 7 is a diagram showing switching of a clock speed within a frame.

FIG. 8 is a diagram illustrating a configuration example of a frame.

[Explanation of symbols]

1. master station, 2a to 2c slave station, 3. backbone network, F1 to F3 PC card bus interface, P1 to P3 data processing device, 11.
・ Antenna part, 12 ・ ・ BB part, 13 ・ ・ IF part,
14. RF section, 15 control section, T1 6 sector antenna section, 21 switch section, 22 communication control section, 23 transmission processing section, 24 reception processing section, 2
5 ··· Modulation / demodulation unit, 26 ··· oscillation unit, 27 ··· carrier generation unit, 28 ··· mixing / separation unit, 29 ··· transmission / reception switching unit, 30 ··· CPU, 31 ·· RAM, 32 ···
ROM, 33..FIFO section, 34..PC card interface section, 35..Clock oscillation section, B..Notification slot, A1 to A4..Reception confirmation slot, R1
... R12 request slot, G1 to G4 permission slot, DS1 to DS3, DL data slot,

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shunji Miura 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Inside Japan Telegraph and Telephone Corporation (72) Inventor Yoshifumi Suzuki 3-192 Nishi Shinjuku, Shinjuku-ku, Tokyo No. Nippon Telegraph and Telephone Corporation F term (reference) 5K033 AA04 CA11 CB15 CC02 DA17 DB11 DB16 DB25 5K067 AA43 BB21 CC04 EE02 EE10 GG11 HH21 HH22 KK13

Claims (1)

[Claims] 1. A wireless communication apparatus for performing wireless communication using a frame including a control slot section and a data slot section and processing a signal received via the slot in accordance with a clock speed by a processor, wherein the signal is transmitted via the slot. Wireless communication means for performing wireless communication; detection means for detecting a break between the control slot part and the data slot part based on the type of the received slot; and, from the control slot part to the data slot part in response to the detection of the detection part. And a clock speed control means for increasing the clock speed at the break from the data slot to the control slot while reducing the clock speed at the break.