JP2000232438A - Frame synchronizing device/method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid synchronism failure and erroneous synchronism without raising the redundancy of a unique word. SOLUTION: A GOLAY decoding circuit 205 executes GOLAY decoding on the candidate part of the header of a reception signal stored in a buffer and counts the number of erroneous bits. A threshold control circuit 206 controls the threshold of a synchronism decision circuit 207 on the basis of the counted number of erroneous bits. A unique word(UW) comparison circuit 204 calculates the correlation value between the candidate part of the unique word of the reception signal stored in the buffer 202 and a unique word inputted from the UW generation circuit 203. The synchronism decision circuit 207 compares the sizes of the correlation value inputted from the UW comparison circuit 204 and the threshold controlled by the threshold control circuit 206. When the correlation value is larger than the threshold, the candidate part of the unique word of the reception signal is decided to be the real unique word.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization device and a frame synchronization method used for a communication system such as data communication and multimedia communication.

[0002]

2. Description of the Related Art In a communication system such as data communication or multimedia communication, it is necessary to establish synchronization when starting communication between devices. Hereinafter, a conventional frame synchronization apparatus will be described with reference to a block diagram shown in FIG.

In FIG. 6, a received signal in which a unique word (hereinafter, referred to as “UW”) known between communication devices is inserted at the end of a frame is temporarily stored in a buffer 12 via an input terminal 11. Are output to the UW comparison circuit 14 as UW candidates. At the same time, the UW generated by the UW generation circuit 13 is also output to the UW comparison circuit 14.

In the UW comparison circuit 14, the U
A correlation value between the candidate portion of W and UW is calculated, and the calculated correlation value is output to the synchronization determination circuit 15. Note that the correlation value is the number of bits that match between two bit strings.

[0005] In the synchronization determination circuit 15, the correlation value is compared in magnitude with a preset threshold value, and a portion where the correlation value exceeds the threshold value is determined as the UW of the received signal.

As described above, the conventional frame synchronizer is
The portion where the correlation value with the UW exceeds the threshold value is determined as the UW portion of the received signal, whereby the leading end of the frame is detected and the frame synchronization is established.

[0007]

However, in the conventional frame synchronizer, if the threshold value is fixed, the propagation environment is poor, and a code error occurs on the transmission line, the UW is not detected or erroneously detected, and the synchronization is lost. Or erroneous synchronization may occur. In order to improve this, if the propagation environment is poor, U
It is necessary to increase the redundancy by increasing W, and the transmission efficiency is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and has as its object to provide a frame synchronization apparatus and a frame synchronization method capable of avoiding loss of synchronization or erroneous synchronization without increasing the redundancy of the UW. And

[0009]

The gist of the present invention is that a threshold value is adjusted based on the number of error bits in a candidate portion of a header of a received signal, and a correlation value between the UW candidate portion of the received signal and UW is adjusted. If the threshold value is not less than the threshold value, it is determined that the UW candidate portion is actually UW.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A frame synchronizer according to a first aspect of the present invention provides a correlation between a known symbol candidate portion and a known symbol of a received signal in which a known symbol and a control symbol are inserted at predetermined positions of each frame. Correlation value calculation means for calculating a value, synchronization determination means for detecting a known symbol position of a received signal based on the magnitude relationship between the correlation value and the threshold value, and threshold adjustment for adjusting the threshold value based on information on a control symbol candidate portion Means is provided.

According to a second aspect of the present invention, there is provided the frame synchronization apparatus according to the first aspect, wherein the control symbol candidate portion of the received signal in which the control symbol is error correction encoded is decoded to count the number of error bits. Means, and the threshold adjusting means adjusts the threshold value lower as the number of error bits is smaller.

According to a third aspect of the present invention, in the frame synchronization apparatus according to the first aspect, a control symbol candidate portion of a next frame of a received signal including an error check bit in a control symbol is decoded to check the error check bit. The apparatus is provided with a first error checker, and the threshold adjuster adjusts the threshold lower when no error is detected.

According to a fourth aspect of the present invention, in the frame synchronization apparatus according to any one of the first to third aspects, the synchronization determining means determines that the correlation value is larger than the adjusted threshold value and that a synchronization error is detected from the other. If no signal is input, it is determined that the known symbol candidate portion is a known symbol, otherwise,
A configuration is adopted in which the known symbol candidate portion is determined not to be a known symbol.

With these configurations, the threshold value can be adaptively changed based on the information written in the control symbol. Therefore, even when the propagation environment is poor, the redundancy of the known symbol can be accurately increased without increasing the redundancy. The end of the frame can be detected.

According to a fifth aspect of the present invention, in the frame synchronization apparatus of the fourth aspect, the control symbol candidate portion of the current frame of the received signal including the error check bit in the control symbol is decoded to check the error check bit. And a second error checker that outputs a signal indicating a synchronization error to the synchronization determiner when an error is detected.

According to a sixth aspect of the present invention, in the frame synchronizer according to the fourth or fifth aspect, a first information bit indicating the type of packet data of the current frame and a second information bit indicating the type of packet data of the previous frame. It is determined whether or not the first information bit of the control symbol candidate portion of the current frame of the received signal whose information bit is included in the control symbol matches the content of the second information bit of the control symbol candidate portion of the next frame. A configuration is provided that includes a bit content determination unit that outputs a signal indicating a synchronization error to the synchronization determination unit when it is determined that they do not match.

According to a seventh aspect of the present invention, in the frame synchronization apparatus according to any one of the fourth to sixth aspects, the pattern of the known symbol differs depending on whether or not the packet data of the current frame extends to the next frame. Whether the pattern of the known symbol candidate portion of the received signal included in the control symbol and the content of the third information bit of the control symbol candidate portion match whether or not the third information bit indicating whether or not the packet data in the next frame covers the next frame , And a comparison means for outputting a signal indicating a synchronization error to the synchronization determination means when it is determined that they do not match is adopted.

With these configurations, it is possible to judge the suitability of the known symbol candidate portion of the received signal based on the information written in the control symbol, so that the frame can be more accurately determined without increasing the redundancy of the known symbol. The tip can be detected.

According to an eighth aspect of the present invention, in the frame synchronizer according to any one of the first to seventh aspects, the synchronization determining means determines that the known symbol candidate portion is known when the correlation value is larger than an initially set threshold value. A configuration is adopted in which a symbol is uniquely determined.

With this configuration, when the propagation environment is good,
Since a known symbol can be specified without adjusting the threshold, the frame synchronization processing time can be reduced.

A wireless communication apparatus according to a ninth aspect of the present invention employs a configuration in which the frame synchronization apparatus according to any one of the first to eighth aspects is mounted.

According to this configuration, even when the propagation environment is poor, the leading end of the frame can be detected accurately without increasing the redundancy of the known symbols, so that the quality can be maintained without lowering the transmission efficiency of wireless communication. it can.

A frame synchronization method according to a tenth aspect of the present invention calculates a correlation value between a known symbol candidate portion of a received signal in which a known symbol and a control symbol are inserted at a predetermined position of each frame, and the known symbol. Adjusting the threshold value based on the information of the control symbol candidate portion, and when the correlation value is larger than the threshold value, it is determined that the known symbol candidate portion of the received signal is a known symbol, and the leading end of the frame of the received signal is detected. Take the method of doing.

According to an eleventh aspect of the present invention, in the frame synchronization method according to the tenth aspect, the control symbol candidate portion of the received signal in which the control symbol is subjected to the error correction code is decoded to count the number of error bits, A method of adjusting the threshold value lower as the number of error bits is smaller is adopted.

According to a twelfth aspect of the present invention, in the frame synchronization method of the tenth aspect, a control symbol candidate portion of a next frame of a received signal including an error check bit in a control symbol is decoded to check the error check bit. If no error is detected, a method of lowering the threshold is adopted.

According to these methods, the threshold value can be adaptively changed based on the information written in the control symbol. Therefore, even when the propagation environment is poor, the redundancy of the known symbol can be accurately increased without increasing the redundancy. The end of the frame can be detected.

According to a thirteenth aspect of the present invention, there are provided the tenth to first aspects.
2. In the frame synchronization method according to any one of aspects 2, the control symbol candidate portion of the received signal including the error check bit in the control symbol is decoded and the error check bit is checked, and if an error is detected, the known symbol candidate portion is known. A method of determining that it is not a symbol is adopted.

According to a fourteenth aspect of the present invention, in the frame synchronization method according to the thirteenth aspect, the first information bit indicating the type of packet data of the current frame and the second information bit indicating the type of packet data of the previous frame are different. If the first information bit of the control symbol candidate portion of the current frame of the received signal included in the control symbol does not match the content of the second information bit of the control symbol candidate portion of the next frame, the known symbol candidate portion is not a known symbol Is determined.

A fifteenth aspect of the present invention is directed to the thirteenth or first aspect.
In the frame synchronization method according to the fourth aspect, the pattern of the known symbol differs depending on whether the packet data of the current frame extends to the next frame, and the first information bit indicating whether the packet data of the current frame extends to the next frame is a control symbol. In the case where the pattern of the known symbol candidate portion of the received signal and the content of the first information bit of the control symbol candidate portion do not match, a method of determining that the known symbol candidate portion is not a known symbol is adopted.

According to these methods, the suitability of the known symbol candidate portion of the received signal can be determined based on the information written in the control symbol, so that the frame can be more accurately determined without increasing the redundancy of the known symbol. The tip can be detected.

According to a sixteenth aspect of the present invention, there are provided the tenth to first aspects.
In the frame synchronization method according to any one of the fifth to fifth aspects, a method is employed in which the known symbol candidate portion is uniquely determined to be a known symbol when the correlation value is larger than an initially set threshold value.

According to this method, when the propagation environment is good,
Since a known symbol can be specified without adjusting the threshold, the frame synchronization processing time can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a frame configuration of a signal received by the frame synchronizer of the present invention.

As shown in FIG. 1, a payload 101 carrying audio encoded data, video encoded data, and the like is divided into appropriate lengths, and a unique word (hereinafter, referred to as a “word”) is provided at the end of the divided payload 101. UW ”) 102,
The header 103 and the duplicate header 104 are inserted. Then, UW 102, header 103, duplicate header 104,
A frame is configured with the payload 101 as one unit.

The header 103 includes information indicating the length of the payload 101 of the current frame, and payload 1 of the current frame.
01 (hereinafter, referred to as the type of data written in
Data (referred to as “multiplexing information”),
AY encoded.

In the duplicate header 104, data such as multiplex information of the previous frame, packet marker (hereinafter referred to as "PM") information, CRC (Cyclic Redundancy Check) check bits and the like are written.

When packet data that does not fit in one frame is divided and written over a plurality of frames, UW is inverted and written in a frame that does not include the end of the divided packet data. “0” is written in the PM information of the duplicate header 104 of the frame. Also, UW is written as it is in other frames,
The PM information of the duplicate header 104 of the frame is “1”
Is written.

The frame synchronizer of the present invention has a header 10
3 and the information written in the duplicate header 104,
The frame synchronization is established by detecting the position of W102 and determining the leading end of the frame.

In the following description, a frame to be subjected to frame synchronization processing is called a current frame, and a frame received after the current frame is called a next frame. Further, the length of the payload 101 of each frame is variable, and the lengths of the UW 102, the header 103, and the duplicate header 104 are constant.

(Embodiment 1) FIG. 2 is a block diagram showing a configuration of a frame synchronization apparatus according to Embodiment 1 of the present invention.

In FIG. 2, a buffer 202 temporarily stores a received signal input from an input terminal 201.
The UW generation circuit 203 generates UW and outputs it to the UW comparison circuit 204.

The UW comparison circuit 204 compares the UW candidate portion of the received signal stored in the buffer 202 with the UW generation circuit 2
A correlation value with the UW input from step 03 is calculated, and the calculated correlation value is output to the synchronization determination circuit 207. Note that the correlation value is the number of bits that match between two bit strings.

The GOLAY decoding circuit 205 performs GOL decoding on the candidate portion of the header of the received signal stored in the buffer.
AY decoding is performed, the presence or absence of an error is detected, the number of erroneous bits is counted, and the count value that is the erroneous bit is output to the threshold adjustment circuit 206.

The threshold adjustment circuit 206 is a synchronization determination circuit based on the count value input from the GOLAY decoding circuit 205.
Adjust the threshold of 07. Specifically, when GOLAY decoding is correctly performed, the threshold is reduced to prevent loss of synchronization, and when an error is detected by GOLAY decoding, the threshold is increased to prevent false detection of synchronization.

The synchronization determination circuit 207 is provided by the UW comparison circuit 20.
4 is compared with the threshold value adjusted by the threshold adjustment circuit 206, and when the correlation value is larger than the threshold value, it is determined that the UW candidate portion of the received signal is actually UW, and the determination result is obtained. Is output from the output terminal 208 to an external device. If the correlation value is equal to or smaller than the threshold value, it is determined that the UW candidate portion of the received signal is not UW, and the determination result is
Output to the W comparison circuit 204 and the GOLAY decoding circuit 205.

Next, the processing of the frame synchronization apparatus according to the present embodiment will be described with reference to the flowchart of FIG.

First, a step (hereinafter, referred to as “ST”)
At 301, a received signal is taken into a buffer 202 via an input terminal 201.

Next, at ST302 and ST303, GO
The LAY decoding circuit 205 performs GOLAY decoding on the header candidate portion, detects the presence or absence of an error, counts the number of erroneous bits, and sets the GOLAY decoding in the threshold adjustment circuit 206.
The threshold of the synchronization determination circuit 207 is adjusted based on the count value input from the Y decoding circuit 205.

In ST 304, UW comparison circuit 204
, The UW candidate portion of the received signal and the UW generation circuit 203
A correlation value with the generated UW is calculated.

Next, in ST305, the synchronization judgment circuit 207
The magnitude of the correlation value is compared with the threshold value. If the correlation value is larger than the threshold, in ST306, it is determined that the UW candidate portion is actually UW 102, and the determination result is output from output terminal 208 to an external device.

If the correlation value is equal to or smaller than the threshold value in ST305, it is determined that the UW candidate portion is not UW 102, and a portion obtained by shifting the current UW candidate portion by one bit is set as a new UW candidate portion. The processing of ST302 and subsequent steps is repeated.

As described above, by adaptively changing the threshold value based on the information written in the header and specifying the UW, even if the propagation environment is poor, the UW redundancy can be accurately increased without increasing the redundancy of the UW. The end of the frame can be detected.

Although the present embodiment has been described using GOLAY decoding, the present invention is not limited to this, and other error correcting codes can be used.

Also, according to the present invention, before adjusting the threshold, the UW
The determination may be performed, and if the UW cannot be identified, the threshold may be adjusted and the UW determination may be performed again. In this case, when the propagation environment is good, the UW can be specified without adjusting the threshold, so that the frame synchronization processing time can be reduced.

(Embodiment 2) FIG. 4 is a block diagram showing a configuration of a frame synchronization apparatus according to Embodiment 2 of the present invention. Note that, in the frame synchronization apparatus of FIG.
The same reference numerals as in FIG. 2 denote the same parts as in FIG.

In FIG. 4, at the timing when a signal is input from the synchronization determination circuit 402, the UW comparison circuit 401 compares the UW candidate portion of the received signal stored in the buffer 202 with the UW generated by the UW generation circuit 203. Enter UW
And a correlation value between the candidate portion of UW and the inverted signal of UW (hereinafter referred to as a "second correlation value"). , The calculated correlation values are used as the synchronization determination circuit 402 and the PM comparison circuit 40.
5 is output.

The synchronization determination circuit 402 includes a UW comparison circuit 40
The magnitude of each of the correlation values input from 1 and the threshold value is compared, and if either correlation value is greater than the threshold value, it is determined that the UW candidate portion of the received signal is actually UW. Then, immediately before the threshold value is adjusted, the determination result is output to the output terminal 2 immediately.
08 to an external device, and after the threshold is adjusted, waits for a signal to be input from the CRC decoding circuit 404, and outputs the determination result from the output terminal 208 to the external device.

When both of the correlation values are equal to or smaller than the threshold value, the synchronization determination circuit 402 outputs a signal indicating the determination result to the GOLAY decoding circuit 403 before the threshold value is adjusted.
And outputs the signal to the CRC decoding circuit 404, and if the threshold value has been adjusted, the UW comparison circuit 4
Output to 01.

Further, when a signal is input from the CRC decoding circuit 404 or the PM comparison circuit 405, the synchronization determination circuit 402 outputs a signal for instructing the next processing to UW without comparing the magnitude of each correlation value with the threshold value. Output to the comparison circuit 401.

When the signal is input from the synchronization determination circuit 402, the GOLAY decoding circuit 403 performs GOLAY decoding on the candidate portion of the header of the received signal stored in the buffer, detects the presence or absence of an error, and The threshold value adjustment circuit 406 counts the number
Output to Also, it outputs information indicating the length of the payload and multiplexed information to the CRC decoding circuit 404.

[0062] The CRC decoding circuit 404
When a signal is input from 02, CRC decoding is performed on the candidate portion of the duplicate header of the current frame, and it is checked from the CRC check bits whether an error has occurred in the duplicate header. If no error is found in the duplicate header as a result of the check, the PM information is output to the PM comparison circuit 405. As a result of the inspection, when an error occurs in the duplicate header, a signal indicating the inspection result is output to the synchronization determination circuit 402.

Further, the CRC decoding circuit 404
When information indicating the length of the payload and multiplexing information are input from the Y decoding circuit 403, CRC decoding is performed on the candidate portion of the duplicate header of the next frame, and whether an error has occurred in the duplicate header from the CRC check bit Inspect whether. As a result of the inspection, if no error occurs in the duplicate header, it is determined whether or not the multiplex information in the candidate portion of the header of the current frame matches the multiplex information in the candidate portion of the duplicate header of the next frame. If the multiplexing information matches as a result of the determination, a signal indicating the determination result is output to the synchronization determination circuit 402. When an error occurs in the duplicate header and when the multiplexed information does not match, a signal indicating the inspection result or the determination result is output to the synchronization determination circuit 402.

The PM comparison circuit 405 is
When the correlation value is input from 1 and the PM information is input from the CRC decoding circuit 404, it is determined whether the correlation value matches the PM information. Specifically, when the first correlation value is larger than the second correlation value and the PM information is “1”, and when the first correlation value is smaller than the second correlation value and the PM information is “0”. , It is determined that the correlation value matches the PM information. When the correlation value and the PM information match as a result of the determination, a signal indicating the determination result is output to the threshold adjustment circuit 406. When the correlation value and the PM information do not match, the signal indicating the determination result is output to the synchronization determination circuit 402. Output to

The threshold value adjusting circuit 406 is connected to the PM comparing circuit 40
5, the signal is input from the GOLAY decoding circuit 403.
The threshold value of the synchronization determination circuit 402 is adjusted based on the count value input from. Specifically, when GOLAY decoding is correctly performed, the threshold is reduced to prevent loss of synchronization, and when an error is detected by GOLAY decoding,
The threshold is increased to prevent erroneous synchronization detection.

Next, the processing of the frame synchronization apparatus according to the present embodiment will be described with reference to the flowchart of FIG.

First, in ST 501, a received signal is fetched into buffer 202 through input terminal 201.

Next, in ST502, UW comparison circuit 401
, The UW candidate portion of the received signal and the UW generation circuit 203
A first correlation value and a second correlation value are calculated from the UW generated in step (1).

Next, in ST503, the synchronization determination circuit 402
The magnitude of each correlation value is compared with the threshold.

If both of the correlation values are equal to or smaller than the threshold value in ST503, the GOLAY decoding circuit 205 performs GOLAY decoding on the candidate portion of the header in ST504 to detect the presence or absence of an error and determine the number of erroneous bits. Is counted. Also, in ST505 to ST506, the CRC decoding circuit performs C
RC decoding is performed, and it is checked from the CRC check bits whether an error has occurred in the duplicate header. And ST5
If an error occurs in the duplicate header in step 05, it is determined that the UW candidate portion is not UW102, and a portion obtained by shifting the current UW candidate portion by a predetermined amount is set as a new UW candidate portion, and the processing of ST502 and subsequent steps is performed. repeat. The shift amount is usually one byte, but is appropriately set by a multiplexing method or the like.

If no error occurs in the duplicate header in ST506, the PM comparison circuit 405 determines in ST507
It is determined whether the correlation value matches the PM information. If the correlation value and the PM information do not match in ST507,
It is determined that the candidate portion of UW is not UW102, and the current UW
The portion obtained by shifting the candidate portion of W by 1 bit is replaced with a new UW
The processing from ST502 onward is repeated as a candidate part of.

If the correlation value matches the PM information in ST507, the threshold value adjusting circuit 40 is set in ST508 to ST509.
At 6, the threshold value of the synchronization determination circuit 402 is adjusted based on the count value, and the synchronization determination circuit 402 compares the magnitude of each correlation value with the threshold value. If both of the correlation values are equal to or smaller than the threshold value in ST509, it is determined that the UW candidate portion is not UW102, and the portion obtained by shifting the current UW candidate portion by one bit is set as a new UW candidate portion in ST502 and subsequent portions. Repeat the process.

If one of the correlation values is larger than the threshold value in ST509, GOLAY is performed in ST510 to ST511.
The information indicating the length of the payload and the multiplexing information are output from the decoding circuit 205 to the CRC decoding circuit 404, and the CRC decoding circuit 404 performs CRC decoding on the candidate portion of the duplicate header of the current frame, To check if there is an error in the duplicate header. If an error occurs in the duplicate header in ST511, it is determined that the UW candidate portion is not UW102, and a portion obtained by shifting the current UW candidate portion by 1 bit is set as a new UW candidate portion in ST502 and subsequent steps. Repeat the process.

If no error has occurred in the duplicate header in ST511, the CRC decoding circuit 404 checks the multiplexed information in the header candidate portion of the current frame and the multiplexed information in the header candidate portion of the next frame in ST512. It is determined whether or not matches. If the multiplexing information does not match, it is determined that the candidate portion of the UW is not UW 102, and a portion obtained by shifting the current candidate portion of the UW by 1 bit is set as a new UW candidate portion, and the process from ST502 onward is repeated.

If the multiplexing information matches in ST512,
Alternatively, if one of the correlation values is larger than the threshold value in ST502, the candidate portion of UW is actually changed to UW in ST513.
102, and outputs the result of the determination from the output terminal 208 to an external device.

As described above, the threshold value is adaptively changed based on the information written in the header, and the appropriateness of the unique word candidate portion is determined based on the information written in the header and the duplicate header. As a result, the leading edge of the frame can be detected more accurately without increasing the redundancy of the unique word.

Although the present embodiment has been described using GOLAY decoding and CRC decoding, the present invention is not limited to this, and other error correcting codes can be used. In the present invention, the UW determination may be performed only after adjusting the threshold without performing the UW determination first. Further, the present invention can also determine the suitability of the unique word candidate portion based only on the information written in the header and the duplicate header.

[0078]

As described above, the frame synchronizing apparatus and the frame synchronizing method of the present invention can detect the leading edge of a frame in consideration of the information written in the header and the duplicate header. Loss of synchronization and erroneous synchronization can be avoided without increasing redundancy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a frame configuration of a signal received by a frame synchronizer according to the present invention;

FIG. 2 is a block diagram showing a configuration of a frame synchronization device according to the first embodiment of the present invention.

FIG. 3 is a flowchart in the above embodiment.

FIG. 4 is a block diagram showing a configuration of a frame synchronization device according to a second embodiment of the present invention.

FIG. 5 is a flowchart in the above embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional frame synchronization device.

[Explanation of symbols]

 204 UW comparison circuit 205 GOLAY decoding circuit 206 Threshold adjustment circuit 207 Synchronization judgment circuit 401 UW comparison circuit 402 Synchronization judgment circuit 403 GOLAY decoding circuit 404 CRC decoding circuit 405 PM comparison circuit 406 Threshold adjustment circuit

Claims (16)

[Claims] 1. A correlation value calculating means for calculating a correlation value between a known symbol candidate portion of a received signal in which a known symbol and a control symbol are inserted at a predetermined position of each frame and a known symbol; 1. A frame synchronization apparatus comprising: synchronization determination means for detecting a known symbol position of a received signal based on the magnitude relationship of; and threshold adjustment means for adjusting the threshold based on information on a control symbol candidate portion. 2. The apparatus according to claim 1, further comprising: counting means for decoding a control symbol candidate portion of the received signal in which the control symbol is error-correction-coded to count the number of error bits. 2. The frame synchronization apparatus according to claim 1, wherein the threshold is adjusted to be low. 3. A first error checker for decoding a control symbol candidate portion of a next frame of a received signal including an error check bit in a control symbol and checking the error check bit,
2. The frame synchronization apparatus according to claim 1, wherein the threshold adjustment unit adjusts the threshold to be low when no error is detected. 4. The synchronization determining means determines that the known symbol candidate portion is a known symbol when the correlation value is larger than the adjusted threshold value and a signal indicating a synchronization error is not input from another source. 4. The frame synchronization apparatus according to claim 1, wherein in the case of (1), the known symbol candidate portion is determined not to be a known symbol. 5. A method for decoding a control symbol candidate portion of a current frame of a received signal including an error check bit in a control symbol to check an error check bit, and when an error is detected, sends a signal indicating a synchronization error to a synchronization determination unit. 5. The frame synchronization apparatus according to claim 4, further comprising a second error checker that outputs the frame. 6. A control symbol candidate portion of a current frame of a received signal, wherein a first information bit indicating the type of packet data of the current frame and a second information bit indicating the type of packet data of the previous frame are included in the control symbol. A bit for determining whether one information bit matches the content of the second information bit of the control symbol candidate portion of the next frame, and outputting a signal indicating a synchronization error to the synchronization determination means when determining that the two information bits do not match. 6. The frame synchronization apparatus according to claim 4, further comprising a content determination unit. 7. A reception pattern in which a pattern of a known symbol differs depending on whether packet data of the current frame extends to the next frame, and a third information bit indicating whether the packet data of the current frame extends to the next frame is included in the control symbol. It is determined whether or not the pattern of the known symbol candidate portion of the signal matches the content of the third information bit of the control symbol candidate portion, and if not, outputs a signal indicating a synchronization error to the synchronization determination means. 7. The frame synchronization apparatus according to claim 4, further comprising comparison means. 8. The synchronization determining means according to claim 1, wherein said known symbol candidate portion is uniquely determined to be a known symbol when the correlation value is larger than an initially set threshold value.
The frame synchronization apparatus according to any one of claims 1 to 7. 9. A wireless communication apparatus equipped with the frame synchronization apparatus according to claim 1. 10. A correlation value between a known symbol candidate portion and a known symbol of a received signal in which a known symbol and a control symbol are inserted at a predetermined position of each frame, and a threshold value is set based on information on the control symbol candidate portion. A frame synchronization method comprising: adjusting the correlation value and, when the correlation value is greater than the threshold value, determining that a known symbol candidate portion of the received signal is a known symbol and detecting a leading end of a frame of the received signal. 11. The method according to claim 1, wherein a control symbol candidate portion of the received signal in which the control symbol is error-correction coded is decoded to count the number of error bits, and the threshold value is adjusted to be lower as the number of error bits is smaller. The frame synchronization method according to claim 10. 12. A control symbol candidate portion of a next frame of a received signal including an error check bit in a control symbol is decoded to check the error check bit, and when no error is detected, the threshold value is adjusted to be low. The frame synchronization method according to claim 10, wherein 13. A control symbol candidate portion of a current frame of a received signal including an error check bit in a control symbol is checked for error check bits. If an error is detected, it is determined that the known symbol candidate portion is not a known symbol. 13. The frame synchronization method according to claim 10, wherein: 14. A control symbol candidate portion of a current frame of a received signal, wherein a first information bit indicating a type of packet data of a current frame and a second information bit indicating a type of packet data of a previous frame are included in a control symbol. 14. The frame synchronization method according to claim 13, wherein when one information bit does not match the content of the second information bit of the control symbol candidate part of the next frame, the known symbol candidate part is determined to be not a known symbol. 15. A reception pattern in which a pattern of a known symbol differs depending on whether or not packet data of the current frame extends to the next frame, and a third information bit indicating whether or not the packet data of the current frame extends to the next frame is included in the control symbol. 15. The known symbol candidate portion is determined not to be a known symbol when the pattern of the known symbol candidate portion of the signal does not match the content of the third information bit of the control symbol candidate portion. Frame synchronization method. 16. The apparatus according to claim 10, wherein when the correlation value is larger than a default threshold value, the known symbol candidate portion is uniquely determined to be a known symbol.
6. The frame synchronization method according to any one of 5.