JP2000232436A - Clock extraction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fast and small clock extraction circuit that can be constituted by only a transistor circuit with no external parts required by preparing an edge detection circuit and an oscillator that uses a frequency divider. SOLUTION: If the frequency component of the signal outputted from an edge detection circuit 10 is satisfactorily approximate to the self-excited frequency of a T-FF 20, the synchronization is established between an input signal and the output signal of the T-FF 20 and accordingly a clock signal can be extracted. However, the clock signal outputted from the T-FF 20 has 1/2 frequency of a transmission clock rate. It's important that the intensity of input signal of the T-FF 20 is lower than the intensity of an input sensitivity curve. An exclusive OR circuit 12 and the T-FF 20 can be constituted by only the transistors and diodes with no filter circuit of a large time constant nor a resonator filter circuit having frequency selection capability. The T-FF 20 is used as a basic element circuit of a frequency divider.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input NRZ.
The present invention relates to a clock extraction circuit for extracting a clock signal from a type data signal, and more particularly to a clock extraction circuit which does not require external components and is suitable for integration.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional clock extraction circuit CE.
FIG.

The clock extraction circuit CE11 is based on PLL technology (Phase Locked Loop).
It comprises an edge detection circuit 101, a phase comparator 102, a low-pass filter 103, and a voltage-controlled oscillator 104.

The edge detecting circuit 101 receives the input NR
This circuit generates a clock signal frequency component not included in the Z signal, detects a rising edge and a falling edge of the NRZ signal, and generates a pulse for each edge.

[0005] The phase comparator 102 is connected to the edge detection circuit 10.
1 and an output signal of the voltage controlled oscillator 104, a phase of both signals is compared, and a difference signal is output.

[0006] The low-pass filter 103 is a phase comparator 1
02 is a circuit that removes the high-frequency component of the output signal 02, converts the phase comparison information into a DC voltage, and feeds it back to the voltage controlled oscillator 104.

The voltage-controlled oscillator 104 is a circuit that controls the oscillation frequency based on the control voltage output from the low-pass filter 103 so as to approach the frequency of the input signal of the clock extraction circuit CE11.

Then, a clock signal synchronized with the NRZ signal input to the clock extraction circuit CE11 is output from the clock extraction circuit CE11.

FIG. 11 is a block diagram showing a conventional resonator-type clock extraction circuit CE12.

The clock extraction circuit CE12 is a circuit generally called a resonator type clock extraction circuit. The clock extraction circuit CE12 includes an edge detection circuit 105 that operates similarly to the edge detection circuit 101 in the clock extraction circuit CE11, a resonator 106, and the limiter amplifier 1
07.

The edge detection circuit 105 is a circuit that generates a clock signal frequency component based on an input NRZ signal. The resonator 106 is a filter having excellent frequency selectivity, and is a circuit for extracting a clock signal component with high purity from an output signal of the edge detection circuit 105. The output signal of the resonator 106 is amplified by the limiter amplifier 107 to a desired voltage amplitude.

In a clock extraction circuit for a high-speed optical communication system, with the recent demand for an increase in transmission capacity, high speed and miniaturization have been pursued, and a 40 Gbit / s class operation has been realized based on these technologies. Have been. 4
For example, M. Wurzer, et. Al., "40 Gb / s Integrated Clock
and Data Recovery Circuit in a Silicon Bipolar Tec
hnology, "in IEEE BCTM Tech. Dig. pp. 136-139, 199
It is described in 8.

[0013]

By the way, the clock extraction circuit needs to stably extract the clock regardless of the pattern of the input NRZ signal. Here, the edge detection circuit generates a clock component based on the rising edge and the falling edge of the input signal. However, when a signal having the same code and a long continuous signal is input, the clock component is lost. For this reason, the clock extraction circuit has a disadvantage that the synchronization is lost when a long continuous signal with the same sign is input.

In order to overcome this drawback, the clock extraction circuit CE11 using the PLL technology requires a large time constant for the low-pass filter 103. Therefore, the elements formed on the semiconductor substrate satisfy the above conditions. I ca n’t,
Generally, there is a problem that the low-pass filter 103 has to be constituted by external components.

In order to cope with a high transmission rate, each of the individual circuits of the edge detection circuit 101, the phase comparator 102, and the voltage controlled oscillator 105 is required to have the ultimate performance. There is a problem that it is difficult to convert. In fact, in the clock extraction circuit according to the above document, the voltage-controlled oscillator and the filter use separate components.

On the other hand, a resonator type clock extraction circuit CE1
2 also has a problem that a clock signal is lost due to a continuous signal having the same sign and a long signal. In order to compensate for this, a resonator having a high Q value is required, and a high gain and a small phase deviation are required. A limiter amplifier is required. However, it is difficult to form a resonator circuit having a high Q value on a semiconductor substrate, and therefore, there is a problem that individual components must be used.

As described above, the conventional technique has a problem that it is difficult to integrate a clock extraction circuit applicable to a high bit rate on the same semiconductor substrate to reduce the size.

An object of the present invention is to provide a clock extracting circuit which can be constituted only by a transistor circuit without external components, and which is fast and small.

[0019]

According to the present invention, there is provided a clock extracting circuit having an edge detecting circuit and an oscillator, wherein a 1 / n frequency divider is used as the oscillator.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a clock extraction circuit CE1 according to a first embodiment of the present invention.

The clock extraction circuit CE1 includes an edge detection circuit 10 and a T-FF (toggle flip-flop) 20.
And is constituted by.

The edge detection circuit 10 is a circuit that inputs an NRZ data signal having no clock signal frequency component and outputs a differentiated full-wave waveform having a clock signal component from the input NRZ data signal. This circuit has a function of detecting a falling edge and generating a pulse for each edge. As the edge detection circuit 10, a differential full-wave rectification circuit is used. That is, the edge detection circuit 10 includes a delay circuit 11 and an exclusive OR circuit 12.

The delay circuit 11 has a bifurcated input NRZ.
This is a circuit that adds a delay to one of the NRZ data. The exclusive OR circuit 12 has a bifurcated input N
The other NRZ data of the RZ data and the delay circuit 1
This is a circuit that outputs an exclusive OR of two data with one output data.

Next, the operation of the above embodiment will be described.

FIG. 2 is a time chart showing the operation of the clock extraction circuit CE1.

The input NRZ data of the edge detection circuit 10 is divided into two, and the difference between the other NRZ data of the two divided input NRZ data and the output data of the delay circuit 11 is exclusively calculated. Since the OR circuit 12 outputs, as shown in FIG. 2B, the exclusive OR circuit 12 outputs a signal having a clock signal component.

Then, the output signal of the exclusive OR circuit 12 is input to the T-FF 20, and the T-FF circuit 20 outputs the signal at the rising edge or the falling edge of the input signal.
This is a logic circuit whose output level changes. When a sine wave is input to an input signal, the frequency of the output signal is reduced to 1/2, so that it is used as a basic element circuit constituting a frequency divider.

FIG. 3 is a diagram showing an example of the input signal sensitivity characteristic of the T-FF circuit 20.

In FIG. 3, the horizontal axis shows the frequency of the input signal, and the vertical axis shows the minimum input signal strength required for normal frequency division. In FIG. 3, there is a frequency at which an input signal becomes extremely small, and this frequency is generally called a self-excited oscillation frequency, and is a frequency at which the T-FF 20 oscillates even when no signal is input from outside. That is, when the intensity of the external input signal is equal to or less than the input signal intensity shown in FIG. 3, the T-FF 20 performs self-excited oscillation.

In the above embodiment, a signal having a frequency component near the oscillation frequency is input from the outside of the self-excited oscillating T-FF 20, and the operation principle of establishing phase synchronization by injection locking is used. .

Therefore, if the frequency component of the signal output from the edge detection circuit 10 is sufficiently close to the self-excited oscillation frequency of the T-FF 20, synchronization between the input signal and the output signal of the T-FF 20 is established, As a result, a clock signal can be extracted. However, the clock signal output from the T-FF 20 has a frequency that is 1/2 of the transmission clock rate.

What is important here is that the T-FF circuit 20 cannot execute the logical operation.
0 means that the input signal strength is sufficiently small. That is, T
-The input signal strength of the FF 20 needs to be lower than the input sensitivity curve.

Generally, a T-FF is a T-FF having a holding function.
There are -FF (master-slave type T-FF and the like) and T-FF without holding function (clocked inverter type T-FF and the like similar to a ring oscillator). In the above embodiment, both can be used. It is. However, when a T-FF having a holding function is used, a T-FF having no holding function is used.
The resistance to the disappearance of the clock frequency component in the output signal of the edge detection circuit 10 is higher than when F is used. That is, if a T-FF having a holding function is used,
Even when the same code continues for a long time in the input NRZ data signal, a 1/2 clock signal can be stably extracted.

In the above embodiment, the exclusive OR circuit 1
2 and the T-FF 20 can all be constituted only by transistors and diodes, and do not require a filter circuit having a large time constant or a resonator filter circuit having excellent frequency selectivity. That is, since all circuits can be realized on the semiconductor substrate, external components conventionally required can be eliminated.

Further, as described above, since the input signal strength of the T-FF 20 needs to be small enough not to perform a normal logical operation, the edge detection circuit 10 in the preceding stage requires a high frequency conversion efficiency. No need. In other words, this is equivalent to the fact that the power of the input signal of the edge detection circuit 10 is small, and the operation margin of the clock extraction circuit CE1 can be improved.

The self-oscillation frequency of the T-FF 20 can be easily adjusted by setting the DC level of the input signal. Therefore, when the present invention is applied to a transmission system in which the transmission rate is uniquely determined, The embodiment is effective.

FIG. 4 is a diagram showing the results of an experiment performed to confirm the operation principle of the clock extraction circuit CE1.

In FIG. 4, the upper part shows the signal waveform of the extracted clock, and the lower part shows the differential full-wave rectified waveform of the NRZ signal input to the T-FF 20 (since the inverted-phase waveform is monitored. , The polarity is inverted from the waveform shown in FIG. 2 (2)). That is, it can be seen that a good clock can be extracted by the above embodiment.

In the above embodiment, the edge detection circuit 10 is constituted by the delay circuit 11 and the exclusive OR circuit 12, but other configurations are used as the edge detection circuit which can be used in the above embodiment. An edge detection circuit may be used.

FIG. 5 is a block diagram showing an edge detection circuit 10a which can be used in place of the edge detection circuit 10 in the above embodiment.

The edge detection circuit 10a is a circuit having a differentiator 11a and a full-wave rectifier 12a.

FIG. 6 is a block diagram showing an edge detection circuit 10b which can be used in place of the edge detection circuit 10 in the above embodiment.

The edge detection circuit 10b includes a delay circuit 11b
And a mixer circuit 12b.

According to the above embodiment, since the injection locking method is used for the operation principle, the filter 103 having a large time constant required in the conventional clock extraction circuit CE11 based on the PLL technique is not required at all. Further, the resonator filter 106 required for the resonator-type clock extraction circuit CE12 is not required at all, and monolithic integration on a semiconductor substrate becomes possible. Further, since the exclusive OR circuit 12 and the T-FF 20 which are the elements of the above embodiment are both logic circuits, they are excellent in design consistency. Suitable for making monolithic. Furthermore, in the above embodiment, it is not necessary to impose high conversion efficiency on the edge detection circuits 10, 10a, 10b, so that the requirements for the input signal strength can be relaxed and the circuit operation margin can be increased.

FIG. 7 is a block diagram showing a clock extracting circuit CE2 according to a second embodiment of the present invention.

The clock extraction circuit CE2 basically includes
Same as the clock extraction circuit CE1, except that the T-FF20
Is different from the clock extracting circuit CE1 in that a 1 / n frequency divider 30 is used instead of (1) (n is an integer). That is,
The clock extraction circuit CE2 includes the edge detection circuit 10 and 1
/ N frequency divider 30. The operation of the clock extraction circuit CE2 is the same as that of the clock extraction circuit CE1.

According to the clock extracting circuit CE2, the frequency of the extracted clock can be down-converted to 1 / n. Further, in the clock extraction circuit CE2, a variable frequency divider can be used instead of the 1 / n frequency divider 30, whereby a desired frequency can be generated.

FIG. 8 is a block diagram showing a 1/2 frequency divider 30a that can be used in place of the 1 / n frequency divider 30 in the clock extraction circuit CE2.

The 1/2 frequency divider 30a includes a T-FF 40,
This is a circuit having a variable delay element 50. T-FF40
Has a master latch 41 and a slave latch 42, and the variable delay element 50 is connected between the master latch 41 and the slave latch 42. That is, 1/2
The frequency divider 30a is a frequency divider having a variable delay element.

The self-excited oscillation frequency of the T-FF 40 is determined by the delay time of the two latch circuits 41 and 42.
The variable delay element 50 is inserted in a critical path (a signal path that determines a delay time) in the T-FF 40,
By making the delay time of the delay element 50 variable, the self-excited oscillation frequency can be adjusted.

In the clock extraction circuit CE2, 1 / n
If the 1/2 frequency divider 30a is used instead of the frequency divider 30, the adjustment width of the self-excited oscillation frequency can be made larger than in the case of the clock extraction circuit CE1, and the operation margin for the transmission rate can be further increased. can do.

The 1/2 frequency divider 30a is connected to the master latch 4
This is a circuit in which a variable delay element 50 is inserted between 1 and the slave latch 42, but instead of doing so,
The variable delay element 50 may be inserted inside the master latch 41 itself or the slave latch 42 itself. Even in such a case, the same operation as in the case of using the 1/2 frequency divider 30a is performed. Further, as the T-FF 40,
A configuration other than the master-slave may be adopted.

Note that instead of the 1/2 frequency divider 30a, 1 /
An n frequency divider may be used, that is, the above-described embodiment is an example of a clock extraction circuit having a 1 / n frequency divider having a variable delay element.

FIG. 9 is a block diagram showing a clock extracting circuit CE3 according to a third embodiment of the present invention.

The clock extracting circuit CE3 has an edge detecting circuit 10, a frequency dividing circuit 30, and an attenuator 60, and the attenuator 60 is connected between the edge detecting circuit 10 and the frequency dividing circuit 30. . Then, by adjusting the amount of attenuation in the attenuator 60, the signal intensity input to the clock extraction circuit CE3 can be adjusted to such an extent that the injection locking operation can be performed.

The operation of the clock extraction circuit CE3 is as follows.
The operation is the same as that of the clock extraction circuit CE1.

According to each of the above embodiments, by directly inputting the output signal of the edge detection circuit to the oscillator, the PLL
Low-pass filters conventionally required in technology,
Alternatively, a clock extraction circuit can be configured without using a resonator required in a resonator-type clock extraction circuit. Furthermore, edge detection circuits, oscillators, especially T
-Since the FF circuit can be monolithically integrated on a semiconductor substrate, the size of the circuit can be significantly reduced as compared with the related art.

[0058]

According to the present invention, it is possible to realize a clock extracting circuit which does not require any external components, and since it can be constituted only by digital logic element circuits, monolithic integration can be achieved. If it is integrated on the same semiconductor substrate together with a D-FF circuit and the like required for data signal reproduction (with a clock extraction circuit), a completely monolithic clock data recovery circuit can be realized. It works.

[Brief description of the drawings]

FIG. 1 is a diagram showing a clock extraction circuit CE1 according to a first embodiment of the present invention.

FIG. 2 shows the operation of the first embodiment according to the present invention.

FIG. 3 is a diagram illustrating an example of an input signal sensitivity characteristic of a T-FF circuit 20;

FIG. 4 is a diagram illustrating the results of an experiment performed to confirm the operation principle of the clock extraction circuit CE1.

FIG. 5 is a block diagram showing an edge detection circuit 10a used in place of the edge detection circuit 10 in the embodiment.

FIG. 6 is a block diagram showing an edge detection circuit 10b used in place of the edge detection circuit 10 in the embodiment.

FIG. 7 is a block diagram showing a clock extraction circuit CE2 according to a second embodiment of the present invention.

FIG. 8 shows a 1/2 frequency divider 3 that can be used in place of the 1 / n frequency divider 30 in the clock extraction circuit CE2.
It is a block diagram showing 0a.

FIG. 9 is a block diagram showing a clock extraction circuit CE3 according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a conventional clock extraction circuit CE11.

FIG. 11 shows a conventional resonator-type clock extraction circuit CE12.
FIG.

[Explanation of symbols]

 CE1, CE2, CE3 ... clock extraction circuit, 10, 10a, 10b ... edge detection circuit, 11 ... delay circuit, 12 ... exclusive OR circuit, 20 ... T-FF, 30 ... 1 / n frequency divider, 40 ... T-FF, 41: master latch, 42: slave latch, 50: variable delay element, 60: attenuator.

Claims (4)

[Claims] 1. An NR having no clock signal frequency component
An edge detection circuit that inputs a Z data signal and outputs a differentiated full-wave waveform having a clock signal component from the input NRZ data signal, and an output signal of the edge detection circuit that is input and synchronizes with the input NRZ signal A clock extraction circuit comprising: an oscillator that outputs a single-frequency clock signal, wherein a 1 / n frequency divider (n is an integer) is used as the oscillator. 2. The clock extraction circuit according to claim 1, wherein the 1 / n frequency divider is a toggle flip-flop. 3. The clock extraction circuit according to claim 1, wherein the 1 / n frequency divider is a frequency divider having a variable delay element. 4. The clock extraction circuit according to claim 1, wherein an attenuator is inserted between the edge detection circuit and the oscillator.