JP2000231793A - Device and method for controlling writing-in of flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a writing-in level from being upgraded due to that a flash memory is repeatedly written in and to prevent the deterioration in the precision of a holding test. SOLUTION: This device consists of a flash cell array section 11, a writing-in section 12 which stores writing-in object binary data and writes the data into the section 11, and a reading out section 17 which reads the data written in the section 11 and stores the data. An inverter 22 is arranged between the sections 12 and 17 to reverse binary data read from the section 17. The reversed binary data, which are reversed by the inverter 22, are reset as writing-in object binary data of the section 12. By properly setting initial setting values of the sections 12 and 17, a performance test is made faster and deterioration in the test is prevented. Thus, the increase in a writing-in level of arbitrary writing-in data is eliminated for an arbitrary write-in data by the physical characteristics of a flash memory in sigular or plural steps of repeated writing-ins.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage element for storing an electronic voltage generated by applying a high voltage,
The present invention relates to a flash memory in which a high-voltage inversion operation is performed at the time of reading and a recorded value needs to be confirmed, and more particularly to a write control device and a write control method for a flash memory that requires a test of a holding characteristic of its electronic voltage.

[0002]

2. Description of the Related Art In fields where high-speed access is desired,
A semiconductor memory is used for the memory device. A flash memory is used as a semiconductor memory that can be erased at once and has an advantage that its stored value is not lost even when the power is cut off.

A flash memory utilizing the fact that local high and negative electrical activation is caused by application of a high voltage tends to deteriorate its holding performance. FIG. 5 shows a basic circuit of a known flash memory. The write target data sent from the CPU 100 and latched (installed) in the write latch 102 is written via the write line bus 103 to the cell array unit 101 which is a flash memory unit. The write data of the address thus written is read via the read line bus 104 and the read latch 105.
The read data latched by the read latch 105 is returned to the CPU 100,
At U100, the consistency between the write data and the read data is checked.

If there is no match, that is, if the data has not been correctly written, the data to be written which has already been written to the write latch 102 is written again to the cell array unit 101 and the data is again written to the read latch 1.
05, and the CPU 100 again checks the consistency between the write data and the read data. Such an operation is repeated until both data match, and correct writing is performed.

[0005] In such writing, the writing operation is repeated in the same manner as the writing to the erroneously written bit, even for the bit that has already been correctly written, and the already written bit is At the next write, the high voltage is applied again, the voltage level for the write rises, the write level differs for each bit, and the write level varies for each location in the array, deteriorating the retention. Is promoted. Further, at the time of a retention test for testing retention performance, it is difficult to specify a bit having the worst retention characteristic, and the precision of the retention test does not increase.

A technique in which the second writing is not performed is known from Japanese Patent Laid-Open No. Hei 6-187791. It is desired that the write level does not increase in the repetitive write step regardless of the write data for data correction. Further, it is desired that the deterioration of the accuracy of the holding test can be prevented.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a write control for a flash memory in which the write level does not increase by repetitive writing and the write level can be made uniform regardless of the write data for data correction. An object of the present invention is to provide an apparatus and a write control method thereof. Another object of the present invention is to make it possible to uniform the write level without increasing the write level by repetitive writing, regardless of the write data for data correction, and to prevent deterioration in the accuracy of the retention test. An object of the present invention is to provide a write control device and a write control method for a flash memory.

[0008]

Means for solving the problem are described as follows. The technical matters corresponding to the claims in the expression are appended with numbers, symbols, etc. in parentheses (). The number, the symbol, etc. are at least one of the technical matters corresponding to the claims and the plurality of embodiments.
Although the agreement / correspondence with the technical matters of the two forms is clarified, it is not intended to show that the technical matters corresponding to the claims are limited to the technical matters of the embodiment.

A write control device for a flash memory according to the present invention includes a flash cell array unit and a write unit for storing binary data to be written and writing the binary data to be written to the flash cell array unit (11). Including part (12)
And a reading unit (1) for reading and storing the binary data written in the flash cell array unit (11).
7) and an inverter interposed between the writing section (12) and the reading section (17) for inverting binary data output from the reading section (17) and inputting the inverted data to the writing section (12). (22) and inverted 2 inverted by the inverter (22)
The value data is reset as binary data to be written by the writing unit (12). Due to the physical characteristics of the flash memory, it is possible to rewrite the already-written bits regardless of the write data for data correction in one or more steps of such repetitive writing. Therefore, the write level does not increase at that bit, and writing can be performed only on the unwritten bit. In this case, by setting all the initial values of the writing unit (12) to zero, the holding performance test can be sped up, and as a result, the deterioration of the holding test accuracy can be prevented.

When the binary data of the reading section matches the original binary data to be written, resetting is stopped.
Further, a logical sum generation circuit (32) interposed between the inverter (22) and the writing unit (12) for generating a logical sum.
And a pre-write unit (31) connected to the input side of the logical sum generation circuit (32). The output side of the inverter (22) is connected to the input side of the logical sum generation circuit (32). The circuit configuration in which the output side of the sum generation circuit (32) is connected to the writing unit (12) is equivalent to the above-described circuit configuration. In this case, by setting all the initial values of the reading unit (17) to 1, the holding performance test can be sped up, and as a result, the deterioration of the holding test accuracy can be prevented.

A write control method for a flash memory according to the present invention includes the steps of writing first / binary data to be written in a flash cell array section (11);
A step of reading the written second binary data from the flash cell array unit (11), a step of inverting the read second binary data, and a step of inverting the inverted third binary data. Writing binary data into the flash cell array unit (11).

Further, the method comprises the step of generating the logical sum of the third binary data and the first binary data, and the step of writing the data in the flash cell array section is performed by the logical sum generated by the step. Convert binary data to third
This is a step for replacing the binary data with the binary data and writing the binary data into the flash cell array unit. This method is equivalent to the method described above. If the first binary data and the second binary data match, writing (11) of the third binary data into the flash cell array unit is stopped.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In accordance with the drawings, an embodiment of a flash memory write control device according to the present invention is provided with a flash memory device having a cell array unit 11 which is a flash memory unit. Write latch 12
Are connected to the cell array unit 11 via the write bus 13. The write operation of the write target data set in the write latch 12 to the cell array unit 11 is performed by the CPU 14.
It is executed by the command of

The write latch 12 is connected to the CPU 14 via a selector 20. The selector 20 has the first
It is connected to the CPU 14 via the data transfer bus 15. The write latch 12 is connected to the selector 20 via the second data transfer bus 16. Read latch 17
Are connected to the cell array unit 11 via the read bus 18. The read latch 17 is connected to the third data transfer bus 1
9 is connected to the CPU 14. The read latch 17 is connected to the selector 2 via the data inversion transfer bus 21.
Connected to 0. The data inversion transfer bus 21 includes:
An inverter 22 for inverting data is provided.

A selection instruction signal 23 is input from the CPU 14 to the write latch 12. The selection instruction signal 23 is also input to the selector 20 at the same time. Selection instruction signal 23
Sets the data inversion transfer bus 21 to the second data transfer bus 1
6 or an electrical signal for selectively instructing the CPU 14 to connect to the second data transfer bus 16.

FIG. 2 shows a flow of the repetitive writing operation. The initial value of the cell array unit 11 is set to zero. As an initial value, (0, 0, 0, 0, 0, 0, 0, 0) (=
0) is exemplified. The write target data 0 is selected by the selection instruction signal 23 and is written to the write latch 12 via the first data transfer bus 15 connected to the second data transfer bus 16.
And the initial value (0, 0,
0, 0, 0, 0, 0, 0).

The initial value (0,0,0,0,0,0,0,0) set in the write latch 12 is stored in the write bus 1
3 is written to a specific address of the cell array unit 11 (step S1). When this writing is completed, the data written at that address is read out to the read latch 17. An error has occurred during writing, and the data read to the read latch 17 is (0,
0, 0, 1, 1, 0, 0, 1).

The data thus read is stored in the read latch 17 via the read bus 18 (step S2). The read data (0, 0, 0, 1, 1, 0, 0, 1) thus stored in the read latch 17 is
The data is input to the inverter 22 via the data inversion transfer bus 21 and is inverted by the inverter 22. The first inverted data inverted by the inverter 22 is (1, 1,
1,0,0,1,1,0).

The first inverted data is input to the selector 20. The data inversion transfer bus 21 selected by the next selection instruction signal 23 is connected to the second data transfer bus 16, and the first inversion data is input to the write latch 12. By this input, the value of the write latch 12 is the first inverted data (1, 1, 1, 0, 0,
(1, 1, 0) (step S3).

The first inverted data is the second write target data, which is written to the cell array unit 11. At the time of this writing, the part (1,
1,1,-,-, 1,1,-) is "1",
There is no increase in the write level of the storage element. The first inverted value data written in this manner is stored in the read latch 17.
At the second time. It is assumed that the data read out the second time has not been completely repaired yet, and an error remains in only one place and is (0, 0, 0, 0, 0, 0, 0, 1) ( Step S4). This data is inverted for the second time and set in the write latch 12 (step S
4).

The value set in the write latch 12 for the second time is (1,1,1,1,1,1,1,0) (step S5). This value is written to the cell array unit 11 for the third time. At the time of this writing, the part (1,1,1,1,1,1,1,1,1) that is inverted with respect to the second write data
The portion of "-" of "1" does not increase the write level of the storage element. Read latch 1 from cell array unit 11
7 is (0, 0, 0, 0, 0, 0,
(0,0).

This data (0,0,0,0,0,0,
(0, 0) is stored in the read latch 17 (step S6). The data to be read, each time the data is read, are sent to the CPU 14 via the third data transfer bus 19 and compared with the initial value. The data and the initial value to be read are identical each time the data is read. Are confirmed by the CPU 14. At the time of the third reading, the read data matches the initial value. CPU 14 that has confirmed the match
Stops subsequent repetitive writing.

FIG. 3 shows another embodiment of the present invention. A pre-write latch 31 and an OR circuit 32 are interposed between the write latch 12 and the CPU 14 instead of the above-described selector. Although not shown, O
The number of the R circuits 32 is equal to the number of buses. Read latch 1
An inverter 22 is provided on the data inversion transfer bus 21 ′ between the gate 7 and the input side of the OR circuit 32. The output side of the OR circuit 32 is connected to the write latch 12 via the bus 33. The selection instruction signal 23 ′ is input from the CPU 14 to the pre-write latch 31 and the read latch 17.

FIG. 4 shows a flow of the repetitive writing operation of the embodiment of FIG. The initial value of the cell array unit 11 is
(1,1,1,1,1,1,1,1,1). The data to be written (1,01,0,1,0,0,1) is set in the prewrite latch 31 (step S11). The write signal 23 'at this setting is 1, and this signal 2'
3 'resets the read latch 17 to (1,
1,1,1,1,1,1,1,1) (step S1)
2). The output value of the data output to the read latch 17 is (1,1,1,1,1,1,1,1).

This output value is inverted by the inverter 22, and the first inverted data is input to the OR circuit 32. On the other hand, the output value (1, 0,
1, 0, 1, 0, 0, 1) are input to the OR circuit 32 as they are. The logical sum output from the OR circuit 32 (step S13) is input to the write latch 12 via the bus 33. The write latch 12 has (1, 0,
1, 0, 1, 0, 0, 1) are stored (step S1).
4).

The data to be written set in the write latch 12 is written to the cell array unit 11. When the first writing is completed, the data at the address just written is read out to the read latch 17. The read data is (1, 0, 1, 0, 1,
0, 1, 1). This read data (1,
0, 1, 0, 1, 0, 1, 1) are stored in the read latch 17 (step S15). Prewrite latch 31
The inverted value of this read data that does not match the write data written in (0, 1, 0, 1, 0, 1, 0, 0)
Is the write data (1, 0, 1, 0, 1, 0, 0,
1) is calculated (step S), and the logical sum is stored again in the prewrite latch 31 (step S).
17).

This OR data is written to the cell array section 11 as the second write data. Until the write data matches the read data (step S1
8) Such writing and reading are repeated. In order to make the logical sum of the value of the pre-write latch and the inverted value of the value of the read latch the next write data, during such repetitive operation, the write level of the flash memory cell is independent of the write data value. Can be aligned.

[0028]

According to the flash memory write control device and the write control method of the present invention, the write level does not increase due to repeated writing regardless of the write data for data correction. By using the inverter, the circuit without raising the write level is simple. By appropriately giving the initial set value, the holding test can be sped up, and as a result, the deterioration of the holding test accuracy can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a flash memory write control device according to the present invention.

FIG. 2 is a flowchart showing an embodiment of a flash memory write control method according to the present invention.

FIG. 3 is a circuit block diagram showing another embodiment of the flash memory write control device according to the present invention.

FIG. 4 is a flowchart showing another embodiment of the write control method of the flash memory according to the present invention.

FIG. 5 is a circuit block diagram of a known device.

[Explanation of symbols]

 11 flash cell array unit 12 write unit (write latch) 17 read unit (read latch) 22 inverter 22 logical sum generation circuit (OR circuit) 31 pre-write unit (pre-write latch)

Claims (8)

[Claims] A flash cell array unit; a write unit for storing binary data to be written and writing the binary data to be written to the flash cell array unit; and a write unit for writing to the flash cell array unit. A reading unit for reading and storing the binary data stored therein; and a binary data interposed between the writing unit and the reading unit, wherein the binary data output by the reading unit is inverted and input to the writing unit. A write control device for a flash memory, wherein the inverted binary data inverted by the inverter is reset as binary data to be written by the writing unit. 2. The flash memory write control device according to claim 1, wherein the resetting is stopped when the binary data of the read unit matches the original binary data to be written. . 3. The write control device for a flash memory according to claim 1, wherein all initial setting values of said writing unit are 0. 4. The logical sum generation circuit according to claim 1, further comprising a logical sum generation circuit interposed between the inverter and the write unit for generating a logical sum, and connected to an input side of the logical sum generation circuit. An output side of the inverter is connected to the input side of the logical sum generating circuit, an output side of the logical sum generating circuit is connected to the writing section, A setting control device for a flash memory, wherein all set values are 1. 5. A step for writing first / binary data to be written to a flash cell array unit, a step for reading the written second / binary data from the flash cell array unit, A flash memory comprising: a step for inverting the second binary data read in the step; and a step for writing the third binary data inverted in the step in the flash cell array unit. Write control method. 6. The method according to claim 5, wherein all of the initial values of the first and second data are zero. 7. The flash cell array according to claim 5, further comprising a step of generating a logical sum of the third and second data and the first and second data. The logical sum / binary data generated in the above step is replaced with the third / binary data to replace the flash / binary data.
A write control method for a flash memory, which is a step for writing to a cell array unit. 8. The method according to claim 7, wherein all of the third and second data are set to 1 as an initial value.