JP2000231425A - Computer system and activity ratio deciding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system and an activity ratio deciding device for realizing power saving control in multiple stages according to an actual using situation by deciding an activity ratio in a simple constitution. SOLUTION: An activity ratio judging circuit 16 is connected with the output of a keyboard(KB) 13. An activity ratio judging circuit 16 is constituted of a resistor(R) 162, a capacitor(C) 163, and a comparator circuit 164. According as key inputs are continuously operated, the storage charge amounts of the capacitor(C) 163 is increased, and when any key input is not operated, the storage charge amounts are gradually decreased from that point. Therefore, a time required for the decrease of the storage charge amounts to a level in which power saving control should be started is made different according to the key inputting situation until that time. Thus, the activity ratio of the computer system can be decided according to the size of the storage charge amounts of the capacitor(C) 163.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a utilization rate judging device, and more particularly to a computer system having a key input device and performing multi-stage power saving control in accordance with the state of key input from the key input device. And a utilization rate determination device usable in the system.

[0002]

2. Description of the Related Art In recent years, various power saving control techniques for reducing power consumption of personal computers and the like have been developed. VESA (Video Electroni
DPMS (Display Power Management Signaling) standardized by cs Standards Association
Is one of the power-saving control technologies. This DPMS is
A standard for power saving the display monitor of a personal computer, in which software detects the length of time that has elapsed since key input is no longer performed, and power saves the display monitor in stages accordingly. It is.

A display monitor compatible with DPMS has a plurality of operating states with different power consumptions, such as an on mode, a standby mode, a suspend mode, and an off mode. Determined by instructions from the side. The instruction from the computer is given by a combination of the supply states of the horizontal synchronization signal and the vertical synchronization signal. By changing the combination, the operation state of the display monitor can be controlled in multiple stages.

[0004]

However, in such a configuration in which the length of time that has elapsed since the key input is not performed is used as an index of the multi-step control, at what frequency the key input has been performed until then. Regardless of whether or not the key is pressed, if there is no key input for a certain period of time, the state is unconditionally shifted to the power saving state. For this reason, it has been difficult for the user to perform power saving control according to the actual use situation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in view of the above circumstances.
It is an object of the present invention to provide a computer system and a usage rate determination device capable of realizing multi-stage power saving control according to an actual use situation.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a computer having a key input device and performing multi-stage power saving control in accordance with the state of key input from the key input device. A charge storage circuit connected to an output of the key input device, the charge storage circuit including a capacitor in which charge is stored each time a key is input, and a discharge circuit thereof; Means for judging the usage rate of the computer system in response thereto, and stepwise power saving control of the computer system or a predetermined device in the computer system according to the judgment result.

In this computer system, the amount of charge stored in the capacitor increases as key input is performed continuously, and the amount of stored charge gradually decreases from the time when key input is not performed. Therefore, the time required for the accumulated charge amount to drop to the level at which the power saving control should be started differs depending on the key input situation up to that point. Therefore, the usage rate of the computer system is determined based on the magnitude of the accumulated charge amount of the capacitor. can do. Therefore, the usage rate can be determined with a simple configuration, and it is possible to realize multi-stage power saving control according to the actual usage status.

As the capacitor, a capacitor having a value such that the accumulated charge of the capacitor reaches the maximum charge accumulation amount of the capacitor when a predetermined plurality of key inputs are continuously performed. Can be.

Further, a charge storage circuit including a capacitor for storing charges each time a command is issued to the device and a discharge circuit therefor may be provided. This makes it possible to implement not only key input but also multi-level power saving control according to the usage rate of the device.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration of a personal computer according to an embodiment of the present invention. This personal computer has a CPU as shown in the figure.
11, system controller 12, keyboard (KB)
13, a display monitor 14, a hard disk drive (HDD) 15, a usage rate determination circuit 16, and the like. The system controller 12 includes the CPU 1
It is composed of various peripheral interfaces for controlling each device under one control. The system controller 12 is provided with a power saving control unit 121, which controls the entire system,
In addition, multi-stage power saving control is performed for each device.

The operating states of the system include a normal operating state, a halt state in which the system power is turned off, a suspend state in which most other devices except the memory are turned off,
There is a hibernation state in which the system power is turned off after storing the memory data in the disk device, and a multi-stage power saving control is performed by switching these operation states. In the power saving control of the device, for example,
The CPU 11 is controlled to switch its operation speed in multiple stages, and the display monitor 14 is switched between high-brightness display, low-brightness display, display-off, power-off, and the like. HDD1
For 5, the operation state is switched between a normal operation state, a motor rotation off state, a power off state, and the like.

The switching of the operation state by the power saving control unit 121 is performed based on the usage rate of the system or a predetermined device. As the idle state that is not used continues for a long time, the state is shifted to a deeper power saving state. You. In the present embodiment, the usage rate of the system is determined based on the state of key input from the keyboard (KB) 13. To this end, an output of the keyboard (KB) 13 is connected to a usage rate determination circuit 16 as shown in FIG.
6 is used to determine the usage rate of the system.

As shown, the duty cycle determination circuit 16 comprises a backflow prevention diode 161, a resistor (R) 162, a capacitor (C) 163, and a comparison circuit 164. The capacitor (C) 163 has a keyboard (K
B) Each time key data is input from 13, a fixed amount of charge is accumulated. For the capacitor (C) 163, the accumulated charge of the capacitor (C) 163 becomes the maximum charge accumulated amount of the capacitor (C) 163 for the first time when a predetermined number of key inputs are continuously performed. Those having a capacity of a value to be reached are used.

In this configuration, the amount of charge stored in the capacitor (C) 163 increases as the key input is performed continuously, and the amount of stored charge gradually decreases from the time when no key input is performed. Will be done. Therefore, the time required for the accumulated charge amount to fall to the level at which the power saving control should be started differs depending on the key input situation up to that point. The usage rate can be determined.

The comparison circuit 164 includes a capacitor (C) 16
3 is compared with a plurality of threshold values predetermined for multi-stage power saving control, and the usage rate is determined according to the comparison result. The determination result is sent to the power saving control unit 121 as a power save level signal (level 0, 1, 2,...) As shown. Level 0 indicates a full power level, in which case the system or device operates in a normal operating state. Level 1, level 2 ...
The system or device is transitioned to a lower power consumption power saving state.

Here, the power saving control operation using the usage rate judgment circuit 16 will be described with reference to FIG.

First, an operation corresponding to one key input operation will be described with reference to FIG.

1) When the keyboard (KB) 13 is pressed, the capacitor (C) 163 is charged.

2) The potential of the capacitor (C) 163 becomes higher than the power save level 0 (full power) of the comparison circuit 164, and a full power signal is output.

3) Upon receiving the full power signal, the power saving control unit 121 sets the system or device to a normal operation state (full power). In this way, by configuring the power level to be equal to or higher than the full power level by one key input operation, the system or device can be immediately returned to the normal operation state by one key input operation.

4) The electric charge charged in the capacitor (C) 163 is discharged according to the time constant of the circuit, and
The power save level is 21.

5) Upon receiving this signal, the power saving control unit 12
1 sets the system or device to a power saving state corresponding to power save level 1.

6) The discharge further proceeds, and the capacitor (C) 1
The potential of 63 becomes the power save level 2 of the comparison circuit 121.

7) Upon receiving this signal, the power saving control unit 12
1 sets the system or device to a power saving state corresponding to power save level 2. In this way, multi-step control according to the change in the amount of charge stored in the capacitor (C) 163 is realized.

FIG. 2B shows a state of a change in the accumulated charge amount when the key input is stopped from a state where the key input frequency is high.

As can be seen from FIG. 2B, when the frequency of key input is high, the amount of charge charged to the capacitor (C) 163 becomes larger than when the key is pressed once.
The time to shift to the power save mode becomes longer. This makes it possible to change the length of time required to shift to the power save mode between when the usage rate is high and when the usage rate is low, and it is possible to realize power saving control according to the usage situation.

FIG. 3 shows an example of a specific connection relationship between the usage rate judging circuit 16 and the keyboard (KB) 13.

The keyboard (KB) 13 is a keyboard controller (KBC) 1 in the system controller 12.
22. That is, the keyboard controller (KBC) 122 scans the key matrix of the keyboard (KB) 13 line by line using the scan line 101 and receives a signal from the return line 102 at a position corresponding to the pressed key.

In this case, as shown in the figure, the OR of the potentials of all the signal lines of the return line 102 is calculated by the OR circuit 201.
, And guiding it to a time constant circuit composed of a resistor (R) 162 and a capacitor (C) 163, it is possible to determine the level based on the frequency of key input.

The usage rate determination circuit 16 can determine the usage rate of a device based on not only key input but also the frequency of issuing commands to the device.

For example, regarding the HDD 15, the HDD 15
Multi-stage power saving control is performed on the HDD 15 based on the usage rate of the HDD 15. In this case, the usage rate of the HDD 15 may be determined by the usage rate determination circuit 16. FIG. 4 shows a configuration example in this case.

The HDD 15 is connected to the system controller 12
Is controlled by the IDE interface controller 123 in the inside. Access to HDD 15 is IDE
This is executed by issuing a command from the IDE interface controller 123 to the HDD 15 via the interface line. The number of IDE interface lines is 40 in total, and includes various control signal lines and data lines. Since the control line used to issue the command may vary depending on the type of command, in this example, for simplicity, the logical sum of the potentials of all the signal lines of the IDE interface line is generated through the OR circuit 202. The level is guided to a time constant circuit composed of a resistor (R) 162 and a capacitor (C) 163 to determine the level based on the command issuing frequency. The operation in this case is as follows.

1) When a command is issued to the HDD 15, the capacitor (C) 163 is charged.

2) The potential of the capacitor (C) 163 becomes equal to or higher than the power save level 0 (full power) of the comparison circuit 164, and a full power signal is output.

3) Upon receiving the full power signal, the power saving control unit 121 sets the HDD 15 to the normal operation state (full power).

4) The electric charge charged in the capacitor (C) 163 is discharged according to the time constant of the circuit, and
The power save level is 21.

5) Upon receiving this signal, the power saving control unit 12
1 sets the HDD 15 to a power saving state corresponding to the power save level 1.

6) The discharge further proceeds, and the capacitor (C) 1
The potential of 63 becomes the power save level 2 of the comparison circuit 121.

7) Upon receiving this signal, the power saving control unit 12
1 sets the HDD 15 to a power saving state corresponding to the power save level 2. Thus, the capacitor (C)
The multi-step control according to the change in the accumulated charge amount in 163 is realized.

When the frequency of command issuance is high, the amount of electric charge charged to the capacitor (C) 163 becomes larger than that at the time of one command issuance, and the time required to shift to the power save mode becomes longer. This makes it possible to change the length of time required to shift to the power save mode between when the usage rate is high and when the usage rate is low, and it is possible to realize power saving control according to the usage situation.

It is to be noted that the usage rate judgment circuit 16 using the capacitor (C) 163 can be connected to an arbitrary signal line for predetermined data input or command transmission, thereby accommodating data input or command transmission. It is possible to determine the usage rate of the device that operates while operating.

The value of the power level (threshold) of the comparison circuit 164 may be set to an appropriate value for each device to be determined. As a result, the usage rate of each of the plurality of devices in the system can be individually determined by the usage rate determination circuit 16 provided for each of the devices.

[0044]

As described above, according to the present invention,
The usage rate can be determined with a simple configuration, and it is possible to realize multi-stage power saving control according to the actual usage status.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view for explaining the operation of a usage rate determination circuit provided in the system of the embodiment;

FIG. 3 is an exemplary view showing an example of a specific connection relationship between a usage rate determination circuit provided in the system of the embodiment and a keyboard;

FIG. 4 is an exemplary view showing an example of a specific connection relationship between a usage rate determination circuit provided in the system of the embodiment and an HDD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... System controller 13 ... Keyboard (KB) 14 ... Display monitor 15 ... HDD 16 ... Usage rate judgment circuit 121 ... Power saving control unit 122 ... Keyboard controller (KBC) 123 ... IDE interface controller 162 ... Resistance 163 ... Capacitor 164: comparison circuit 202, 202: OR circuit.

Claims (5)

[Claims] 1. A computer system having a key input device and performing multi-stage power saving control in accordance with the state of key input from the key input device, the computer system being connected to an output of the key input device, A charge storage circuit including a capacitor in which a charge is stored each time an input is performed and a discharge circuit thereof, and a use rate of the computer system is determined according to a magnitude of a stored charge amount of the charge storage circuit, and according to the determination result, Means for stepwise power saving control of the computer system or a predetermined device in the computer system. 2. The capacity of the capacitor is set to a value such that the accumulated charge of the capacitor reaches the maximum charge accumulation amount of the capacitor when a predetermined plurality of key inputs are continuously performed. The computer system according to claim 1, wherein: 3. A computer system for performing multi-stage power saving control according to the frequency of use of a device, wherein the computer system is connected to a signal line for issuing a command to the device, and charges are accumulated each time a command is issued. A charge storage circuit including a capacitor and a discharge circuit thereof, and determining a usage rate of the device or the computer system according to the amount of charge stored in the charge storage circuit.
Means for stepwise power saving control of the computer system or a predetermined device in the computer system according to the determination result. 4. The capacity of the capacitor is set to a value such that the accumulated charge of the capacitor reaches the maximum charge accumulation amount of the capacitor when a predetermined plurality of commands are continuously issued. The computer system according to claim 3, wherein: 5. A charge storage circuit which is connected to a signal line for predetermined data input or command transmission and includes a capacitor for storing charge each time data input or command transmission is performed, and a discharge circuit therefor; Means for judging the usage rate of a device that operates while accommodating the data input or command transmission according to the magnitude of the accumulated charge amount in the circuit.