JP2000228510A - Non-volatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device together with its manufacturing method wherein a silicide process is employed. SOLUTION: A floating gate 4 which is, comprising an acute corner part at its upper part, formed on a silicon substrate 1, a tunnel oxide film covering the floating gate 4, a control gate 6 so formed as to provide a region overlapping the floating gate 4 through the tunnel oxide film, source/drain regions 7 and 8 so formed, on the front surface of substrate, as to adjoin the floating gate 4 and the control gate 6, a siliciding-prevented film 12 so formed as to cover the floating gate 4 on the side of source region 8, a titanium silicide film 13 formed on the surface of the drain region 8, and a metal wiring connected to the source/drain regions 7 and 8 through an inter-layer insulating film 9, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate formed so as to overlap the floating gate via a tunnel oxide film covering the floating gate, and a method of manufacturing the same. More specifically, the present invention relates to a technique for improving a silicide process in such a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell comprises a single transistor, in particular, a programmable ROM (EEPROM: Electronically Erasable an).
In d Programmable ROM), each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a memory cell transistor having a double gate structure,
Data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. And F-
Data is erased by extracting charges from the floating gate to the control gate by N-conduction (Fowler-Nordheim tunnelling).

FIG. 7 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
Is a sectional view taken along line X1-X1. FIG. 1 shows a split gate structure in which a control gate is arranged alongside a floating gate.

[0006] LO is applied to the surface region of the P-type silicon substrate 1.
A plurality of element isolation films 2 made of a LOCOS oxide film formed selectively and thickly by a COS (Local Oxidation Of Silicon) method are formed in a strip shape, and an element region is partitioned.
A floating gate 4 is formed on a silicon substrate 1 so as to extend between adjacent element isolation films 2 via an oxide film 3A.
Is arranged. This floating gate 4 is arranged independently for each memory cell. The selective oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 by selective oxidation, and a sharp corner is formed at an end of the floating gate 4. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation.

A control gate 6 is arranged on a silicon substrate 1 on which a plurality of floating gates 4 are arranged via a tunnel oxide film 3 integrated with the oxide film 3A corresponding to each column of the floating gates 4. Is done. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3A. The floating gate 4 and the control gate 6 are
The adjacent rows are arranged so as to be plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in a substrate region between the control gate 6 and a substrate region between the floating gates 4. The drain region 7 is formed between the control gate 6 and the device isolation film 2.
Are separated from each other, and the source region 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.

Then, on the control gate 6,
Metal wiring 10 is arranged in a direction intersecting control gate 6 with interlayer insulating film 9 interposed therebetween. This metal wiring 10
Is connected to the drain region 7 through the contact hole 11. Each control gate 6 becomes a word line, and the source region 8 extending in parallel with the control gate 6 becomes a source line. Also, the drain region 7
Wiring 10 made of aluminum alloy or the like to be connected to
Becomes a bit line.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is changed, and the resulting difference in the operating characteristics of each memory cell transistor is made to correspond to the stored data. ing.

The data write, erase, and read operations in the above nonvolatile semiconductor memory device are performed, for example, as follows. In the write operation, the potential of the control gate 6 is 2 V, the potential of the drain region 7 is 0.5 V, and the high potential of the source region 8 is 12 V. Then, between the control gate 6 and the floating gate 4 and between the floating gate 4 and the substrate (source region 8) are capacitively coupled (the capacitance between the control gate 6 and the floating gate 4 <the floating gate 4 and the substrate (source region 8). ) The capacity between),
Due to this capacitance coupling ratio, the potential of the floating gate 4 is raised to about 9 V, hot electrons generated near the drain region 7 are accelerated to the floating gate 4 side, and injected into the floating gate 4 through the oxide film 3A to write data. Done.

On the other hand, in the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 14 V. As a result, the charges (electrons) accumulated in the floating gate 4 are transferred from the FN (Fowler-Nor
The tunnel oxide film 3 is formed by conduction.
Is released to the control gate 6 to erase the data.

In the read operation, the potential of the control gate 6 is set at 4 V, and the drain region 7 is set at 2 V.
V and the source region 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed below the floating gate 4 and no drain current flows. Conversely, if charges (electrons) are not injected into the floating gate 4, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a drain current flows.

In such a nonvolatile semiconductor memory device, for example, a titanium silicide film is formed on a source / drain region by a silicide process to reduce its parasitic resistance and to suppress wiring delay and conductance deterioration. Is growing.

[0013]

However, when the silicide process is used as it is in the conventional device having the above-described structure, the following problems may occur. That is, as shown in FIG. 9 (a partially enlarged view of FIG. 8), in the conventional configuration, a sharp corner 4A is formed above the floating gate 4, so that silicidation is not performed as in a normal silicide process. Even when the side wall spacer film 9D is formed in the portion, there is a problem that the margin between the corner 4A and the film to be silicided (for example, a titanium film) cannot be secured, and the conditions are severely determined.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device employing a silicide process and a method of manufacturing the same.

[0015]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems.
The non-volatile semiconductor memory device described in the item 1 is, for example, a floating gate 4 formed on a P-type
A tunnel oxide film 3 covering the floating gate 4; a control gate 6 formed to have a region overlapping the floating gate 4 via the tunnel oxide film 3;
N-type source / drain regions 7, 8 formed on the surface of the silicon substrate 1 adjacent to the control gate 6, and a metal connected to the source / drain regions 7, 8 via an interlayer insulating film 9. In the nonvolatile semiconductor memory device having the wiring 10, the metal wiring 10 is formed on the surface of the drain region 7 via a titanium silicide film 13, and the metal wiring 10 is formed on the surface of the source region 8 without a titanium silicide film. It is characterized in that the wiring 10 is formed.

In the nonvolatile semiconductor memory device according to the second aspect of the present invention, a silicidation protection film 12 (, 14) is formed on the surface of the source region 8 so that a titanium silicide film is not formed. It is characterized by being.

Further, in the nonvolatile semiconductor memory device according to the third aspect of the present invention, for example, a floating gate 4 formed on a P-type silicon substrate 1 and having a sharp corner 4A at an upper portion, and the floating gate 4 A tunnel oxide film covering the gate, a control gate formed to have a region overlapping the floating gate via the tunnel oxide film, and covering the floating gate and the control gate; Insulating film (sidewall spacer film 9)
D), N-type source / drain regions 7 and 8 formed on the surface of the substrate 1 adjacent to the floating gate 4 and the control gate 6, and a drain region 8
The titanium silicide film 13 formed on the surface and the silicidation protection film 12 (,) formed so as to cover at least the sharp corner 4A above the floating gate 4.
14), and a metal wiring 10 connected to the source / drain regions 7 and 8 via an interlayer insulating film 9.

According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device, the silicidation protection film is made of TEO.
The silicidation protection film 12 made of S film or HTO
The silicidation protection film 14 is made of a film or a SiN film.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising: a floating gate formed on a P-type silicon substrate; and a tunnel oxide film covering the floating gate. 3, a control gate 6 formed to have a region overlapping the floating gate 4 with the tunnel oxide film 3 interposed therebetween, and a control gate 6 formed on the surface of the substrate 1 adjacent to the floating gate 4 and the control gate 6. And an N-type source / drain region 7, 8 to be formed.
2 (, 14), a titanium film 13A is formed on the entire surface, and the titanium film 13A is heat-treated to form a titanium silicide film 13 only on the surface of the drain region 7.
The titanium film 13A that is not to be silicided is removed. Then, after the interlayer insulating film 9 is formed, a step of forming a metal wiring 10 contacting the source / drain regions 7 and 8 via the interlayer insulating film 9 is provided.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the surface of the P-type silicon substrate 1 is thermally oxidized to form a gate oxide film 3A. A first conductive film 4B is formed thereon,
After a silicon nitride film 23 having an opening 23A of a predetermined pattern is formed on the conductive film 4B, the first conductive film 4B is selectively oxidized through the opening 23A to form a selective oxide film 5. Next, using the selective oxide film 4 as a mask, the first conductive film 4B is anisotropically etched to form a floating gate 4 having a sharp corner 4A at the top.
Subsequently, after a tunnel oxide film 3 is formed so as to cover the floating gate 4, a polysilicon film and a tungsten silicide (W
A second conductive film 6A made of an (Six) film is formed, and the second conductive film 6A is patterned to form a control gate 6 having a region overlapping with the floating gate 4 via the tunnel oxide film 3. I do. Further, the floating gate 4 and the control gate 6
The surface of the silicon substrate 1 adjacent to the N-type source
After forming the drain regions 7 and 8, the source region 8 is formed.
A silicidation protection film 12 (, 14) is formed thereon. Next, a titanium film 13A is formed on the entire surface.
After heat-treating A to form a titanium silicide film 13 only on the surface of the drain region 7, the titanium film 13A that is not silicided is removed. And forming a metal wiring 10 in contact with the source / drain regions 7 and 8 via the interlayer insulating film 9 after forming the interlayer insulating film 9.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a gate oxide film 3A is formed by thermally oxidizing the surface of a P-type silicon substrate 1, and the gate oxide film 3A is formed. A first conductive film 4B is formed thereon,
After a silicon nitride film 23 having an opening 23A of a predetermined pattern is formed on the conductive film 4B, the first conductive film 4B is selectively oxidized through the opening 23A to form a selective oxide film 5. Next, using the selective oxide film 4 as a mask, the first conductive film 4B is anisotropically etched to form a floating gate 4 having a sharp corner 4A at the top.
Subsequently, after a tunnel oxide film 3 is formed so as to cover the floating gate 4, a polysilicon film and a tungsten silicide (W
A second conductive film 6A made of an (Six) film is formed, and the second conductive film 6A is patterned to form a control gate 6 having a region overlapping with the floating gate 4 via the tunnel oxide film 3. I do. Further, the floating gate 4 and the control gate 6
The surface of the silicon substrate 1 adjacent to the N-type source
After forming the drain regions 7 and 8, the source region 8 is formed.
A silicidation protection film 12 (, 14) is formed thereon. Subsequently, after cleaning the entire surface, an impurity (for example, boron ion) is ion-implanted into the drain region 7, a titanium film 13A is formed on the entire surface, and the titanium film 13A is heat-treated to cover the surface of the drain region 7. After forming only the titanium silicide film 13, the titanium film 13A that is not silicided is removed. Then, after the interlayer insulating film 9 is formed, a step of forming a metal wiring 10 contacting the source / drain regions 7 and 8 via the interlayer insulating film 9 is provided.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to claim 8 of the present invention, the silicidation protection film according to claim 5 or 6 or 7 comprises a TEOS film. It is a silicidation protection film 12 or a silicidation protection film 14 made of an HTO film or a SiN film.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention and a method for manufacturing the same will be described with reference to the drawings. A plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate and a partial (X1-X1) sectional view thereof are shown in FIGS.
Are substantially the same as those shown in FIG. 1, and the description thereof is omitted to avoid repetition. However, the same components will be denoted by the same reference numerals, and the description will be simplified. A feature of the present invention is that the silicidation protection film 12 is formed so as to cover the sharp corner 4A above the floating gate 4 on the source region 8 side as shown in FIG. 5, which is a partially enlarged view of FIG. It is formed. Thus, only with the sidewall spacer film 9D formed so as to cover the side wall of the floating gate 4, the distance between the floating gate 4 and the silicided film (for example, titanium film) due to the presence of the corner 4A. Even in a configuration having a strict margin, silicidation can be surely prevented in a portion that is not to be silicided, and the risk of short-circuit between the floating gate 4 and the source region 8 as in the related art can be suppressed.

Hereinafter, a method for manufacturing a memory cell of such a nonvolatile semiconductor memory device will be described with reference to the drawings.

First, in FIG. 1A, an element isolation film 2 is formed in a predetermined region of a P-type semiconductor substrate 1 (see FIG. 7), and a gate oxide film 3A is formed on a surface layer other than the element isolation film 2. Is formed to a thickness of about 70-150 °. Then, a polysilicon film is formed on the gate oxide film 3A to a thickness of about 1000 to 2000 mm, and a silicon nitride film 23 having an opening 23A is formed on the phosphorus-doped first conductive film 4B.

Next, as shown in FIG. 1B, the first conductive film 4B is formed using the silicon nitride film 23 as a mask.
A selective oxidation film 5 is formed by selective oxidation by a COS (Local Oxidation Of Silicon) method.

Subsequently, as shown in FIG. 2A, the first conductive film 4B is anisotropically etched using the selective oxide film 5 as a mask to form the floating gate 4 under the selective oxide film 5. Form. At this time, a sharp corner 4A is formed above the floating gate 4, reflecting the shape of the selective oxide film 5. As a result, the electric field is concentrated on the corner 4A during the erasing operation, and the electrons (charges) accumulated in the floating gate 4 can easily pass through the tunnel oxide film 3 to the control gate 6, thereby improving the erasing efficiency. Have improved.

Next, as shown in FIG. 2 (b), the thickness is approximately 200 to 400, which is formed integrally with the gate oxide film 3A so as to cover the floating gate 4.
An insulating film (1) (hereinafter referred to as a tunnel oxide film 3) is formed. The tunnel oxide film 3 is formed of a gate oxide film 3A and a CVD oxide film, for example, TEOS (Tetra Ethyl Ortho Silicate) on the gate oxide film 3A by a CVD method.
It is formed by forming a film or an HTO (High Temperature Oxide) film and then thermally oxidizing the film.

Subsequently, as shown in FIG. 3A, a second conductive layer having a two-layer structure including, for example, a phosphorus-doped polysilicon film and a tungsten silicide film (WSix film) is formed on the tunnel oxide film 3. Membrane 6A and approximately 2000
An insulating film 9A having a thickness of {3000} is formed. The conductive film 6A is formed by first forming a polysilicon film by about 100
After forming the polysilicon film to a thickness of 0 to 2000 mm and then doping the polysilicon film with phosphorus using POCl ₃ as a diffusion source, a tungsten silicide film (WSix) is formed on the polysilicon film.
(Film) to a thickness of approximately 1000-2000 °. A control film is formed by forming a photoresist film (not shown) on the insulating film 9A, patterning the conductive film 6A and the insulating film 9A using the resist film as a mask, and laminating the insulating film 9B thereon. A gate 6 is formed on one end side of the floating gate 4 via the tunnel oxide film 3 so as to extend from the upper portion to the side wall portion. Then, after removing the resist film, at least a portion where a drain region is to be formed is covered with a photoresist film (not shown), and using this photoresist film as a mask, n-type impurities such as phosphorus ions ( ³¹ P ⁺ ) Is approximately 4.0 to 5.0 × 10
^The source region 8 is formed by implanting under an implantation condition of ¹⁵ / cm ² and an acceleration voltage of 50 to 70 KeV, annealing and diffusing. As the n-type impurity to be ion-implanted, may be used arsenic ion ⁽⁷⁵ As ⁺⁾ or the like.

Next, as shown in FIG. 3 (b), the entire surface of the
LPCVD oxide film (for example, TEOS
4A, the insulating film 9C and the tunnel oxide film 3 are anisotropically etched to expose the upper surface of the source / drain formation region and to form the side wall, as shown in FIG. The spacer film 9D is formed.

Then, using the floating gate 4 and the control gate 6 as a mask, for example, phosphorus ( ³¹ P ⁺ ) ions are applied to the surface layer of the substrate 1 with a dose of about 1.0.
2.0 × 10 ¹³ / cm ² , acceleration voltage 35-45 KeV
And annealing treatment is performed under the implantation conditions of
To form

Next, as shown in FIG. 4B, an LPTEOS film 12A having a thickness of about 300 to 400 ° is formed on the entire surface of the substrate 1 by LPCVD, and a photoresist film 25 covering the source region 8 is formed. Using this as a mask, this T
The EOS film 12A is patterned to form the silicidation protection film 12 on the source region 8. The silicidation protection film 12 functions to assist the silicidation prevention action of the sidewall spacer film 9D covering the upper corner 4A of the floating gate 4. As will be described in detail later, since the upper corner portion 4A of the floating gate 4 is covered together with the sidewall spacer film 9D, a titanium film is formed on the entire surface in a later step, and the titanium film and the lower surface are subjected to heat treatment. When a titanium silicide (TiSi ₂ ) film is formed by reacting with Si to form a titanium silicide (TiSi ₂ ) film, silicidation of a portion not desired to be silicided can be reliably prevented.

Subsequently, as shown in FIG.
A metal film as a film to be silicided, for example, titanium
After the (Ti) film 13A is formed by sputtering, the titanium
Film 13A is deposited and heat treated (Rapit Thermal Annie)
Hereinafter referred to as RTA. ) By adding silicide
Insulating film 9B and sidewall spacer film 9
By removing the titanium film 13A remaining on D, FIG.
As shown in (b), the surface layer of the drain region 7 is selected.
And self-aligned titanium silicide (TiSi _Two) Membrane 1
Form 3 In addition, RTA processing is excessive silicidation.
Is done in two steps to prevent the progress. That is, the first
The first RTA treatment was performed at about 650 ° C. to 700 ° C. for 10 hours.
~ 45 seconds, and then a second RTA process
At 750 ° C to 850 ° C for about 10 to 45 seconds
You.

Then, as shown in FIG. 6A, after an interlayer insulating film 9 made of a BPSG film is formed on the entire surface, a contact hole 11 is formed on the source / drain regions 7 and 8 so as to make contact. .Drain regions 7, 8
A contact plug (made of, for example, a tungsten film) 1 is formed via a barrier metal film (for example, a laminated film of a titanium film and a titanium nitride (TiN) film) not shown above.
0A, and a metal film 10B (for example, Al, Al-Si, Al-Si-C) is formed on the contact plug 10A.
u) is formed, and the metal wiring 10 is formed. In addition, for example, Al, Al-Si,
A metal wiring made of Al-Si-Cu may be formed. Here, since the titanium silicide film 13 is formed on the drain region 7, the contact resistance at the contact portion is reduced.

Hereinafter, another embodiment of the present invention will be described with reference to the drawings.

A feature of another embodiment of the present invention is to further enhance the function of the silicidation protection film 13 described above. For example, instead of the TEOS film 12A,
That is, an HTO film or a silicon nitride film is used.

That is, in the process description in the above-described embodiment, the description is omitted for convenience, but FIG.
5A, a wet cleaning process is performed in order to clean the Si surface of the portion to be silicided before the titanium film 13A is formed by sputtering after the silicidation protection film 12 is formed. ing.

At this time, the silicidation protection film 12 made of a TEOS film is also shaved and thinned (for example, 400Å → 2).
00Å) It is expected that the protective property is weakened and the effect of suppressing the reaction between the base Si and the titanium film 13A is weakened. Therefore, when the silicidation protection film 12 is broken and the underlying layer is silicided, the floating gate 4 and the source region 8
There is a risk of short circuit.

Therefore, in another embodiment of the present invention, the wet etching rate during the wet cleaning before the sputtering of the titanium film 13A is lower than that of the TEOS film 12A. For example, as shown in FIG. , The HTO film or the silicon nitride film constitutes the silicidation protection film 14.

As a result, the silicidized portion of Si
A margin for wet cleaning with HF (hydrofluoric acid) or the like at the time of cleaning the surface is increased, and silicidation of unnecessary portions can be suppressed.

Further, an additional (re) cleaning becomes possible by increasing the margin at the time of cleaning before sputtering of the titanium film 13A.

Further, prior to the formation of the titanium film 13A by sputtering, an impurity (for example, boron ion) is ion-implanted into the Si surface of the portion to be silicided, and this portion is made amorphous to promote silicidation. Is adopted, the impurity due to the implantation is L
It is also injected into the silicidation protection film 12 made of a PTEOS film. At this time, in the silicidation protection film 12 made of the LPTEOS film, the silicidation protection property is weakened by the influence of the implantation, but by changing to the silicidation protection film 14 made of the HTO film or the silicon nitride film, the implantation resistance is reduced. Can be improved.

[0043]

According to the present invention, a titanium film is formed in a state where a silicidation protection film made of an LPTEOS film is formed in a portion which is not to be silicided, and heat treatment is performed to silicide the titanium film. Region) and the titanium film can be suppressed.

Further, in order to suppress the abrasion of the silicidation protection film during cleaning before forming the titanium film by sputtering, H
By forming a silicidation protection film made of a TO film or a silicon nitride film, the wet etching rate is reduced to the TE
It is slower than the OS film, the etching margin is increased, silicidation into unnecessary portions can be reliably suppressed, and the risk of short-circuit between the floating gate and the source region can be avoided.

More specifically, in order to promote the silicidation, impurities are ion-implanted into the Si surface of the portion to be silicided before the titanium film is formed by sputtering, and when the portion is made amorphous, the HTO film is formed. A silicidation protection film made of a silicon nitride film or silicon nitride film has a high resistance to implantation and can reduce a weakening of the silicidation protection property due to the influence of the implantation.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a partial sectional view of FIG. 7;

FIG. 9 is a partially enlarged view of FIG. 8;

 ────────────────────────────────────────────────── ─── Continued from the front page F term (reference) PR21 PR34 PR36

Claims (8)

[Claims] 1. A floating gate formed on a silicon substrate of one conductivity type, an insulating film covering the floating gate, and a region overlapping the floating gate with the insulating film interposed therebetween. A control gate; a diffusion region of a reverse conductivity type formed on the surface of the silicon substrate adjacent to the floating gate and the control gate; and a metal wiring connected to the diffusion region via an interlayer insulating film. In the non-volatile semiconductor storage device, it is preferable that the metal wiring is formed on one diffusion region surface via a silicide film, and the metal wiring is formed on the other diffusion region surface without a silicide film. A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a silicidation protection film is formed on the surface of the other diffusion region so that a silicide film is not formed. A floating gate having a sharp corner formed on a silicon substrate of one conductivity type; a tunnel oxide film covering the floating gate; and a floating gate on the floating gate via the tunnel oxide film. A control gate formed so as to have a region that overlaps with; an insulating film formed so as to cover the floating gate and the control gate; and an insulating film formed on the surface of the silicon substrate adjacent to the floating gate and the control gate. A diffusion region of the opposite conductivity type to be formed, a silicide film formed on the surface of one of the diffusion regions, a silicidation protection film formed so as to cover at least a sharp corner on the floating gate, and an interlayer insulating film And a metal wiring connected to the diffusion region through A nonvolatile semiconductor memory device. 4. The non-volatile semiconductor memory device according to claim 2, wherein the silicidation protection film is a TEOS film, an HTO film, or a SiN film. 5. A floating gate formed on a silicon substrate of one conductivity type, an insulating film covering the floating gate, and a region overlapping the floating gate with the insulating film interposed therebetween. A method for manufacturing a nonvolatile semiconductor memory device comprising: a control gate; and a diffusion region of an opposite conductivity type formed on a surface of the silicon substrate adjacent to the floating gate and the control gate, wherein the floating gate and the control gate are provided. Forming an insulating film so as to cover the entire surface; forming a silicidation protection film on the entire surface; and then removing the silicidation protection film on one of the diffusion regions; and cleaning the entire surface, and then forming a silicided film on the entire surface. Forming a silicide by heat-treating the silicided film. Forming a metal wiring contacting the diffusion region via the interlayer insulating film after forming an interlayer insulating film, and a step of forming a metal wiring contacting the diffusion region via the interlayer insulating film after forming the interlayer insulating film. Manufacturing method of a nonvolatile semiconductor memory device. 6. A step of thermally oxidizing a surface of a silicon substrate of one conductivity type to form a gate oxide film; and forming a first conductive film on the gate oxide film;
Forming an oxidation resistant film having an opening of a predetermined pattern on the conductive film, and selectively oxidizing the first conductive film according to the opening to form a selective oxide film; Etching the first conductive film as a mask to form a floating gate having a sharp corner at an upper portion; forming a tunnel oxide film so as to cover the floating gate; Patterning the second conductive film after forming a second conductive film thereon to form a control gate so as to have a region overlapping the floating gate via a tunnel oxide film; Forming an insulating film so as to cover the control gate; the floating gate and the control gate Forming a diffusion region of the opposite conductivity type on the surface of the adjacent silicon substrate; removing the silicidation protection film on one of the diffusion regions after forming the silicidation protection film on the entire surface; and cleaning the entire surface. Forming a silicided film over the entire surface later, heat-treating the silicided film to form a silicide film, and then removing the silicided film that is not silicided; and forming an interlayer insulating film between the silicide films. Forming a metal wiring contacting the diffusion region with an insulating film interposed therebetween. 7. A step of thermally oxidizing a surface of a silicon substrate of one conductivity type to form a gate oxide film; and forming a first conductive film on the gate oxide film;
Forming an oxidation resistant film having an opening of a predetermined pattern on the conductive film, and selectively oxidizing the first conductive film according to the opening to form a selective oxide film; Etching the first conductive film as a mask to form a floating gate having a sharp corner at an upper portion; forming a tunnel oxide film so as to cover the floating gate; Patterning the second conductive film after forming a second conductive film thereon to form a control gate so as to have a region overlapping the floating gate via a tunnel oxide film; Forming an insulating film so as to cover the control gate; the floating gate and the control gate Forming a diffusion region of the opposite conductivity type on the surface of the adjacent silicon substrate; removing the silicidation protection film on one of the diffusion regions after forming the silicidation protection film on the entire surface; and cleaning the entire surface. A step of ion-implanting an impurity into the one diffusion region later; a step of forming a silicided film over the entire surface; and a heat treatment of the silicided film to form a silicide film and then not to be silicided after forming the silicide film. And a step of forming a metal wiring contacting the diffusion region via the interlayer insulating film after forming the interlayer insulating film, the method of manufacturing a nonvolatile semiconductor memory device. 8. The method according to claim 5, wherein the silicidation protection film is a TEOS film, an HTO film, or a SiN film.