JP2000223979A - Limiter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a limiting characteristic which prevents input power from being outputted equally to or more than a certain fixed level within a wide range of an input power level by respectively connecting an amplifier and a transmission line to two output terminals of a power distributor and performing reverse phase combination by a power combiner. SOLUTION: An amplifier 3 and a transmission line 10 are respectively connected to 1st and 2nd output terminals 8 and 9 of a power distributor 6 that attaches 90 deg. phase difference and distributes. Also, the output terminal 11 of the amplifier 3 is connected to the 1st input terminal 14 of a power combiner 13, the output terminal 12 of the line 10 is connected to the 2nd input terminal 15 of the combiner 13 and the combiner 13 which adds 90 deg. phase difference and performs combining, that is, adds 180 deg. phase difference and performs combining is provided. Then, the distributor 6 equally distributes one signal into two, one of the two signals is amplified by the amplifier 3, the other goes through the line 10 without being amplified and the two resultant signals are combined with reverse phases by the combiner 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a limiter circuit for reducing the amplitude of an output signal of a high-frequency amplifier to a certain value or less.

[0002]

2. Description of the Related Art A satellite communication repeater sometimes receives unexpectedly large input power. At that time, a semiconductor element such as a field effect transistor (hereinafter, FET) used for an amplifier or the like at the first stage of the repeater may be broken.
Therefore, a method is often used in which the output power is limited by using a limiter amplifier or the like which uses a FET having a wide gate width with a reduced drain voltage so that a subsequent amplifier does not fail due to excessive input.

[0003] For example, FIG. 8 is an equivalent circuit diagram of a conventional limiter amplifier shown at the 1993 Spring Meeting of the Institute of Electronics, Information and Communication Engineers (C-54). In this limiter amplifier, a first amplifier 3a, a second amplifier 3b, a first attenuator 4a,
A first isolator 5a, a third amplifier 3c and a fourth amplifier 3d, a second attenuator 4b,
b, and a fifth amplifier 3e and a sixth amplifier 3f are cascaded.

Next, the operation will be described. The signal input to the input terminal 1 is amplified in a linear region by the first to third amplifiers 3a to 3e. The output power of the signal amplified by the fifth amplifier 3e becomes constant using the nonlinearity of the sixth amplifier 3f. That is, the output power can be limited. If the power of the input signal further increases, then the fifth amplifier 3e takes advantage of the non-linearity to limit the output power of the fifth amplifier. Similarly, the output power of each of the first amplifier 3a to the fourth amplifier 3d is also limited by using the nonlinearity. In order to improve the limiter characteristics of each amplifier, the input return loss of each amplifier is degraded. Here, the first isolator 5a and the second isolator 5b
Are arranged to improve the input return loss of the amplifier. The first attenuator 4a and the second attenuator 4b are arranged for level adjustment between the second amplifier 3b and the third amplifier 3c and between the fourth amplifier 3d and the fifth amplifier 3e. The curve in FIG. 9 shows the power of the output signal with respect to the power of the signal input to the input terminal.

[0005]

Since the conventional limiter circuit is constructed as described above and uses a large number of isolators, attenuators, and FETs, the entire limiter circuit is very large and expensive. There was a problem.

Also, since many FETs are used,
It is necessary to make adjustments using a large number of matching circuits.
It is necessary to adjust the amount of attenuation of the attenuator used for adjusting the power level of the signal. Therefore, there is also a problem that much time is needed for adjustment.

Further, there is a problem in that a large number of FETs are used, so that a large amount of DC power is supplied, so that power consumption is increased.

Furthermore, since a large number of FETs and attenuators are used, there is a problem that the frequency characteristics are deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a limiter circuit which is small in size, easily adjusts an output signal, consumes low power, and has a wide band.

[0010]

A limiter circuit according to a first aspect of the present invention divides one signal into two equal parts, amplifies one of the two signals with an amplifier, and does not amplify the other with only a transmission line. Thus, the respective signals are combined in opposite phases.

[0011] Further, the limiter circuit according to the second invention comprises:
One signal is equally divided into two, and one of the two signals is amplified by an amplifier, the other is attenuated by an attenuator, and the signals are combined in opposite phases.

Further, the limiter circuit according to the third aspect of the present invention comprises:
One signal is divided equally into two, and one of the two signals is amplified by an amplifier, an attenuator is connected to the output terminal of the amplifier and attenuated, and the other is not amplified only by the transmission line. Are synthesized in opposite phases.

The limiter circuit according to a fourth aspect of the present invention comprises:
One signal is equally divided into two, one of the two signals is amplified by an amplifier, and the other is changed in phase only by a phase shifter, and the respective signals are combined in opposite phases.

The limiter circuit according to a fifth aspect of the present invention comprises:
One signal is divided equally into two, one of the two signals is amplified by an amplifier, a phase shifter is connected to the output terminal of the amplifier to change the phase, and the other is not amplified only by the transmission line, These signals are combined in opposite phases.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is an equivalent circuit diagram of a limiter circuit according to Embodiment 1 of the present invention. In FIG. 1, 1 is an input terminal, 2 is an output terminal,
6 is a power divider, 7 is an input terminal of the power divider, 8 and 9 are first and second output terminals of the power divider, 3 is an amplifier, 10 is a transmission line, and 11 is an amplifier 3 An output terminal, 12 is an output terminal of the transmission line 9, 13 is a power combiner, 14 and 15 are first and second input terminals of the power combiner, and 16 is an output terminal of the power combiner.

This limiter circuit is an interdigital,
A power divider 6 using a branch line coupler, a rat race, or the like, for distributing with a phase difference of 90 °, and connected to a first output terminal 8 and a second output terminal 9 of the power divider 6. The output terminal 11 of the amplifier 3 is connected to the amplifier 3, the transmission line 10, and the first input terminal 14 of the power combiner 13, and the output terminal of the transmission line 10 is connected to the second input terminal 15 of the power combiner 13. 12 and a power combiner 13 for combining with a phase difference of 90 °, that is, combining with a phase difference of 180 °. At this time, the transmission line 1
The electrical length of 0 is the same as the electrical length of the amplifier 3.

The amplifier 3 is for amplifying microwaves. As shown in FIG. 2, an FET 17 for amplifying microwave signals and a matching for impedance matching provided at the input / output unit of the FET 17 are provided. Circuit 18,
19, a gate bias circuit 20 for setting a bias voltage from DC power to a desired value and applying a bias voltage to the FET 17 without affecting the amplifier characteristics, and a drain bias circuit 21. The bias voltage from the DC power to the amplifier is supplied to the gate bias terminal 22 and the drain bias terminal 23.

In the limiter circuit of the first embodiment, an input signal inputted from an input terminal 1 in FIG. 1 is converted to an input terminal 7 of a power distributor, a power distributor 6, and a first output of the power distributor 6. A signal passing through a route of a terminal 8, an amplifier 3, an output terminal 11 of the amplifier, a first input terminal 11 of the power combiner and a power combiner 13, an output terminal 16 of the power combiner and an output terminal 2; Input terminal 7, power divider 6, second output terminal 9 of power divider, transmission line 10, output terminal 12 of transmission line, second input terminal 15 of power combiner, power combiner 13, power combiner The signal transmitted through the output terminal 16 of the vessel and the signal transmitted through the path of the output terminal 2 are combined in opposite phases. The power divider 6 distributes the input signal power to the two paths for the time being, and the power combiner 13 combines with the line loss and the loss due to the phase shift.

The path passing through the amplifier 3 has a constant power gain due to the characteristics of the amplifier 3, and the output power increases as the input power increases. Further, the saturation output power of the amplifier is determined depending on the gate width of the FET 17 in FIG. 2 and the voltage of the applied drain bias. At a certain level Psat as shown by the curve in FIG. Saturates. That is, the power gain decreases as the input power increases. Further, in a route passing through the transmission line 10,
With the input power, the output power also increases with a small loss. As shown in the path through the amplifier 3, there is no decrease such as the saturation of the output power, and the straight line of FIG. 3B is obtained.

When the input power to the limiter circuit of the first embodiment is small, that is, when the amplifier is operating linearly, the power input to the power combiner 13 from the path of the transmission line 10 is Since the power input to the power combiner 13 is sufficiently smaller than the power input to the power combiner 13, the power input to the power combiner 13 from the path of the transmission line 10 can be neglected. It has almost the same characteristics. When the input power increases, the input power input to the amplifier 3 also increases, and the amplifier 3 operates non-linearly. That is, as the input power increases, the power gain of the amplifier decreases, and the transmission line 10 gradually decreases.
The power input to the power combiner 13 from the path cannot be ignored. The power input to the power combiner 13 from the path of the transmission line 10 has a passing phase difference of 180 ° with respect to the power input to the power combiner 13 from the path of the amplifier 3. Synthesized in reversed phase. Thereby, the output power of the limiter circuit is reduced as compared with the power input from the amplifier 3 to the power combiner 13.

The conventional amplifier reaches the maximum output power level Psat at Pi1 in FIG. However, as in the first embodiment, one signal is divided into two, one is amplified by the amplifier 3, and the other is transmitted by the transmission line 10, and the signals are combined in opposite phases. , And a curve C in FIG. When the input power becomes larger than around Pi1, the output power from the limiter circuit of the first embodiment decreases due to the influence of the signal input from the transmission line 10 to the power combiner 13. At the point where the input power is Pi3, the power level of the signal input from the amplifier 3 to the power combiner 13 and the power level of the signal input from the transmission line 10 to the power combiner 13 become extremely small, and the output power becomes extremely small. When the input power exceeds Pi3, the power combiner 13
Is higher than the power of the signal input from the amplifier 3, the output power from the limiter circuit of the first embodiment is again increased. That is, it is possible to increase the input power at which the output power exceeds a certain level.

Embodiment 2 FIG. FIG. 4 is an equivalent circuit diagram of the limiter circuit according to the second embodiment of the present invention. This limiter circuit has an attenuator 24 provided between the output terminal 12 of the transmission line and the second input terminal of the power combiner in the first embodiment shown in FIG.

In the first embodiment, when the input power is Pi3 in FIG. 3, the signal input from the transmission line 10 to the second input terminal 15 of the power combiner and the output terminal 11
The signal input to the first input terminal 14 of the power combiner is subjected to reverse phase synthesis at the same level to minimize the signal level. However, in the limiter circuit of the second embodiment, the attenuator 24
Is connected between the output terminal 12 of the transmission line and the second input terminal 15 of the power combiner, the point at which the output signal level of the limiter circuit becomes minimum becomes larger than Pi3 in FIG.

As described above, by providing the attenuator 24 between the output terminal 12 of the transmission line and the second input terminal 15 of the power combiner, the input power level at which the output power level of the limiter circuit is minimized And the dynamic range of the limiter circuit is increased.

Embodiment 3 FIG. 5 is an equivalent circuit diagram of a limiter circuit according to Embodiment 3 of the present invention. This limiter circuit has an attenuator 24 provided between the output terminal 10 of the amplifier and the first input terminal 14 of the power combiner in the first embodiment shown in FIG.

In the first embodiment, when the input power is Pi3 in FIG. 3, the signal input from the output terminal 12 of the transmission line to the second input terminal 15 of the power combiner and the output terminal 11 of the amplifier The signal input to the first input terminal 14 of the power combiner is subjected to reverse-phase synthesis at the same level to minimize the signal level. However, in the limiter circuit according to the third embodiment,
By connecting the attenuator 24 between the output terminal 11 of the amplifier and the first input terminal 14 of the power combiner, the point at which the output signal level of the limiter circuit is minimized is Pi3 in FIG.
Smaller than.

Further, by connecting the attenuator 24 between the output terminal 11 of the amplifier and the first input terminal 14 of the power combiner, the saturation output power of the amplifier is reduced. Therefore, the limiter circuit according to the third embodiment has an advantage that the output power of the limiter circuit is reduced.

Embodiment 4 FIG. 6 is an equivalent circuit diagram of a limiter circuit according to Embodiment 4 of the present invention. This limiter circuit has a phase shifter 26 provided between the output terminal 12 of the transmission line and the second input terminal 15 of the power combiner in the first embodiment shown in FIG.

In the first embodiment, when the input power is Pi3 in FIG. 3, the signal input from the output terminal 12 of the transmission line to the second input terminal 15 of the power combiner and the output terminal 11 of the amplifier The signal input to the first input terminal 14 of the power combiner is subjected to reverse-phase synthesis at the same level to minimize the signal level. However, in the limiter circuit according to the fourth embodiment,
By connecting the phase shifter 26 between the output terminal 12 of the transmission line and the second input terminal 15 of the power combiner, Pi3
In this case, the signal level is the minimum, but the signal level is higher than in the first embodiment.

As described above, by inserting the phase shifter 26 between the output terminal 12 of the transmission line and the second input terminal 15 of the power combiner, the minimum level of the output power of the limiter circuit increases, There is an advantage that a significant decrease in signal level is eliminated.

Embodiment 5 FIG. 7 is an equivalent circuit diagram of a limiter circuit according to Embodiment 2 of the present invention. This limiter circuit has a phase shifter 26 provided between the output terminal 11 of the amplifier and the first input terminal 14 of the power combiner in the first embodiment shown in FIG.

In the first embodiment, when the input power is Pi3 in FIG. 3, the signal input from the output terminal 11 of the transmission line to the second input terminal 15 of the power combiner and the signal input from the output terminal of the amplifier The signal input to the first input terminal 14 of the power combiner is reverse-phase-combined at the same level to minimize the signal level. However, in the limiter circuit according to the fifth embodiment, the phase shifter 26 is connected to the output of the amplifier. By connecting between the terminal 11 and the first input terminal 14 of the power combiner, the fourth embodiment
In the case of Pi3, the signal level becomes minimum, but the signal level becomes higher than that in the first embodiment.

As described above, in the limiter circuit according to the fifth embodiment, the phase shifter 26 is connected between the output terminal 11 of the amplifier and the first input terminal 14 of the power combiner. As in the case of the limiter circuit, there is an advantage that the minimum level of the output power of the limiter circuit is increased, and an extreme decrease in the signal level is prevented.

[0034]

According to the first aspect of the present invention, an amplifier and a transmission line are connected to two output terminals of the power divider, respectively, and the power combiner performs opposite-phase combining, thereby providing a wide range of input power levels. Thus, it is possible to obtain a limiting characteristic that does not output a certain level or more.

Also, since only one FET is used, the power consumption is small and the cost is low. Since the isolator is not used, it is miniaturized, and a power divider for distributing with a phase difference of 90 ° and a power divider of 90 ° are used. Since a power combiner that combines signals with a phase difference is used, a good VSWR characteristic can be obtained.

According to the second aspect, the attenuator is provided between the output terminal of the transmission line and the power combiner, so that the input power level at which the output power level of the limiter circuit is minimized is increased, and the input power level is further reduced. In a wide range of power levels, it is possible to obtain a limiting characteristic that does not output a certain level or more.

According to the third aspect, the output power of the limiter circuit is lowered by inserting an attenuator between the output terminal of the amplifier and the power combiner, and the output power of the limiter circuit is kept constant over a wide range of the input power level. It is possible to obtain a limiting characteristic that does not output a level or more.

According to the fourth aspect, an attenuator is provided between the output terminal of the transmission line and the power combiner, thereby avoiding an extreme decrease in output power level as compared with the first aspect, and reducing the input power level. Over a wide range, it is possible to obtain a limiting characteristic that does not output a certain level or more.

According to the fifth aspect of the present invention, an attenuator is provided between the output terminal of the amplifier and the power combiner. It is possible to obtain a limiting characteristic in which output is not output beyond a certain level over a wide range of the input power level while avoiding a decrease.

[Brief description of the drawings]

FIG. 1 is a first embodiment of a limiter circuit according to the present invention;
FIG.

FIG. 2 is a diagram illustrating a configuration of a unit amplifier.

FIG. 3 is an amplifier constituting a limiter circuit according to the present invention;
FIG. 4 is a diagram illustrating output power with respect to input power of a transmission line and a limiter circuit.

FIG. 4 is a second embodiment of a limiter circuit according to the present invention;
FIG.

FIG. 5 is a third embodiment of a limiter circuit according to the present invention;
FIG.

FIG. 6 is a limiter circuit according to a fourth embodiment of the present invention;
FIG.

FIG. 7 is a limiter circuit according to a fifth embodiment of the present invention;
FIG.

FIG. 8 is a diagram showing a conventional limiter circuit.

FIG. 9 is a diagram showing output power with respect to input power of a conventional limiter circuit.

[Explanation of symbols]

Reference Signs List 1 input terminal, 2 output terminal, 3 amplifier, 4 attenuator, 5 isolator, 6 power splitter, 7 input terminal of power splitter, 8 first output terminal of power splitter, 9
Second output terminal of the power divider, 10 transmission line, 11
Output terminal of amplifier, 12 Output terminal of transmission line, 13
Power combiner, 14 first input terminal of power combiner, 15
1st input terminal of power combiner, 16 output terminal of power combiner, 17 FET, 18 matching circuit, 19 matching circuit, 20 gate bias circuit, 21 drain bias circuit, 22 gate bias terminal, 23 drain bias terminal, 24 Attenuator, 25 output terminal of attenuator,
26 Phaser, 27 Output terminal of phaser.

Claims (5)

[Claims] An input terminal and a first and a second output terminal, wherein a phase is compared with a phase between the input terminal and the first output terminal.
A power divider that distributes a signal with a phase between the input terminal and the second output terminal delayed by 90 °, a first input terminal, a second input terminal, and an output terminal; A power combiner that combines a signal with a phase between the second input terminal and the output terminal being delayed by 90 from the phase between the output terminals, and a first output terminal of the power divider and a first of the power combiner. A limiter circuit provided between input terminals and comprising an amplifier using a semiconductor element, and a transmission line provided between a second output terminal of the power divider and a second input terminal of the power combiner. 2. The limiter circuit according to claim 1, wherein an attenuator is provided between an output terminal of the transmission line and a second input terminal of the power combiner. 3. The limiter circuit according to claim 1, further comprising an attenuator connected in series to said amplifier. 4. The limiter circuit according to claim 1, wherein a phase shifter is provided between an output terminal of the transmission line and a second input terminal of the power combiner. 5. The limiter circuit according to claim 1, further comprising a phase shifter connected in series to said amplifier.