JP2000223595A - Semiconductor device and its fabrication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce chip size by integrating a plurality of memory cells in a plurality of ROMs arranged in X direction as word lines and connecting the drain regions and source regions of a plurality of memory cells arranged in Y direction commonly with respective bit lines and source lines. SOLUTION: Source region 23 and drain region 24 on the major surface of a semiconductor substrate 1 is covered with an insulation film 7 of silicon oxide and laminated with a gate 28 of polycide film laminated with a polysilicon film and a high melting point metal silicide, e.g. tungsten silicide, through a gate insulation film 26 of silicon oxide film. The gate 28 is connected with the gate 28 of an FET in other block adjacent in X direction by specified number and it is a word line extending in X direction. A common source line is connected with a common source region 23 and a main bit line is connected with a common drain region 24 through a select FET provided at the other end of each element forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a nonvolatile memory element having a two-layer gate structure and a method of manufacturing the same, and more particularly to a technique which is effective when applied to improvement of the disturb characteristics of the nonvolatile memory element. is there.

[0002]

2. Description of the Related Art Some semiconductor memory devices use an FET having a two-layer gate structure including a control gate and a floating gate.
Charges are injected into or extracted from the floating gate, and information is stored depending on the presence or absence of charges in the floating gate. Since the floating gate is surrounded by the insulating film and is not connected to the external wiring, the injected charge remains even when power is not applied, and does not require a power supply to hold information. Can be used as

In a semiconductor memory device using such storage elements, as shown in FIG. 1, a memory cell array in which a plurality of storage elements are arranged in a matrix form in a plane, and a row address signal and a column address signal are supplied to the memory cell array. An X decoder and a Y decoder for selecting a predetermined memory cell, a command decoder for writing / reading data to / from the selected memory cell, and a control circuit such as a booster circuit are provided.

As a memory cell array, an AND type, NA,
Various circuit configurations such as ND type, NOR type, and DINOR type have been considered. For example, in the AND type memory cell array shown in FIG. 2, the control gates of a plurality of memory cells arranged in the row direction are integrated to form a word line WL,
A drain region of a plurality of memory cells arranged in a column direction is commonly connected to a sub-bit line, a source region of a plurality of memory cells arranged in a column direction is commonly connected to a source line, and the sub-bit line is a selection FET. And the source line is connected to a common source line via a selection FET.

In such an AND type memory cell, information is rewritten by applying a predetermined voltage to each of a source region, a drain region, a control gate, and a substrate to inject / emit electrons to / from a floating gate.

More specifically, in the write operation, the drain selection FET is turned on, a voltage of about 0 V to 6 V is applied to the drain region, the source selection FET is turned off, the source region is floated, and the selected word line is turned off. At 16
By applying a high voltage of about V, charges are injected into the floating gate to increase the threshold voltage.

On the other hand, in the read operation, the drain selection FE
Turn on T, apply a voltage of about 1 V to the drain region, turn on the source selection FET, apply a voltage of about 2 V to the source region, apply a voltage of about 2 V to the substrate, and apply a voltage of about 2 V to the selected word line. By applying a voltage of about 3 V, the magnitude of the threshold voltage, that is, the presence or absence of information is determined based on the magnitude of the current flowing between the drain and the source.

In the erasing operation, a drain selection FET is used.
Is turned on and a voltage of about 2 V is applied to the drain region,
The source select FET is turned on, a voltage of about 2 V is applied to the source region, a voltage of about 2 V is applied to the substrate, and a high voltage of about -16 V is applied to the selected word line, thereby injecting the floating gate. The charge thus obtained is extracted using a tunnel current to lower the threshold voltage.

In such a memory cell having a two-layer gate structure, the characteristics are somewhat different for each memory cell, and when operated under a single condition, a memory cell that does not meet the condition may be operated. It is not possible, and the number of available memory cells is limited, making it difficult to increase the capacity. Therefore, in order to increase the number of operable memory cells, it is necessary to change operating conditions according to the characteristics of the memory cells.

[0010] Further, by repeating the above-mentioned writing and erasing, a small amount of charge remaining in the floating gate is accumulated, thereby causing a change in characteristics over time.
In order to cope with such a characteristic change, it is necessary to perform a complicated operation such as changing operating conditions such as an applied voltage or an application time depending on the number of times of voltage application.

In order to perform such a complicated operation, it is necessary to record the detailed operation conditions in advance.
For this purpose, a read-only storage element such as a ROM (Read O
nly Memory) is built in a semiconductor memory device. Also, some semiconductor devices have a ROM for mounting a program for performing circuit debugging, operation assurance test, and the like.

[0012]

As a memory cell of such a ROM, a cell substantially the same as a normal FET is used, and the presence or absence of information is determined by the presence or absence of conduction at the time of selection. In the case of non-conduction at the time of selection, a method of not implanting impurities into the source region and the drain region or not connecting a wiring is adopted.

As a circuit configuration of the ROM, a NOR type (referred to as a horizontal ROM) and a NAND type (referred to as a vertical ROM)
However, a NOR type is usually used for the built-in type, with emphasis on random access.

In such a NOR type circuit configuration, each memory cell is connected to a bit line and a source line, respectively.
For example, in the layout of the NOR type memory cell array shown in FIG. 3, control gates of a plurality of memory cells arranged in a row direction are integrated to form a word line WL, and drain regions of a plurality of memory cells arranged in a column direction are formed. D is connected to the bit line BL at each connection region CNT, and source regions S of a plurality of memory cells arranged in the row direction are commonly connected on the main surface of the semiconductor substrate.

As described above, by making the source region a common region on the main surface of the semiconductor substrate, contact for each cell can be made unnecessary, but contact with the bit line is made for each cell or for two adjacent cells. Connection area CN for each cell
T is required. Therefore, providing the connection region CNT in the memory cell increases the cell size, which causes a problem that the chip size of the semiconductor memory device increases.

This problem increases as the capacity of the mounted ROM increases. For example, in a nonvolatile semiconductor memory device, in order to increase the capacity without increasing the chip size, multi-valued storage of two or more bits of information in a single memory cell has been promoted. It is necessary to set more complicated operating conditions for the memory cell
The OM also has a larger capacity. In addition, a test program and the like are complicated, and a required ROM is also increased in capacity. By increasing the capacity of such a ROM, R
The area occupied by the OM increases, and therefore the chip size increases.

An object of the present invention is to provide a technique capable of reducing a chip size by reducing a cell size of a ROM incorporated in a semiconductor device. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows. In a semiconductor device provided with a plurality of FET-type ROMs, the plurality of ROMs are word lines by integrating gates of a plurality of memory cells arranged in an X direction, and a plurality of memories arranged in a Y direction. The drain region of the cell is commonly connected to a bit line, and the source regions of a plurality of memory cells arranged in the Y direction are commonly connected to a source line. According to the above-described means, for the memory cell of the ROM, the contact for each cell is eliminated,
It is possible to reduce the cell size to the same size as the nonvolatile memory element.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0020]

FIG. 4 is a longitudinal sectional view showing a section along a word line extending in a row direction of an AND type memory cell array of a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a longitudinal sectional view showing a section in the column direction orthogonal to the word lines of the memory cell array.

In the memory cell array of this embodiment, the main surface of the semiconductor substrate 1 made of single crystal silicon or the like is
element isolation insulating film 2 by allow Trench Isolation)
A predetermined number of storage elements having a double-layer gate structure are continuously formed in the column direction in each of the element formation regions divided by the column, and a unit block is formed by the predetermined number of storage elements, and a plurality of storage elements forming the same block are formed. The source region 3 and the drain region 4 are formed continuously, respectively, so that the source region 3 and the drain region 4 are shared by each block, and the storage elements are connected in parallel.

The floating gate 5 having a two-layer gate structure serving as a memory element is provided on the main surface of the semiconductor substrate 1 with a gate insulating film 6 interposed therebetween.
Is composed of a lower film 5a provided between the source region 3 and the drain region 4, and an upper film 5b laminated on the lower film 5a and extending over the source region 3 and the drain region 4 to the region of the element isolation insulating film 2. The source regions 3 and 5 are self-aligned with the lower film 5a of the floating gate 5.
A drain region 4 is formed.

The source region 3 and the drain region 4 on the main surface of the semiconductor substrate 1 are covered with an insulating film 7 made of silicon oxide, and the upper layer film 5b of the floating gate 5 has the source region 3 and the drain Extending over region 4,
It is separated from the adjacent upper layer film 5b on the element isolation insulating film 2. By providing the upper film 5b, the channel length defined by the lower film 5a can be increased without increasing the channel length.
The coupling capacitance between the floating gate 5 and the control gate 8 can be increased.

The upper layer film 5b is provided with a polycrystalline silicon film and a tungsten silicide or the like via an inter-gate insulating film 9 composed of an ONON film in which a silicon oxide film, a silicon nitride film, a silicon oxide film, and a silicon nitride film are laminated. A control gate 8 made of a polycide film formed by laminating a metal silicide having a melting point is laminated. The control gate 8 is connected to a predetermined number of control gates 8 of FETs in another block adjacent in the row direction, and a word extending in the row direction. It is a line.

The upper surface of the control gate 8 is covered with a cap 10 made of silicon oxide or the like. The cap 10 serves as a mask when processing the control gate 8 and the floating gate 5, and an adjacent two-layer gate is formed. The space between the side spacers 11 made of silicon oxide or the like
Are separated by

As a memory cell array, a first metal wiring layer 13 which extends in the column direction, for example, and is used as a common source line via an interlayer insulating film 12 is formed on the FET having the two-layer gate structure. And the first metal wiring layer 13
A second-layer metal wiring layer 15 extending in the column direction, for example, and being used as a main bit line is formed on the upper side via the interlayer insulating film 14.

The common source line is connected to a common source region 3 via a selection FET (not shown) provided at one end of each element forming region, and the main bit line is connected to a common bit line.
The common drain region 4 is connected via a selection FET (not shown) provided at the other end of each element formation region. Then, a protective insulating film 16 covering the second metal wiring layer 15 and protecting and insulating the entire surface of the semiconductor device is formed on the entire surface using silicon nitride or polyimide.

In the AND type memory cell of this embodiment,
Rewriting of information is performed by applying a predetermined voltage to each of the source region, the drain region, the control gate, and the substrate, and injecting / emitting electrons into / from the floating gate. Specifically, in the write operation, the drain selection FET is turned on, a voltage of about 0 V to about 6 V is applied to the drain region, the source selection FET is turned off to make the source region floating, and about 16 V is applied to the selected word line. By applying a high voltage, charges are injected into the floating gate to increase the threshold voltage.

On the other hand, in the read operation, the drain selection FE
Turn on T, apply a voltage of about 1 V to the drain region, turn on the source selection FET, apply a voltage of about 2 V to the source region, apply a voltage of about 2 V to the substrate, and apply a voltage of about 2 V to the selected word line. By applying a voltage of about 3 V, the magnitude of the threshold voltage, that is, the presence or absence of information is determined based on the magnitude of the current flowing between the drain and the source.

In the erase operation, the drain selection FET
Is turned on and a voltage of about 2 V is applied to the drain region,
The source select FET is turned on, a voltage of about 2 V is applied to the source region, a voltage of about 2 V is applied to the substrate, and a high voltage of about -16 V is applied to the selected word line, thereby injecting the floating gate. The charge thus obtained is extracted using a tunnel current to lower the threshold voltage.

Next, a ROM mounted on the semiconductor device of the present embodiment will be described. FIG. 6 is a circuit diagram showing a configuration of a memory cell array of a ROM mounted on the semiconductor device according to the present embodiment. FIG. 7 is a plan view showing a layout of the memory cells. FIG. 9 is a longitudinal sectional view showing a section taken along a word line extending in the row direction of FIG. 1, and FIG. 9 is a longitudinal sectional view showing a section taken in a column direction orthogonal to the word lines of the memory cell array.

In the ROM memory cell array of the present embodiment, the main surface of the semiconductor substrate 1 using single crystal silicon or the like is
A predetermined number of storage elements are continuously formed in the column direction in each element formation region divided by the element isolation insulating film 2 by TI or the like, and a unit block is formed by the predetermined number of storage elements to form the same block. By forming a plurality of source regions 23 and drain regions 24 of the storage element continuously, the source region 23 and the drain region 24 are shared by each block, and an AND type in which the storage elements are connected in parallel. Configuration.

In the FET serving as a storage element, the semiconductor substrate 1
The source region 23 and the drain region 24 on the main surface are covered with an insulating film 7 made of silicon oxide, and a polycrystalline silicon film and a high melting point metal silicide such as tungsten silicide are interposed via a gate insulating film 26 made of a silicon oxide film. A gate 28 made of a polycide film on which a product is
Reference numeral 8 denotes a word line that is connected to a predetermined number of gates 28 of FETs of another block adjacent in the row direction and extends in the row direction.

The gate 28 is covered on its upper surface with a cap 10 made of silicon oxide or the like. The cap 10 serves as a mask when processing the gate 28, and a side wall made of silicon oxide or the like is provided between adjacent gates. Spacer 3
Separated by 0.

As the memory cell array, a first metal wiring layer 13 extending in the column direction, for example, and used as a common source line is formed on the FET via an interlayer insulating film 12, and a first layer is formed. On the first metal wiring layer 13, a second metal wiring layer 15 which extends in the column direction, for example, and is used as a main bit line via an interlayer insulating film 14 is formed.

The common source line is connected to a common source region 23, and the main bit line is connected via a selection FET (not shown) provided at the other end of each element formation region. Drain region 24 is connected.
Then, a protective insulating film 16 covering the second metal wiring layer 15 and protecting and insulating the entire surface of the semiconductor device is formed on the entire surface using silicon nitride or polyimide.

In the ROM of the present invention, since the circuit configuration is of the AND type, the contact for each memory cell is eliminated, so that the cell size can be reduced to the same size as the nonvolatile memory element. When used as a memory,
Depending on whether or not impurities are introduced into at least one of the source region 23 and the drain region 24, whether or not it functions as an FET, that is, by applying a voltage of about 3 V to a selected word line, a current flows between the drain and source. The magnitude of the threshold voltage, that is, the presence or absence of information is determined based on the magnitude of the current.

Next, a method of manufacturing the above-described nonvolatile memory element and ROM of the semiconductor device will be described with reference to FIGS.
The process will be described for each process. In each figure, the ROM is shown on the right side of the figure, and the nonvolatile memory element in the same step is shown on the left side.

First, silicon oxide is deposited in a groove formed on the main surface of the semiconductor substrate 1 by photolithography and dry etching, and the main surface of the semiconductor substrate 1 is formed by an STI element isolation insulating film 2 polished and planarized by CMP. It is divided into each element formation region. A mask is formed by photolithography and etching according to the semiconductor type of each of the divided element forming regions, that is, the p-type or the n-type of the main surface of the semiconductor substrate, and the insulation is thinly left on each of the element forming regions by the planarization. Impurities are introduced by ion implantation through the film, and each well region is formed for each predetermined semiconductor type.

A gate insulating film 7 is formed on the main surface of the semiconductor substrate 1 in the element formation region by thermal oxidation, and polycrystalline silicon to be a lower layer film 5a of the floating gate 5 is deposited, for example, a silicon oxide film is deposited. Using a resist mask formed by photolithography, the silicon oxide film is patterned to form a cap 25, and using the cap 25 as a mask, polycrystalline silicon is patterned into the lower film 5a. The lower film 5a is also formed in the memory cell of the ROM.

Subsequently, the source region 3, the drain region 4 of the nonvolatile memory element and the source region 23 and the drain region 23 of the ROM are formed by ion implantation using the lower film 5a and the cap 25 as a mask. In the case of a ROM memory cell, the source region 23 and the drain region 23
The presence or absence of information may be stored by selectively performing the formation. This state is shown in FIG.

Next, an insulating film 7 made of silicon oxide is formed on the main surface of the semiconductor substrate 1 in the source region 3 and the drain region 4 by, for example, CVD, and polycrystalline silicon to be the upper layer 5b of the floating gate 5 is deposited on the entire surface. Then, patterning is performed, and the upper layer film 5b extends on the insulating film 7 and is separated for each block on the element isolation insulating film 2. This state is shown in FIG.

Next, an ONON film formed by laminating a silicon oxide film, a silicon nitride film, a silicon oxide film, and a silicon nitride film is deposited on the entire surface.
The ON film is removed, and the floating gate 5 is further removed. This ONON film becomes an inter-gate insulating film 9 between the floating gate 5 and the control gate 8. This state is shown in FIG.

Next, the gate insulating film 26 of the ROM memory cell is formed by the peripheral circuit gate insulating film forming step, and the threshold control of the ROM memory cell is controlled by the FE of the peripheral circuit.
The presence / absence of information may be stored by utilizing the steps of photolithography of T formation and impurity introduction. Subsequently, a polycide film is formed by laminating a polycrystalline silicon film and a high melting point metal silicide such as tungsten silicide, and is separated for each FET using the cap 10 made of silicon oxide formed on the polycide film as a mask. After patterning, control gate 8 of each block
Are connected by a predetermined number to form word lines extending in the row direction. A single-layer film of polycrystalline silicon may be used as the word line.

By patterning the word line or using the word line as a mask, so-called overlap cutting for patterning between the inter-gate insulating film 12 and the floating gate 5 is performed, and the control gate 8 is formed.
The floating gate 5 is separated for each storage element by self-alignment. Similarly, in the case of the ROM, each of the FEs is
Perform patterning to separate for each T, RO of each block
A predetermined number of M gates 28 are connected to form a word line extending in the row direction. Thereafter, a side spacer 11 for insulating between word lines is formed of, for example, silicon oxide, and an interlayer insulating film 12 covering the control gate 8 and the gate 28 is formed.
To form This state is shown in FIG.

Thereafter, an opening is provided in the interlayer insulating film 12, and a first wiring layer 13 used as, for example, a common source line is formed on the interlayer insulating film 12 by using, for example, aluminum mainly by sputtering. The wiring layer 13 is covered with an interlayer insulating film 14, an opening is provided in the interlayer insulating film 14, and a second wiring layer 15 used as, for example, a main bit line is formed on the interlayer insulating film 14 by using, for example, aluminum mainly by sputtering. To form the wiring layer 15 on the protective insulating film 16
4, 5, 8 and 9.

As described above, since the ROM of the present invention can be formed by using the steps of forming the non-volatile memory element and the FET of the peripheral circuit, the number of steps for forming the ROM does not increase.

As described above, the invention made by the present inventor
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0049]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, a memory cell of a ROM
There is an effect that the cell size can be reduced to the same size as the nonvolatile memory element by eliminating the contact for each cell. (2) According to the present invention, since the nonvolatile memory element and the peripheral circuit can be formed by using the FET forming process, there is an effect that the number of processes is not increased for forming the ROM.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a semiconductor device on which a nonvolatile memory element is mounted.

FIG. 2 is a circuit diagram showing a circuit configuration of an AND-type memory cell array using a nonvolatile storage element.

FIG. 3 is a plan view showing a memory cell array of a conventional ROM.

FIG. 4 is a longitudinal sectional view showing a nonvolatile memory element of the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a longitudinal sectional view showing a nonvolatile memory element of the semiconductor device according to one embodiment of the present invention;

FIG. 6 shows an RO of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a circuit diagram showing a circuit configuration of an M memory cell array.

FIG. 7 illustrates an RO of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a plan view showing an M memory cell array.

FIG. 8 shows an RO of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a longitudinal sectional view showing an M memory cell.

FIG. 9 illustrates an RO of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a longitudinal sectional view showing an M memory cell.

FIG. 10 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 12 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 13 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3,23,
... Source region, 4,24 ... Drain region, 5 ... Floating gate, 5a ... Lower film, 5b ... Upper film, 6,26
... gate insulating film, 7 ... insulating film, 8 ... control gate, 28 ... gate, 9 ... inter-gate insulating film, 10, 25 ...
Caps, 11, 30, side spacers, 12, 14, ...
Interlayer insulating films, 13, 15: wiring layer, 16: protective insulating film.

Continued on the front page F term (reference) 5F001 AA25 AB08 AC02 AD12 AD41 AE02 AE03 AE08 AF06 AF07 AG07 AG15 AG40 5F083 CR02 CR03 EP02 EP23 EP55 EP79 ER03 ER14 ER19 ER22 ER30 GA09 GA11 GA21 GA22 GA28 GA30 JA04 JA36 KA01 MA01 MA01 PR29 PR43 PR45 PR53 PR55 ZA14 ZA20

Claims (9)

[Claims] 1. A semiconductor device provided with a plurality of FET-type ROMs, wherein the plurality of ROMs form word lines by integrating gates of a plurality of memory cells arranged in an X direction and are arranged in a Y direction. A drain region of the plurality of memory cells is commonly connected to a bit line, and a source region of the plurality of memory cells arranged in the Y direction is commonly connected to a source line. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided with a storage circuit using a nonvolatile memory element having a two-layer gate structure provided with a floating gate. 3. The storage circuit according to claim 1, wherein the storage circuit has an AND circuit configuration using a flash memory.
Alternatively, the semiconductor device according to claim 2. 4. A method of manufacturing a nonvolatile memory element having a two-layer gate structure provided with a floating gate and a control gate, a peripheral circuit, and a semiconductor device provided with a plurality of ROMs, comprising: a gate insulating film of the ROM; A method of manufacturing a semiconductor device, comprising: forming a gate insulating film of a circuit; and forming a gate of the ROM and the control gate. 5. The method according to claim 4, wherein the nonvolatile storage element is a flash memory and is a storage circuit having an AND circuit configuration. 6. A storage circuit using a nonvolatile storage element having a two-layer gate structure provided with a floating gate, and a plurality of ROMs formed by electrically conducting the two-layer gate. Semiconductor device. 7. The memory circuit according to claim 6, wherein the storage circuit has an AND circuit configuration using a flash memory.
3. The semiconductor device according to claim 1. 8. Manufacturing of a semiconductor device having a storage circuit using a nonvolatile storage element having a two-layer gate structure provided with a floating gate and a plurality of ROMs formed by electrically conducting the two-layer gate. A method, comprising: a source region and a drain region of the nonvolatile storage element;
A method of manufacturing a semiconductor device, comprising forming a source region and a drain region of the plurality of ROMs in the same step. 9. The method according to claim 8, wherein the nonvolatile storage element is a flash memory and is a storage circuit having an AND circuit configuration.