JP2000217115A - Image coder, its method, image decoder, its method and providing medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To retrieve an optimum class code by applying nonlinear ADRC processing to a pixel value of a class tap by extending the retrieval range of the class code. SOLUTION: A pixel value update circuit 6 uses an original image and a prediction coefficient to update values of pixels of a high-order layer image. A prediction coefficient update circuit 7 uses pixel values of the high-order layer image and pixel values of the original image, to generate a prediction coefficient, which is outputted to prediction coefficient memory 4. A class code selection circuit 8 causes the classification information of pixels of the high-order layer image to change so as to retrieve an optimum class code for a target pixel and to output classification information corresponding to the optimum class code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding apparatus and method, an image decoding apparatus and method, and a providing medium, and more particularly, to image encoding for generating a reduced image capable of generating an image almost identical to an original image. The present invention relates to an apparatus and a method, an image decoding apparatus and a method, and a providing medium.

[0002]

2. Description of the Related Art An upper-layer image composed of a smaller number of pixels than the number of pixels constituting an original image is generated, and a lower-layer image substantially identical to the original image is generated from the upper-layer image (the original image is generated by Restoring) technology has been proposed by the present applicant.

[0003] This proposal is called integrated compression using class classification adaptive processing, and in this integrated compression, the pixel value of a lower hierarchical image is determined by the pixel value of a prediction tap centered on a target pixel of an upper hierarchical image. And a linear primary combination of prediction coefficients corresponding to the class code into which the pixel of interest is classified. Note that the class code of the target pixel is determined by adding ADRC (Adaptive Dynamic Range Coding) to the pixel value of the class tap composed of the target pixel and its neighboring pixels.
The processing is performed and the decision is made.

[0004]

By the way, in order to generate an upper layer image capable of generating a lower layer image closer to the original image, the pixel value and the class code of the upper layer image are calculated as follows.
It is necessary to search for the optimal value by changing each. However, even if the pixel value of the upper layer image is largely changed due to the fact that the class code is determined by the ADRC process, the width of the change of the class code accompanying the change is not wide. Therefore, there is a problem that the optimum class code may exist outside the variation range of the class code, that is, outside the search range.

The present invention has been made in view of such a situation, and performs a non-linear ADRC process on the pixel value of a class tap to extend a search range of a class code.
It allows you to search for the optimal class code.

[0006]

An image encoding apparatus according to claim 1, wherein n pixel values of a first image are generated using m pixel values of an original image. And a prediction coefficient generation means for generating a prediction coefficient using the pixel value of the original image and the pixel value of the first image; and storing a predetermined portion of the pixel data of the first image as a pixel value; Pixel data storage means for storing as class classification information,
A class tap extracting means for extracting a class tap corresponding to a predetermined pixel of the first image, and a class code for generating a class code by applying a non-linear ADRC process to class classification information of pixels constituting the class tap A generation unit, a prediction coefficient storage unit that stores a prediction coefficient in association with a class code, a pixel value that is a predetermined portion of pixel data of the first image, and a prediction coefficient corresponding to the class code,
A calculating means for calculating the pixel value of the second image; a comparing means for comparing the pixel value of the original image with the pixel value of the second image; and a pixel data storing means for storing the pixel data corresponding to the comparison result of the comparing means. A pixel value updating unit for updating the pixel value being updated, a prediction coefficient updating unit for updating the prediction coefficient stored in the prediction coefficient storage unit, and a comparison result of the comparison unit. Correspondingly, a classification information updating means for updating the classification information stored in the pixel data storage means is provided.

According to a third aspect of the present invention, there is provided an image coding method, comprising: a pixel value generating step of generating n pixel values of a first image using m pixel values of an original image; A predictive coefficient generating step of generating a predictive coefficient using the value and the pixel value of the first image, storing a predetermined portion of the pixel data of the first image as a pixel value, and using the other portion as information for class classification Storing pixel data to be stored;
A class tap extracting step of extracting a class tap corresponding to a predetermined pixel of the image of the image, and a class code generating step of applying a non-linear ADRC process to a class classification information of a pixel constituting the class tap to generate a class code A prediction coefficient storing step of storing a prediction coefficient in association with a class code; a pixel value which is a predetermined part of pixel data of the first image; and a second prediction coefficient using the prediction coefficient corresponding to the class code. A calculating step of calculating the pixel value of the image, a comparing step of comparing the pixel value of the original image with the pixel value of the second image, and a pixel value stored in the pixel data storing step corresponding to the comparison result of the comparing step. A pixel value updating step of updating the prediction coefficient, and a prediction coefficient updating step of updating the prediction coefficient stored in the prediction coefficient storage step in accordance with the comparison result of the comparison step And a class classification information updating step of updating the class classification information stored in the pixel data storage step in accordance with the comparison result of the comparison step.

[0008] According to a fourth aspect of the present invention, there is provided a recording medium, comprising:
A pixel value generating step of generating n pixel values of a first image using the pixel values of the first image;
A prediction coefficient generation step of generating prediction coefficients using pixel values of the image of the image data, and pixel data for storing a predetermined portion of the pixel data of the first image as a pixel value and storing the other portion as information for class classification A storage step; a class tap extraction step of extracting a class tap corresponding to a predetermined pixel of the first image; and a non-linear ADRC process to apply a class code to the class classification information of the pixels constituting the class tap. A class code generating step to be generated, a prediction coefficient storage step of storing a prediction coefficient in association with the class code, a pixel value being a predetermined portion of pixel data of the first image, and a prediction coefficient corresponding to the class code. A calculating step of calculating a pixel value of the second image using the calculating step, a comparing step of comparing the pixel value of the original image with the pixel value of the second image, and a comparing step A pixel value update step of updating the pixel value stored in the pixel data storage step in accordance with the comparison result of the above, and a prediction coefficient updating the prediction coefficient stored in the prediction coefficient storage step in accordance with the comparison result of the comparison step A computer-readable program that causes the image encoding apparatus to execute a process including an updating step and a class classification information updating step of updating the class classification information stored in the pixel data storage step in accordance with the comparison result of the comparison step. A unique program is provided.

According to a fifth aspect of the present invention, there is provided an image decoding apparatus, comprising: designating means for designating a predetermined pixel of a first image as a pixel of interest; extracting a class tap corresponding to the pixel of interest; Class tap extracting means for reading class classification information from a predetermined portion of the pixel data, and class code generating means for generating a class code by applying a non-linear ADRC process to the class classification information read by the class tap extracting means, A prediction tap extracting unit that determines a prediction tap corresponding to the pixel of interest and extracts a pixel value from a predetermined portion of pixel data of a pixel included in the prediction tap; a pixel value extracted by the prediction tap extraction unit; Restoring means for restoring pixel values of an original image using corresponding prediction coefficients.

According to a sixth aspect of the present invention, in the image decoding method, a specifying step of specifying a predetermined pixel of the first image as a pixel of interest, extracting a class tap corresponding to the pixel of interest, and A class tap extraction step of reading class classification information from a predetermined portion of pixel data, and a class code generation step of generating a class code by applying a nonlinear ADRC process to the class classification information read in the class tap extraction step, A prediction tap extraction step of determining a prediction tap corresponding to the pixel of interest and extracting a pixel value from a predetermined portion of pixel data of a pixel included in the prediction tap; a pixel value extracted in the prediction tap extraction step; Restoring the pixel values of the original image using the corresponding prediction coefficients.

According to a seventh aspect of the present invention, in the providing medium, a specifying step of specifying a predetermined pixel of the first image as a pixel of interest, extracting a class tap corresponding to the pixel of interest, and selecting a pixel included in the class tap A class tap extraction step of reading class classification information from a predetermined portion of data, and a class code generation step of applying a nonlinear ADRC process to the class classification information read in the class tap extraction step to generate a class code. A prediction tap extraction step of determining a prediction tap corresponding to the pixel and extracting a pixel value from a predetermined portion of the pixel data of the pixel included in the prediction tap; and a pixel code extracted in the prediction tap extraction step and corresponding to the class code. And a restoring step of restoring the pixel value of the original image using the prediction coefficient to be executed. A computer-readable program is provided.

[0012] In the image encoding apparatus according to the first aspect, the image encoding method according to the third aspect, and the providing medium according to the fourth aspect, the pixel value of the original image is calculated using m pixel values. N pixel values of the first image are generated, a prediction coefficient is generated using the pixel values of the original image and the pixel values of the first image, and a predetermined portion of the pixel data of the first image is defined as a pixel value. And the other parts are stored as class classification information. Further, a class tap corresponding to a predetermined pixel of the first image is extracted, a class code is generated by applying a non-linear ADRC process to the class classification information of the pixels constituting the class tap, and the prediction coefficient is The pixel value of the second image is calculated using the pixel value that is stored in association with the code and is a predetermined portion of the pixel data of the first image and the prediction coefficient corresponding to the class code. Further, the pixel value of the original image is compared with the pixel value of the second image, and the stored pixel value, prediction coefficient, and class classification information are updated in accordance with the comparison result.

[0013] The image decoding apparatus according to claim 5, and claim 6.
And the providing medium according to claim 7, wherein a predetermined pixel of the first image is designated as a target pixel, a class tap corresponding to the target pixel is extracted and included in the class tap. Class classification information is read from a predetermined portion of the pixel data of the pixel to be processed, and a class code is generated by applying a non-linear ADRC process to the class classification information. Further, a prediction tap corresponding to the pixel of interest is determined, a pixel value is extracted from a predetermined portion of pixel data of a pixel included in the prediction tap, and the extracted pixel value and a prediction coefficient corresponding to a class code are used. The pixel values of the original image are restored.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A configuration example of an encoder to which the present invention is applied will be described with reference to FIG. Note that the original image input to the encoder 1 has an 8-bit pixel value per pixel, and the upper layer image generated by the encoder 1 also has an 8-bit information amount (pixel data) per pixel. And

In the following, a pixel of interest is a pixel specified to specify a position without updating the pixel value, and a pixel of interest is specified to specify a position.
In addition, it is assumed that the pixel value is updated.

The original image input to the encoder 1 is
Preprocessing circuit 2, pixel value updating circuit 6, prediction coefficient updating circuit 7, class code selecting circuit 8, and convergence determining circuit 10
Supplied to The preprocessing circuit 2 generates an initial upper layer image by using the supplied original image, and generates an upper layer image memory 3.
And an initial prediction coefficient table is generated and stored in the prediction coefficient memory 4.

The upper layer image memory 3 outputs the stored upper layer image to the selector 5. The upper layer image memory 3 updates the 4 bits on the MSB (Most Significant Bit) side of the upper layer image stored up to that point using the pixel value (4 bits) input from the pixel value updating circuit 6. The four bits on the LSB (Least Significant Bit) side of the upper layer image stored so far are updated using the class classification information (4 bits) input from the class code selection circuit 8.

The prediction coefficient memory 4 stores the prediction coefficients in association with the class codes, and stores the stored prediction coefficients in a pixel value updating circuit 6, a class code selection circuit 8, a decoding circuit 9, and a convergence determination circuit. Supply 10 Also,
The prediction coefficient memory 4 updates the stored prediction coefficients by using the prediction coefficients input from the prediction coefficient update circuit 7.

The selector 5 operates in accordance with the control signal input from the update counter 11 to store the upper hierarchical image memory 3.
Are sequentially output to the pixel value update circuit 6, the prediction coefficient update circuit 7, and the class code selection circuit 8 in addition to the decode circuit 9 and the convergence determination circuit 10.

The pixel value updating circuit 6 updates the pixel value (4 bits on the MSB side of the pixel data (8 bits)) of the pixel of the upper hierarchical image input from the selector 5 using the original image and the prediction coefficient. , And output to the upper layer image. The prediction coefficient updating circuit 7 outputs the upper-layer image input from the selector 5,
Further, a prediction coefficient is generated using the original image and output to the prediction coefficient memory 4.

The class code selection circuit 8 changes the class classification information (the 4 bits on the LSB side of the pixel data (8 bits)) of the predetermined target pixel of the upper layer image input from the selector 5 to thereby change the target pixel. The optimum class code of the pixel is searched, and class classification information (4 bits) corresponding to the optimum class code is output to the upper layer image memory 3.

The decoding circuit 9 generates a lower hierarchical image using the upper hierarchical image input from the selector 5 and the prediction coefficients stored in the prediction coefficient memory 4, and outputs it to the convergence determining circuit 10.

The convergence judging circuit 10 calculates the S / N of the original image of the lower hierarchical image input from the decoding circuit 9, further calculates the increase, and judges that the increase of the S / N has converged. In this case, the upper layer image input from the selector 5 and the prediction coefficient table input from the prediction coefficient memory 4 are output to the subsequent stage. The convergence determination circuit 10
Outputs the higher-layer image input from the selector 5 and the prediction coefficient table input from the prediction coefficient memory 4 to the subsequent stage even when the control signal is input from the update counter 11.

The update number counter 11 is provided for the convergence judgment circuit 1.
0, the pixel value update circuit 6, the prediction coefficient update circuit 7, or the class code selection circuit 8 outputs a control signal to the selector 5 and outputs the control signal in response to the end of each process. The number of times is counted, and when the counted value reaches a predetermined number, a control signal is output to the convergence determination circuit 10.

Next, the operation of the encoder 1 will be described with reference to FIG.
This will be described with reference to the flowchart of FIG. This encoding process is started when the original image is input to the encoder 1. In step S1, the preprocessing circuit 2 performs preprocessing using the input original image.

This pre-processing comprises steps S11 and S12 as shown in FIG. The initial upper layer image generation process in step S11 will be described with reference to the flowchart in FIG. In step S21, the preprocessing circuit 2 converts the input original image into a predetermined size (for example, FIG.
(3 × 3 pixels) as shown in FIG.

In step S22, the preprocessing circuit 2
Averages the pixel values of a plurality of (9 in this case) pixels included in the block divided in step S21, and uses the average value as the pixel value of one pixel of the initial upper layer image.
As shown in FIG. 6, the upper layer image data (8 bits)
Record in the 4 bits on the MSB side.

However, since the average value of the original image is 8 bits, that is, 256 gradations, in order to express this with 4 bits (16 gradations), the average value is simply 8 bits indicating the average value.
Instead of using the 4 bits on the MSB side, the average value is divided by 16, and a value obtained by adding a predetermined offset value (for example, 7 or 8) is converted into 4 bits.

The pre-processing circuit 2 records an arbitrary value (for example, a random number) as four bits on the LSB side of the pixel data (8 bits) of the upper layer image as class classification information.

It should be noted that the method of determining the pixel value of the initial upper hierarchical image is not a method based on averaging as described above.
A method using thinning or a Gaussian filter may be used.

Referring back to FIG. After the processing in step S11, an initial prediction coefficient generation processing is executed in step S12. This processing will be described with reference to the flowchart in FIG. In step S31, the preprocessing circuit 2 determines one pixel of the initial upper layer image generated in step S11 in FIG. 3 as a pixel of interest.

In step S32, the preprocessing circuit 2
Extracts class classification information (4 bits each) of a class tap (for example, a pixel of interest and a total of five pixels located above, below, left, and right thereof) corresponding to the pixel of interest.

In step S33, the preprocessing circuit 2
Performs a non-linear 1-bit ADRC process on the five pieces of class classification information (each 4 bits) extracted in step S32, converts each into 1 bit, and converts them into, for example, a predetermined value corresponding to a pixel position. By arranging in the order of 5
Get the class code of a bit.

Here, the non-linear ADRC processing will be described. In the non-linear ADRC processing, a non-linear parameter is assigned to the extracted five-pixel class classification information (each 4 bits) (hereinafter, a non-linear parameter Y is allocated to the class classification information X). Is described as (X; Y)).

That is, for example, (0000; -60),
(0001; -24), (0010; -15, (0011; -8),
(0100; -4), (0101; -2), (0110; -1),
(0111; 0), (1000; 1), (1001; 2), (1010;
4), (1011; 8), (1100; 15), (1101; 2)
4), (1110; 60), (1111; 80), parameters at different intervals are assigned to equally spaced class classification information.

The dynamic range of the five parameters assigned to the five pieces of classification information is DR,
When the value of the parameter is L, the requantization code is Q, and the bit allocation of the requantization code Q is k (k = 1 in this case), the following equation is calculated. Q = {(L−Min) × 2 ^k / DR} DR = Max−Min + 1

Note that, here, Δ means truncation processing. Max and Min represent the maximum and minimum values of the five parameters, respectively. By this nonlinear ADRC processing, five parameters L1 to L5 are each set to 1
It is converted into bit (k = 1) requantization codes Q1 to Q5. By arranging the requantized codes Q1 to Q5 in a predetermined order, a 5-bit class code is generated. Hereinafter, such processing is referred to as non-linear 1-bit ADRC processing.

Returning to the description of FIG. In step S34, the preprocessing circuit 2 extracts a pixel value of a prediction tap of a predetermined size (for example, 5 × 5 pixels) centering on the target pixel. In step S35, the preprocessing circuit 2 generates a normal equation including a known original image and pixel values of prediction taps, and unknown prediction coefficients.

In step S36, the pre-processing circuit 36
Determines whether all the pixels of the initial upper layer image have been set as the target pixels, and repeats the processing of steps S31 to S36 until it determines that all the pixels have been set as the target pixels. If it is determined in step S36 that all the pixels have been set as the target pixel, the process proceeds to step S37.

In step S37, the pre-processing circuit 37
Generates the normal equation generated in step S35 for each 5-bit class code, and applies the least squares method to the equation to obtain 32 types of prediction coefficients.

In step S38, the preprocessing circuit 2
Outputs 32 types of prediction coefficients corresponding to a 5-bit class code to the prediction coefficient memory 4. Further, the preprocessing circuit 2 outputs to the upper layer image memory 3 an initial upper layer image in which 4 bits on the MSB side are pixel values and 4 bits on the LSB side are pixel data that is information for class classification.

As a method of generating an initial prediction coefficient other than the above-described processing, a random number may be associated with a class code represented by 5 bits.

Returning to FIG. After the pre-processing of step S1 is performed as described above, a decoding process is performed in step S2. That is, the upper layer image input from the upper layer image memory 3 to the selector 5 is supplied to the decoding circuit 9 in accordance with the control signal from the update counter 11. The decoding circuit 9 uses the upper layer image (in this case, the initial upper layer image) input from the selector 5 and the prediction coefficient table (in this case, the initial prediction coefficient table) supplied from the prediction coefficient memory 4. A lower layer image is generated and output to the convergence determination circuit 10. As shown in FIG. 5, the pixels of the lower hierarchical image are as follows.
For one pixel of interest in the upper layer image, 3 × 3 pixels (pixels a to i) centering on pixel i of the lower layer image at the corresponding position are generated. The configuration and operation of the decoding circuit 9 will be described later with reference to FIGS.

In step S3, the convergence determination circuit 10
Calculates the S / N of the lower hierarchical image input from the decoding circuit 9 with respect to the original image, further calculates the increase amount, and determines whether or not the increase amount of the S / N has converged. S / N
Is determined to have converged, or when the control signal from the update counter 11 has been received,
Proceed to step S7. If it is determined that the S / N increase amount has not converged and the control signal from the update counter 11 has not been received, the process proceeds to step S4.

In this case, since the convergence determination process is performed on the lower-layer image decoded for the first time, the amount of increase in S / N is not calculated. Since the control signal from the update counter 11 has not been received, the process proceeds to step S4.

In response to the completion of the determination processing of the convergence determination circuit 10, the update number counter 11 outputs a control signal to the selector 5.

In step S 4, the upper layer image input from the upper layer image memory 3 to the selector 5 is supplied to the pixel value updating circuit 6 in accordance with the control signal from the update counter 11. The pixel value updating circuit 6 updates the pixel value (4 bits on the MSB side of the pixel data) of the input upper-layer image.

Before describing the pixel value updating process, an example of the configuration of the pixel value updating circuit 6 will be described with reference to FIGS. The upper layer image input from the selector 5 is stored in the upper layer image memory 21 in the pixel value updating circuit 6. The upper layer image memory 21
The stored upper layer image is supplied to the optimum pixel value determination circuit 22. The upper-layer image memory 21 stores the optimized pixel value (4 bits) from the optimum pixel value determination circuit 22.
Is used to update the pixel value (4 bits on the MSB side of the pixel data) of the upper layer image that has been stored so far. The upper layer image in which the pixel values of all the pixels are optimized is output to the upper layer image memory 3 via the switch 24.

The original image and the prediction coefficient table from the prediction coefficient memory 4 are also supplied to the optimum pixel value determination circuit 22. The optimum pixel value determination circuit 22 includes a target pixel determination circuit 23
Optimizes the pixel value of the target pixel designated by, and outputs it to the upper layer image memory 21. The attention pixel determination circuit 23
The pixels of the upper layer image are sequentially determined as the pixel of interest, and the position information is output to the optimum pixel value determination circuit 22. Also,
The target pixel determination circuit 23 outputs a control signal for turning on the switch 24 after determining all pixels of the upper layer image as target pixels.

FIG. 9 shows a detailed configuration example of the optimum pixel value determination circuit 22. In the optimum pixel value determination circuit 22, the pixel values of the pixels other than the pixel of interest are fixed,
The pixel value of the target pixel is optimized.

The pixel-of-interest determination circuit 31 determines the range affected by the change in the pixel value of the pixel of interest determined by the pixel-of-interest determination circuit 23 (the center of the prediction tap including the pixel of interest). A range including a pixel, hereinafter referred to as an affected range) is set, and the pixels of the upper hierarchical image existing within the affected range are sequentially determined as a pixel of interest, and the position information is determined by the class tap extraction circuit 32. And a prediction tap extraction circuit 34. In addition, the target pixel determination circuit 31 outputs a control signal for turning on the switch 37 after determining all pixels within the influence range as target pixels.

The class tap extracting circuit 32 extracts the class tap information (4 bits on the LSB side of the pixel data) of the class tap corresponding to the target pixel (the target pixel and the pixels located above, below, left and right of the target pixel). Output to the circuit 33.

The class classification circuit 33 applies a non-linear 1-bit ADRC process to the classification information for five pixels input from the class tap extraction circuit 32 to generate a 5-bit class code. 35.
The prediction tap extraction circuit 34 extracts the pixel value (4 bits on the MSB side of the pixel data) of the prediction tap (5 × 5 pixels centered on the pixel of interest) corresponding to the pixel of interest and outputs it to the error function generation circuit 35 I do.

The error function generation circuit 35 generates an error function corresponding to the target pixel using the pixel value of the prediction tap and the prediction coefficient corresponding to the class code, and outputs the error function to the influence error function register 36. The influence error function register 36 adds the error functions corresponding to all the pixels of interest to generate an influence error function, and outputs the result to the pixel-of-interest calculation circuit 38 via the switch 37.

The target pixel value calculation circuit 38 includes a switch 37
The pixel value of the pixel of interest is calculated by solving the influence error function input via. The details of the error function and the influence error function will be described later.

Next, the operation of the pixel value updating circuit 6 will be described.
This will be described with reference to the flowchart of FIG. This pixel value updating process is started when the upper layer image input from the selector 5 is stored in the upper layer image memory 21 of the pixel value updating circuit 6.

In step S51, the pixel-of-interest determination circuit 23 determines the pixel of interest in the upper hierarchical image, as shown in FIG.
Output to 2. In step S52, the target pixel determination circuit 31 of the optimum pixel value determination circuit 22 determines a range (influence range) affected when the pixel value of the target pixel is changed. For example, when the size of the prediction tap is 5 × 5 pixels, a range including 5 × 5 pixels centered on the pixel of interest as shown in FIG. 11B (a lower layer image generated from the upper layer image) , The affected area is 15 × 15 pixels as shown in FIG.

In step S53, the pixel-of-interest determination circuit 31 determines one pixel of the pixels included in the affected area as the pixel of interest, and uses the position information of the class tap extraction circuit 32 and the prediction tap extraction circuit 34. Output to
The class tap extraction circuit 32 extracts the information for class classification of the pixels constituting the class tap corresponding to the pixel of interest and outputs the information to the class classification circuit 33. Predictive tap extraction circuit 3
Reference numeral 3 extracts a pixel value of a pixel forming a prediction tap corresponding to the target pixel and outputs the extracted pixel value to the error function generation circuit 34.

In step S54, the class classification circuit 33 applies a non-linear 1-bit ADRC process to the classification information for five pixels input from the class tap extraction circuit 32 to generate a 5-bit class code. Output to the error function generation circuit 35. The prediction tap extraction circuit 34 extracts the pixel value of the prediction tap corresponding to the pixel of interest and outputs it to the error function generation circuit 35.

In step S55, the error function generation circuit 35 generates an error function corresponding to the pixel of interest using the pixel value of the prediction tap and the prediction coefficient corresponding to the class code, and outputs the error function to the influence error function register 36. .

Here, the error function will be described. Nine pixel values (prediction values) y _i ′ (i = 1 to 9) of 3 × 3 pixels of the lower hierarchical image corresponding to one target pixel of the upper hierarchical image are expressed by the following equation (1). As described above, it can be represented by a linear linear combination of the pixel value x of the upper hierarchical image and the prediction coefficient w. _{y i '= w i1 x 1} + w i2 x 2 + ··· + w ik x k + ··· + w i25 x 25 ... (1)

Here, w _{i1 to} w _i25 are prediction coefficients corresponding to the class code of the pixel of _interest , and x _{1 to} x i
Reference numeral ₂₅ denotes a pixel value of a pixel included in a prediction tap centered on the target pixel. In particular, the pixel value w _ik and the prediction coefficient x _k are
The pixel value of the target pixel and the corresponding prediction coefficient.

[0063] If the pixel values of the lower layer image (predicted value) pixel values of the corresponding original image y _i '(true value) y _i, the error function E, the error e _i to the true value of the predicted value The sum of the squares can be expressed as in the following equation (2). Error function E = Σe _i ² = Σ (y _i −y _i ′) ² = Σ ((y _i -Σw _ij x _j ) −w _ik x _k ) ² (2)

Where Σ at the left end of the right side of equation (2) is i =
The sum of 1 to 9 is shown, and the Σ in parenthesis indicates the sum of j = 1 to 25 (excluding j = k).

In equation (2), the pixel value x _k of the target pixel is a value to be optimized, that is, a variable, and the true value y _i , prediction coefficients w _ij , w _ik , and pixel value x _j are known. Is the value of Therefore, Expression (2) can be expressed as a quadratic expression of the _target pixel value xk, as shown in Expression (3). Error function E = a · x _k ² + b · x _k + c (3)

Here, a, b, and c are as follows. a = w _k ² b = −2w _k (y _i −Σw _ij x _j ) c = (y _i −Σw _ij x _j ) ²

Returning to FIG. In step S56,
The pixel-of-interest determination circuit 31 determines whether or not all the pixels within the affected area have been determined as the pixel of interest. If it is determined that all the pixels within the affected area have not been determined as the pixel of interest, the process proceeds to step S53. Return, and the subsequent processing is repeated.

Thereafter, when it is determined in step S56 that all the pixels within the influence range have been determined as the target pixel, the process proceeds to step S57. In step S57,
The target pixel determination circuit 31 outputs a control signal for turning on the switch 37. The influence error function register 36 adds the error functions E (Equation (3)) corresponding to all the pixels of interest within the influence range, and obtains an influence error function E _check = ΣE
Is generated, and the target pixel value calculation circuit 3
8 is output. Incidentally, since it is the sum of the error function E is a quadratic equation of the pixel value x _k of the pixel of interest, as shown in the following equation (4), the impact error function E _{chec k} pixel values x _k of the pixel of interest 2 It becomes the following function. Influence error function E _check = a ′ · x _k ² + b ′ · x _k + c ′ (4)

In step S58, the target pixel value calculation circuit 38 calculates a pixel value x _k = −b ′ / 2a ′ that minimizes the influence error function E _check as a quadratic function as an optimum pixel value of the target pixel. Then, the image is output to the upper layer image memory 21. The upper layer image memory 21 updates the stored pixel value of the target pixel using the input optimal pixel value.

In step S59, the pixel-of-interest determination circuit 23 determines whether or not all the pixels of the upper hierarchical image have been determined as the pixel of interest. If it is determined that all the pixels have not been determined as the pixel of interest, Returning to step S51, the subsequent processing is repeated.

Thereafter, if it is determined in step S59 that all the pixels of the upper hierarchical image have been determined as the target pixel, the target pixel determination circuit 23 outputs a control signal for turning on the switch 24. The switch 24 is turned on in response to this control signal, and the upper layer image with the optimized pixel values stored in the upper layer image memory 21 is output to the subsequent upper layer image memory 3. The update number counter 11 outputs a control signal to the selector 5 in response to the end of the processing of the pixel value updating circuit 6.

Returning to FIG. After the pixel value updating process is performed in step S4 as described above, in step S5, the upper layer image input to the selector 5 from the upper layer image memory 3 corresponds to the control signal from the update number counter 11. Then, it is supplied to the prediction coefficient updating circuit 7. The prediction coefficient update circuit 7 updates the prediction coefficient table stored in the prediction coefficient memory 4 using the input upper layer image and original image.

Before describing the prediction coefficient updating process, a detailed configuration example of the prediction coefficient updating circuit 7 will be described with reference to FIG.
This will be described with reference to FIG. The upper layer image input from the selector 5 is supplied to the prediction tap extracting circuit 42 and the class tap extracting circuit 43 in the prediction coefficient updating circuit 7. The pixel-of-interest determination circuit 41 sequentially determines the pixels of the upper layer image as pixels of interest, and outputs the position information to the prediction tap extraction circuit 42 and the class tap extraction circuit 43.

The prediction tap extracting circuit 42 calculates a prediction tap corresponding to the pixel of interest (5 × 5 pixels centered on the pixel of interest).
(The 4 bits on the MSB side of the pixel data) are extracted and output to the normal equation generation circuit 46. The class tap extraction circuit 43 extracts class classification information (LSB side 4 bits of pixel data) of a class tap (pixel of interest and pixels located above, below, left, and right) corresponding to the pixel of interest, and outputs the information to the class classification circuit 44. Output. The class classification circuit 44 generates a 5-bit class code by applying a non-linear 1-bit ADRC process to the 5-pixel class classification information input from the class tap extraction circuit 43, and outputs the 5-bit class code to the normal equation generation circuit 46. I do.

The teacher data extracting circuit 45 extracts teacher data (true values corresponding to the pixel values of the lower hierarchical image to be generated) from the original image and outputs the extracted teacher data to the normal equation generating circuit 46.
The normal equation generation circuit 46 outputs, for each class code of the pixel of interest, the known teacher data and the pixel value of the prediction tap,
In addition, a normal equation including unknown prediction coefficients is generated and output to the prediction coefficient calculation circuit 47.

The prediction coefficient calculation circuit 47 calculates the 32 types of prediction coefficients (prediction coefficient tables) corresponding to the 5-bit class codes by applying the least square method to the input normal equation, and stores the prediction coefficients in the prediction coefficient memory 4. Output.

Next, the operation of the prediction coefficient updating circuit 7 will be described with reference to the flowchart of FIG. The prediction coefficient update processing is started when an upper layer image is input from the selector 5 to the prediction coefficient update circuit 7.

In step S61, the pixel-of-interest determination circuit 41 determines one pixel of the upper hierarchical image as a pixel of interest, and outputs the position information to the prediction tap extraction circuit 42 and the class tap extraction circuit 43. The prediction tap extraction circuit 42 extracts the pixel value of the prediction tap corresponding to the pixel of interest and outputs it to the normal equation generation circuit 46. The class tap extraction circuit 43 extracts the information for class classification of the class tap corresponding to the pixel of interest and outputs the information to the class classification circuit 44.

In step S62, the class classification circuit 44 applies a non-linear 1-bit ADRC process to the classification information for five pixels input from the class tap extraction circuit 43 to generate a 5-bit class code. Output to the normal equation generation circuit 46.

In step S 63, the teacher data extraction circuit 45 extracts the pixel value of the original image as the teacher data and outputs it to the normal equation generation circuit 46. The normal equation generation circuit 46 generates a normal equation using the known teacher data and the pixel value of the prediction tap and the undetermined prediction coefficient for each class code of the pixel of interest, and outputs the normal equation to the prediction coefficient calculation circuit 47. I do.

In step S64, the pixel-of-interest determination circuit 41 determines whether or not all the pixels of the upper layer image have been set as the pixel of interest. If it is determined that not all the pixels have been set as the pixel of interest, the process returns to step S61. , And the subsequent processes are repeated. Thereafter, when it is determined in step S64 that all the pixels have been set as the target pixel, the process proceeds to step S65.

In step S65, the prediction coefficient calculation circuit 47 calculates the 32 types of prediction coefficients corresponding to the 5-bit class code by applying the least square method to the normal equation generated by the normal equation generation circuit 46 in step S63. I do. In step S66, the prediction coefficient calculation circuit 47
Outputs the obtained prediction coefficient (prediction coefficient table) to the prediction coefficient memory 4. The prediction coefficient memory 4 updates the stored prediction coefficient table by using the input prediction coefficient table. The update number counter 11 outputs a control signal to the selector 5 in response to the end of the processing of the prediction coefficient update circuit 6.

Returning to FIG. As described above, after the prediction coefficient updating process is performed in step S5, the process proceeds to step S6.
In the above, the upper layer image input from the upper layer image memory 3 to the selector 5 is supplied to the class code selection circuit 8 in accordance with the control signal from the update counter 11. The class code selection circuit 8 selects an optimum one of the 32 types of prediction coefficients stored in the prediction coefficient memory 4 for each pixel of the input upper layer image.

Before describing the class code selection processing, a detailed configuration example of the class code selection circuit 8 will be described with reference to FIG. Target pixel determination circuit 51
Determines the pixels of the upper layer image sequentially as the pixel of interest,
The position information is output to the prediction tap extraction circuit 52 and the class tap extraction circuit 53. Prediction tap extraction circuit 52
Is a prediction tap corresponding to the pixel of interest (5 ×
The pixel value (five pixels) (4 bits on the MSB side of the pixel data) is extracted and output to the mapping circuit 55.

The class tap extraction circuit 53 extracts the class tap information (the four bits on the LSB side of the pixel data) of the class tap (the target pixel and the pixels located above, below, left and right) corresponding to the target pixel. The classification information of the pixel of interest in the classification information for the five pixels is replaced with the value of the counter supplied from the classification counter 60 and output to the classification circuit 54. Classification circuit 5
4 generates a 5-bit class code by applying the non-linear 1-bit ADRC process to the 5-pixel class classification information input from the class tap extraction circuit 53 and outputs the 5-bit class code to the mapping circuit 55.

The mapping circuit 55 includes a classifying circuit 5
The prediction coefficient corresponding to the class code input from 4 is
The linear coefficient is read out from the prediction coefficient memory 4 to calculate the linear combination of the obtained prediction coefficient and the pixel value of the prediction tap. .

The error calculation circuit 56 includes a mapping circuit 55
, And the error (S / N) between the predicted value input from and the corresponding pixel value (true value) of the original image is calculated and output to the comparator 57 and the switch 58. The comparator 57 compares the error input from the error calculation circuit 56 with the error stored in the minimum error register 59, and the error input from the error calculation circuit 56 is smaller (the S / N is larger). ), A control signal for turning on the switches 58 and 61 is output. Further, the comparator 57 outputs a signal for incrementing the class classification information counter 60 after comparing the error regardless of the result of the comparison. The minimum error register 59 updates the previously stored error using the error input via the switch 57.

The class classification information counter 60 increments the value of the 4-bit counter by one in accordance with the control signal input from the comparator 57, and outputs it to the class tap extraction circuit 53 and the switch 61. The class counter information counter 60 has a counter value of the maximum value 1111.
, A control signal for turning on the switch 63 is output, and the value of the counter is reset to the initial value 0000.

The optimum class classification information register 62 updates the class classification information stored so far by using the class classification information input via the switch 61. Therefore, the optimal class classification information register 62 holds class classification information (optimal class classification information) for generating a class code corresponding to the prediction coefficient that minimizes the error. The optimum class classification information register 62 outputs the stored optimum class classification information to the subsequent upper-layer image memory 3 via the switch 63.

Next, the operation of the class code selection circuit 8 will be described with reference to the flowchart of FIG. This class code selection processing is started when an upper layer image is input from the selector 5 to the class code selection circuit 8.

In step S 71, the pixel-of-interest determination circuit 51 determines one pixel of the upper hierarchical image as a pixel of interest, and outputs the position information to the prediction tap extraction circuit 52 and the class tap extraction circuit 53. In step S72, the prediction tap extraction circuit 52 extracts the pixel value of the prediction tap corresponding to the pixel of interest from the upper layer image input from the selector 5, and outputs the pixel value to the mapping circuit 55.

In step S 73, the class classification information counter 60 outputs the initial value 0000 of the counter to the class tap extraction circuit 53. In step S74, the class tap extraction circuit 53 extracts the class classification information of the class tap corresponding to the pixel of interest and obtains the obtained 5
The class-classifying information of the pixel of interest in the class-classifying information for the pixels is replaced with the value of the counter supplied from the class-classifying counter 60 and output to the class-classifying circuit 54. In step S75, the class classification circuit 54
A non-linear 1-bit ADRC process is applied to the 5-pixel class classification information input from the class tap extraction circuit 53 to generate a 5-bit class code, and the mapping circuit 55
Output to

In step S76, the mapping circuit 55 reads out the prediction coefficient corresponding to the class code input from the class classification circuit 54 from the prediction coefficient memory 4, and obtains the obtained prediction coefficient and the pixel of each pixel of the prediction tap. A linear primary combination with the value is calculated, and the calculation result is output to the error calculation circuit 56 as a pixel value (predicted value) of the lower hierarchical image.

In step S77, the error calculation circuit 5
6 calculates an error (S / N) between the predicted value input from the mapping circuit 53 and the corresponding pixel value (true value) of the original image, and outputs the result to the comparator 57 and the switch 58.
The comparator 57 compares the error input from the error calculation circuit 56 with the error stored in the minimum error register 59, and the error input from the error calculation circuit 56 is smaller (the S / N is larger). ), A control signal for turning on the switches 58 and 61 is output. In response to this control signal, the switch 61 is turned on, and the class classification information counter 60 is turned on.
Is transferred to the optimum class classification information register 62 via the switch 61 and stored therein. Also,
The switch 58 is turned on, and the output of the error calculation circuit 54 at that time is transferred to the minimum error register 59 and stored. The comparator 57 is provided with a class classification information counter 6.
An increment signal is output to 0.

In response to the increment signal, the class classification information counter 60 determines in step S78 whether the counter value is smaller than the maximum value 1111 and the counter value is smaller than the maximum value 1111. When it is determined in step S79, the value of the counter is incremented by 1 and output to the class tap extraction circuit 53 and the switch 61 in step S79.

Thereafter, until it is determined in step S78 that the value of the counter is not smaller than the maximum value 1111, the processing in steps S74 to S79 is repeated, and the value of the counter is not smaller than the maximum value 1111 (the value of the counter is not smaller than 1111). If the value is determined to be the maximum value 1111), step S
Go to 80.

In step S80, the class classification information counter 60 outputs a control signal for turning on the switch 63, and resets the counter value to an initial value 0000. The switch 63 is turned on in response to this control signal, and the optimal class classification information of the pixel of interest, which is held in the optimal class classification information register 62, is output to the subsequent upper-layer image memory 3. The upper-layer image memory 3 uses the input optimum class classification information,
The 4 bits on the LSB side of the pixel data of the corresponding pixel are rewritten.

In step S81, the pixel-of-interest determination circuit 51 determines whether or not all the pixels of the upper layer image have been set as the pixel of interest. If it is determined that not all the pixels have been set as the pixel of interest, the process returns to step S71. , And the subsequent processes are repeated. Thereafter, when it is determined in step S81 that all the pixels have been set as the target pixel, the process returns to step S2 in FIG.

Before describing the decoding processing in step S2 in FIG. 2, a detailed configuration example of the decoding circuit 9 will be described with reference to FIG. Target pixel determination circuit 71
Sequentially determines the pixels of the upper layer image as the pixel of interest, and outputs the position information to the class tap extraction circuit 72 and the prediction tap extraction circuit 74.

The class tap extracting circuit 72 includes a selector 5
The class classification circuit extracts the class tap information (4 bits on the LSB side of the pixel data) of the class tap (the target pixel and the pixels located above, below, left and right) corresponding to the target pixel from the input upper layer image 73. The class classification circuit 73 includes a non-linear 1-bit AD in the class classification information for five pixels input from the class tap extraction circuit 72.
A 5-bit class code is generated by applying the RC processing and output to the mapping circuit 75. Predictive tap extraction circuit 74
Is a prediction tap corresponding to the pixel of interest (5 ×
The pixel value (5 bits) (4 bits on the MSB side of the pixel data) is extracted and output to the mapping circuit 75.

The mapping circuit 75 includes a classifying circuit 7
The prediction coefficient corresponding to the class code input from 3 is
It reads out from the prediction coefficient memory 4, calculates a linear linear combination of the obtained prediction coefficient and the pixel value of the prediction tap, and outputs the calculation result to the lower layer image memory 76 as the pixel value (prediction value) of the lower layer image. I do.

The lower layer image memory 76 stores the pixel values of the lower layer image input from the mapping circuit 75,
The convergence determination circuit 1 at the subsequent stage stores the stored pixel values in frame units.
Output to 0.

Next, the operation of the decoding circuit 9 will be described with reference to the flowchart of FIG. This decoding process is started when an upper layer image is input from the selector 5 to the decoding circuit 9.

In step S91, the pixel of interest determination circuit 71 determines one pixel of the upper hierarchical image as a pixel of interest, and outputs the position information to the class tap extraction circuit 72 and the prediction tap extraction circuit 74. The class tap extracting circuit 72 extracts the class tap information for the class tap corresponding to the pixel of interest from the upper layer image input from the selector 5 and outputs the information to the class sorting circuit 73. The prediction tap extraction circuit 74 extracts the pixel value of the prediction tap corresponding to the pixel of interest from the upper layer image input from the selector 5 and outputs the pixel value to the mapping circuit 75.

In step S92, the class classification circuit 73 applies a non-linear 1-bit ADRC process to the classification information for five pixels input from the class tap extraction circuit 72 to generate a 5-bit class code. Output to the mapping circuit 75.

In step S93, the mapping circuit 75 reads out the prediction coefficient corresponding to the class code input from the class classification circuit 73 from the prediction coefficient memory 4 and calculates the difference between the obtained prediction coefficient and the pixel value of the prediction tap. The linear primary combination is calculated, and the calculation result is output to the lower layer image memory 76 as a pixel value (predicted value) of the lower layer image.

In step S94, the pixel-of-interest determination circuit 71 determines whether or not all the pixels of the upper layer image have been set as the pixel of interest. If it is determined that not all the pixels have been set as the pixel of interest, the process returns to step S91. , And the subsequent processes are repeated. Thereafter, when it is determined in step S94 that all pixels have been set as the target pixel, the process proceeds to step S95. In step S95, the lower hierarchical image memory 76 stores the stored pixel value of the lower hierarchical image
It is output to the convergence determination circuit 10 at the subsequent stage.

Returning to FIG. Again, in step S3, the convergence determination circuit 10 calculates the S / N of the lower hierarchical image and the original image input from the decoding circuit 9 and the increase thereof, and determines whether the increase of the S / N has converged. Steps S2 to S6 are repeated until it is determined that the increase in S / N has converged or a control signal from the update counter 11 is received.

Thereafter, if it is determined in step S3 that the S / N increase has converged, or if a control signal from the update counter 11 has been received, the flow proceeds to step S7. In step S7, the convergence determination circuit 10 outputs the optimal upper layer image and the prediction coefficient table to the decoder 81 (FIG. 18) via a medium (not shown).

As described above, the encoder 1 uses the MSB side 4 bits of the pixel data (8 bits) of the generated upper layer image as the pixel value and the LSB side 4 bits as the class classification information. Are not changed when optimizing the value of, and each can be optimized independently.

FIG. 18 shows an example of the configuration of a decoder for restoring an original image from an upper layer image generated by the encoder 1. In the decoder 81, the upper layer image generated by the encoder 1 is supplied to the class tap extraction circuit 83 and the prediction tap extraction circuit 85, and the prediction coefficient table is supplied to the mapping circuit 86.

The pixel-of-interest determination circuit 82 sequentially determines the pixels of the upper hierarchical image as the pixel of interest, and outputs the position information to the class tap extraction circuit 83 and the prediction tap extraction circuit 85. The class tap extracting circuit 83 uses the upper layer image generated by the encoder 1 to classify information of the class tap (the target pixel and the pixels located above, below, left and right thereof) corresponding to the target pixel (the LSB side of the pixel data). Bit) is extracted and output to the class classification circuit 84. The class classification circuit 84 receives the input 5 from the class tap extraction circuit 83.
A non-linear 1-bit ADRC process is applied to the pixel class classification information to generate a 5-bit class code, which is output to the mapping circuit 86. The prediction tap extracting circuit 85 calculates the pixel value (4 bits on the MSB side of the pixel data) of the prediction tap (5 × 5 pixels centered on the pixel of interest) corresponding to the pixel of interest from the upper layer image generated by the encoder 1 Is extracted and output to the mapping circuit 86.

The mapping circuit 86 includes a classifying circuit 8
The prediction coefficient corresponding to the class code input from 4 is
It reads from the prediction coefficient table generated by the encoder 1, calculates a linear linear combination of the obtained prediction coefficient and the pixel value of the prediction tap, and outputs the calculation result to the image memory 87 as a restored value of the pixel of the original image. I do.

The image memory 87 stores the restored values of the pixels of the original image input from the mapping circuit 86, and outputs the stored restored values to, for example, a monitor (not shown) in frame units.

Next, the operation of the decoder 81 will be described with reference to FIG.
This will be described with reference to the flowchart of FIG. The decoding process is performed on the sequentially input upper layer image after the prediction coefficient table from the encoder 1 is supplied to the mapping circuit 86.

In step S 101, the pixel-of-interest determination circuit 82 determines one pixel of the upper layer image as a pixel of interest, and outputs the position information to the class tap extraction circuit 83 and the prediction tap extraction circuit 85. The class tap extracting circuit 83 extracts information for class classification of the class tap corresponding to the pixel of interest from the upper layer image generated by the encoder 1, and outputs the information to the class classification circuit 84. The prediction tap extraction circuit 85 extracts the pixel value of the prediction tap corresponding to the pixel of interest from the upper layer image generated by the encoder 1 and outputs the pixel value to the mapping circuit 86.

In step S 102, the class classification circuit 84 sets the 5 input from the class tap extraction circuit 83.
A non-linear 1-bit ADRC process is applied to the pixel class classification information to generate a 5-bit class code, which is output to the mapping circuit 86.

In step S103, the mapping circuit 86 reads the prediction coefficient corresponding to the class code input from the class classification circuit 84 from the prediction coefficient table generated by the encoder 1, and obtains the obtained prediction coefficient and prediction tap. , And outputs the calculation result to the image memory 87 as a restored value of the pixel of the original image.

In step S104, the pixel-of-interest determination circuit 82 determines whether or not all the pixels of the upper layer image have been set as the pixel of interest. If it is determined that not all the pixels have been set as the pixel of interest, the process returns to step S101. , And the subsequent processes are repeated. Thereafter, when it is determined in step S104 that all the pixels have been set as the target pixel, the process proceeds to step S105. In step S105, the restored original image stored in the image memory 87 is output to a monitor (not shown).

Next, the effect of the nonlinear ADRC processing on the conventional (non-linear) ADRC processing will be described with reference to FIG. In the conventional ADRC processing, for example, processing is performed on equally spaced values such as pixel values. Therefore, when the pixel value of one of the pixels included in the class tap is slightly changed, the corresponding fluctuation range of the class code is narrow, for example, as shown in a range B in FIG. In contrast, in the nonlinear ADRC processing of the present invention,
ADRC processing is performed for parameters with different intervals. Therefore, when the pixel value of one of the pixels included in the class tap is slightly changed, the corresponding variation range of the class code is smaller than the range B as shown in the range A in FIG. Become wider. Therefore, nonlinear AD
According to the RC processing, it is possible to search for a truly optimal class code a, instead of the class code b that was considered optimal in the range B.

In the present embodiment, the nonlinear
Although the bit allocation k of the requantization code Q in the ADRC process is 1 bit, the bit allocation k is not limited to 1 bit.

In this embodiment, the pixel data is 8 bits, and the 4 bits on the MSB side are the pixel value, L
Although the four bits on the SB side are used as the classification information, the number of these bits may be changed.

Further, various modifications and application examples can be considered without departing from the gist of the present invention. Therefore,
The gist of the present invention is not limited to the present embodiment.

The computer program for performing each of the above processes can be provided to the user via a network medium such as the Internet or a digital satellite in addition to a medium such as an information recording medium such as a magnetic disk or a CD-ROM. it can.

[0125]

As described above, according to the image encoding apparatus of the first aspect, the image encoding method of the third aspect, and the providing medium of the fourth aspect, the first image A predetermined part of the pixel data is stored as a pixel value, and the other part is stored as class classification information. Further, a class tap corresponding to a predetermined pixel of the first image is extracted, and non-linear information is added to the class classification information of the pixels constituting the class tap.
Since the class code is generated by applying the ADRC process, it is possible to search for an optimal class code, and it is possible to generate an upper layer image that can restore the original image.

According to the image decoding apparatus of the fifth aspect, the image decoding method of the sixth aspect, and the providing medium of the seventh aspect, the predetermined value of the pixel data of the pixel included in the class tap is determined. Read the information for class classification from the part,
Since the class code is generated by applying the non-linear ADRC processing to the classification information, the original image can be restored from the upper layer image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an encoder 1 to which the present invention has been applied.

FIG. 2 is a flowchart illustrating an operation of the encoder 1 of FIG.

FIG. 3 is a flowchart illustrating an operation of a preprocessing circuit 2 of FIG. 1;

FIG. 4 is a flowchart illustrating details of step S11 in FIG. 3;

FIG. 5 is a diagram for explaining an arrangement of pixels.

FIG. 6 is a diagram for explaining pixel data.

FIG. 7 is a flowchart illustrating details of step S12 in FIG. 3;

8 is a block diagram illustrating a configuration example of a pixel value updating circuit 6 in FIG.

9 is a block diagram illustrating a configuration example of an optimum pixel value determination circuit 22 in FIG.

FIG. 10 is a flowchart illustrating an operation of the pixel value updating circuit 6 of FIG. 1;

FIG. 11 is a diagram for explaining an arrangement of pixels.

12 is a block diagram illustrating a configuration example of a prediction coefficient updating circuit 7 in FIG.

FIG. 13 is a flowchart illustrating the operation of the prediction coefficient update circuit 7 of FIG. 1;

FIG. 14 is a block diagram illustrating a configuration example of a class code selection circuit 8 of FIG. 1;

FIG. 15 is a flowchart illustrating the operation of the class code selection circuit 8 of FIG. 1;

FIG. 16 is a block diagram illustrating a configuration example of a decoding circuit 9 in FIG. 1;

FIG. 17 is a flowchart illustrating an operation of the decoding circuit 9 of FIG. 1;

FIG. 18 is a decoder 81 corresponding to the encoder 1 of FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG.

FIG. 19 is a flowchart illustrating the operation of the decoder 81 in FIG. 18;

FIG. 20 is a diagram for explaining the effect of nonlinear ADRC processing.

[Description of Signs] 1 encoder, 2 pre-processing circuit, 3 upper layer image memory, 4 prediction coefficient memory, 5 selector,
6 pixel value update circuit, 7 prediction coefficient update circuit, 8
Class code selection circuit, 9 decoding circuit, 10
Convergence determination circuit, 11 update counter, 81 decoder, 82 pixel of interest determination circuit, 83 class tap extraction circuit, 84 class classification circuit, 85 prediction tap extraction circuit, 86 mapping circuit, 87 image memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK38 LA00 MA01 MA28 MA31 MC30 MD07 RC14 SS11 TA06 TA29 TA39 TB10 TB17 TC43 TD17 UA02 UA05 UA33 5C078 BA35 BA64 CA00 DA01 DA02 DB04 DB14

Claims (7)

[Claims] 1. An image coding apparatus for converting an original image composed of a plurality of pixels into a first image composed of a smaller number of pixels, wherein the first image is converted using m pixel values of the original image. A pixel value generation unit that generates n pixel values of: a prediction coefficient generation unit that generates a prediction coefficient using a pixel value of the original image and a pixel value of the first image; A pixel data storage unit that stores a predetermined portion of the pixel data as a pixel value and stores the other portion as information for class classification; and a class tap extraction that extracts a class tap corresponding to a predetermined pixel of the first image. Means, class code generating means for applying a non-linear ADRC process to the class classification information of the pixels constituting the class tap to generate a class code, and associating the prediction coefficient with the class code Prediction coefficient storage means for storing, and calculation means for calculating a pixel value of a second image using a pixel value which is a predetermined portion of the pixel data of the first image and a prediction coefficient corresponding to the class code Comparing means for comparing the pixel value of the original image with the pixel value of the second image; and updating the pixel value stored in the pixel data storing means in accordance with the comparison result of the comparing means. A pixel value updating unit, a prediction coefficient updating unit that updates the prediction coefficient stored in the prediction coefficient storage unit in response to a comparison result of the comparison unit, and a pixel value updating unit that corresponds to a comparison result of the comparison unit. An image coding apparatus, comprising: a class classification information updating unit that updates the class classification information stored in the pixel data storage unit. 2. The image according to claim 1, wherein the class code generating means assigns a non-linear parameter to the class classification information, and generates a class code by applying ADRC processing to the parameter. Encoding device. 3. An image coding method of an image coding apparatus for converting an original image composed of a plurality of pixels into a first image composed of a smaller number of pixels, wherein m pixel values of the original image are used. A pixel value generation step of generating n pixel values of the first image; a prediction coefficient generation step of generating prediction coefficients using the pixel values of the original image and the pixel values of the first image; A pixel data storing step of storing a predetermined portion of the pixel data of the first image as a pixel value and storing the other portion as information for class classification; and a class tap corresponding to the predetermined pixel of the first image. A class tap extracting step of extracting, a class code generating step of generating a class code by applying a non-linear ADRC process to class classification information of pixels constituting the class tap, A prediction coefficient storing step of storing a coefficient in association with the class code; a pixel value that is a predetermined part of the pixel data of the first image; and a second coefficient using a prediction coefficient corresponding to the class code. A calculating step of calculating a pixel value of an image; a comparing step of comparing a pixel value of the original image with a pixel value of the second image; and, corresponding to a comparison result of the comparing step, the pixel data storing step. A pixel value update step of updating the stored pixel value; a prediction coefficient update step of updating the prediction coefficient stored in the prediction coefficient storage step in accordance with a comparison result of the comparison step; and a comparison of the comparison step. A class information update step of updating the class information stored in the pixel data storing step in response to a result. Image coding method that. 4. An image encoding apparatus for converting an original image composed of a plurality of pixels into a first image composed of a smaller number of pixels, wherein the first image is encoded using m pixel values of the original image. A pixel value generating step of generating n pixel values of: a prediction coefficient generating step of generating a prediction coefficient using a pixel value of the original image and a pixel value of the first image; A pixel data storing step of storing a predetermined portion of the pixel data as a pixel value and storing the other portion as information for class classification; and extracting a class tap corresponding to a predetermined pixel of the first image. A class code generating step of applying a non-linear ADRC process to class classification information of pixels constituting the class tap to generate a class code; A prediction coefficient storage step of storing the pixel value of the second image using a prediction value corresponding to the class code and a prediction value corresponding to the class code. A calculating step of calculating; a comparing step of comparing a pixel value of the original image with a pixel value of the second image; and the pixel value stored in the pixel data storing step corresponding to a comparison result of the comparing step. A pixel value updating step of updating the prediction coefficient, and a prediction coefficient updating step of updating the prediction coefficient stored in the prediction coefficient storage step in response to the comparison result of the comparison step. A computer that executes a process including a class classification information updating step of updating the class classification information stored in the pixel data storage step. Providing medium characterized by providing a Ri can program. 5. The original image is reconstructed by using a first image and a prediction coefficient table which are generated using m pixel values of the original image and are composed of a smaller number of n pixel values. An image decoding apparatus that specifies a predetermined pixel of the first image as a pixel of interest, extracts a class tap corresponding to the pixel of interest, and specifies a predetermined pixel data of a pixel included in the class tap. Class tap extracting means for reading class classification information from a portion; class code generating means for applying a nonlinear ADRC process to the class classification information read by the class tap extracting means to generate a class code; and A prediction tap extracting means for determining a corresponding prediction tap and extracting a pixel value from a predetermined portion of pixel data of a pixel included in the prediction tap; An image decoding apparatus, comprising: a pixel value extracted by a group extraction unit; and a restoration unit that restores a pixel value of the original image using a prediction coefficient corresponding to the class code. 6. The original image is reconstructed by using a first image and a prediction coefficient table which are generated using m pixel values of the original image and are composed of a smaller number of n pixel values. In the image decoding method of the image decoding apparatus, a designation step of designating a predetermined pixel of the first image as a pixel of interest, extracting a class tap corresponding to the pixel of interest, and selecting a pixel included in the class tap A class tap extraction step of reading class classification information from a predetermined part of data, and a class code generation step of applying a non-linear ADRC process to the class classification information read in the class tap extraction step to generate a class code, A prediction that determines a prediction tap corresponding to the pixel of interest and extracts a pixel value from a predetermined portion of pixel data of a pixel included in the prediction tap Image extraction comprising the steps of extracting a pixel value extracted in the prediction tap extraction step, and a pixel value of the original image using a prediction coefficient corresponding to the class code. Method. 7. The original image is reconstructed by using a first image and a prediction coefficient table which are generated by using m pixel values of the original image and are composed of a smaller number of n pixel values. A designating step of designating a predetermined pixel of the first image as a pixel of interest, extracting a class tap corresponding to the pixel of interest, and determining a predetermined pixel data of a pixel included in the class tap. A class tap extraction step of reading class classification information from a portion; a class code generation step of applying a non-linear ADRC process to the class classification information read in the class tap extraction step to generate a class code; A prediction tap extraction step for determining a corresponding prediction tap and extracting a pixel value from a predetermined portion of pixel data of a pixel included in the prediction tap. Computer-readable program for executing a process including: a pixel value extracted in the prediction tap extraction step; and a restoration step of restoring a pixel value of the original image using a prediction coefficient corresponding to the class code. A providing medium characterized by providing: