JP2000215192A - Chaos genrating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the chaos generating circuit which is easily LSI-implemented while having a wide dynamic range by including a linear mapping circuit which has a CMOS transistor and a load component connected in series. SOLUTION: The sources of a P channel transistor 14 and an N channel transistor 15 which are manufactured by CMOS process technology are connected to a plus power source VDD11 and a minus power source VSS 12 respectively. The gates of the transistors 14 and 15 are connected in common to form an input terminal Vi13. A load element 18 (impedance) is connected between the drains of the transistors 14 and 15 and the potential generated across the load element 18 is an output Vo. When a linear voltage is applied as an input voltage Vi13, a through current ID flows from the VDD11 to the VSS12. Closer the input voltage/output current characteristics are to an ideal secondary function, stabler the chaos becomes that the linear mapping circuit generates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog or mixed analog / digital chaos generation circuit.

[0002]

2. Description of the Related Art In recent years, a chaos generation circuit has been attracting attention as a suitable random number generation circuit as a study of neurocomputers.

Hereinafter, a conventional chaos generating circuit will be described.

FIG. 15 shows a one-dimensional mapping circuit of a conventional chaos generating circuit. One of the resistors R111 is connected to the input Vi110.
The other is output Vo114 and is connected to both the anode of the first diode 112 and the cathode of the second diode 113, and the other of the two diodes is connected to the power supply.

FIG. 16 is a diagram showing input / output characteristics of a conventional primary mapping circuit.

[0006] By discretely sampling the one-dimensional mapping circuit of FIG. 16 using two sample-and-hold circuits as shown in FIG. 14, the following discrete operation is executed, and X (t + 1) = F (X ( t)) Chaos was generated analogously.

[0007]

However, the one-dimensional mapping circuit of the conventional chaos generating circuit has the following problems and is not suitable for integration.

First, in the one-dimensional mapping circuit of the conventional chaos generating circuit, a diode clamp is used, so that Vo
Is only about 1 V to 1.5 V, which is slightly higher than the forward voltage of the diode, and is susceptible to external noise, making it difficult to operate stably.

In a conventional one-dimensional mapping circuit of a chaos generating circuit, when an LSI is used, a resistor 1 is used to reduce the diode current in order to reduce the diode area.
It is necessary to increase the value of 11, and if the value of the resistor 111 is reduced, it is necessary to increase the area of the diode. In any case, there is a problem that the area cannot be reduced.

Further, when a P substrate is used in a low-cost MOS manufacturing process, the reference power supply of the diode of the conventional one-dimensional mapping circuit of the chaos generating circuit has to be fixed to VSS. When an N substrate is used, the reference power supply of the diode of the one-dimensional mapping circuit of the conventional chaos generation circuit must be fixed to VDD, and in order to widen the dynamic range, the midpoint potential of the positive power supply and the negative power supply is required. However, it is difficult to connect the midpoint potential to two opposing diodes due to the limitation of the semiconductor substrate in a general-purpose CMOS manufacturing process.

As described above, in the one-dimensional mapping circuit of the conventional chaos generating circuit, the dynamic range is narrow and the noise resistance is weak for stable chaos generation, and the size of the LSI is reduced, and the semiconductor wafer substrate can be freely used. There was a problem that could not be selected.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a chaos generation circuit which has a wide dynamic range and is easily formed into an LSI.

[0013]

In order to achieve the above object, the first means is to use a positive power supply as a current source.
A load component for generating a voltage by current is connected in series between the drain of the MOS-P channel transistor and the drain of the CMOS-N channel transistor having a negative power supply as a current source, and a gate of the CMOS-P channel transistor is connected to the load component. CMOS using a negative power supply as a current source
The gate of the N-channel transistor is commonly used as an input,
A chaos generation circuit is configured including a one-dimensional mapping circuit that outputs the voltage between both ends of the load.

As a second means, a current is applied between the drain of the P-channel transistor using the positive power supply as a current source and the drain of the CMOS-N-channel transistor using the negative power supply as a current source. The chaos generation circuit includes a one-dimensional mapping circuit configured by CMOS transistors as active elements as generated load components.

As a third means, a drain of a first CMOS-P-channel transistor using the positive power supply of the first means as a current source and a first CMOS-N channel using a negative power supply as a current source A first load component for generating a voltage by a current is connected in series between the drain of the transistor and a first CM using a gate of the first CMOS-P channel transistor and a negative power source as a current source;
A first CM using the gate of the OS-N channel transistor as a common input and using a positive power supply as a current source
A second load component for generating a voltage by current is connected between the drain of the OS-P channel transistor and the positive power supply, and a first CMO using the negative power supply as a current source
A chaotic circuit including a one-dimensional mapping circuit that connects a third load component that generates a voltage by current between a drain of the SN channel transistor and a negative power supply and outputs a voltage between both ends of the first load; Construct a generating circuit.

The fourth means comprises a one-dimensional mapping circuit having one of the second load component and the third load component of the third means to constitute a chaos generation circuit.

Further, as a fifth means, a chaos generating circuit including a one-dimensional mapping circuit constituted by a load component capable of appropriately changing both or one of the second load component and the third load component of the third means. Is configured.

As a sixth means, the drain of the first CMOS-P channel transistor having a positive power supply as a current source and the negative power supply having a current source described in the third to fifth means are described. A load component that generates a voltage with a current between the drain of one CMOS-N-channel transistor or a current between the drain of the first CMOS-P-channel transistor and a positive power supply whose current source is a positive power supply A load component that generates a voltage, or a load component that generates a voltage with a current between the drain of the first CMOS-N-channel transistor having a negative power supply as a current source and the negative power supply, or A chaos generation circuit is formed by using CMOS transistors as active elements for all load components.

As a seventh means, a CMOS-P which uses the positive power supply of the first means to the sixth means as a current source.
The potential of a load component that generates a voltage by current between the drain of a channel transistor and the drain of a CMOS-N channel transistor having a negative power supply as a current source is supplied to a positive input and a negative input of the differential amplifier. A chaos generating circuit including a one-dimensional mapping circuit that is connected to each other and outputs an output voltage based on a positive or negative power supply is configured.

As described above, a stable chaos generation circuit is realized and the conventional problem is solved.

Further, as an application, the first means to the seventh means
A neuro-computer system is constituted by using a plurality of chaos generating circuits constituted by the means.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described from a logistic function of chaos generation. The logistic function of chaos generation is expressed as X (t + 1) = aX (t) (1-X (t)) 0 <X <1, 0 <a. Here, t represents a discrete time, and X (t) represents a value of X at a specific time.

By transforming the above equation, X (t + 1) = − a (X (t) −0.5) ＾ 2 + a / 4 is obtained.

That is, the mapping function is a quadratic function of X. Further, the relationship between the gate voltage and the drain current of the MOS transistor also has the property of a quadratic function. The present invention is a MOS
It aims to realize a chaotic circuit by applying characteristics of a quadratic function of a transistor to a logistic function. This will be described below using a specific example.

First, a description will be given with reference to FIG.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and corresponds to claim 1. The respective sources of the P-channel transistor and the N-channel transistor made by the CMOS process technology are connected to the positive power supply VDD11 and the negative power supply VSS12, and the gates of the P-channel transistor and the N-channel transistor are connected in common and the input terminal Vi13 A load element 18 (impedance) that generates a voltage by current is connected between the drains of the P-channel transistor and the N-channel transistor, and the potential generated at both ends of the load element is configured as an output (Vo). .

Next, a specific operation will be described with reference to the drawings.

When a linear voltage is applied to the input voltage Vi13, a through current ID flows between VDD11 and VSS12 as shown in FIG. The closer the input voltage / output current characteristic is to an ideal quadratic function, the more stable the chaos can be generated in the one-dimensional mapping circuit. When this load 18 is a linear load component, when this current flows through the load 18 in FIG. 1, a voltage Vo having a similar function as that of ID is generated across the load 18.
As a method of changing this Vo to a reference of a negative power supply in order to facilitate the sample-hold and the like, as shown in FIG. 3 (second embodiment, corresponding to claim 7), Voz is increased by adding a differential amplifier 31. can get. FIG. 4 is a graph showing the input voltage / output voltage characteristics of the circuit of FIG. 3 and an ideal quadratic function.

As a third embodiment (corresponding to claim 2), there is shown a circuit in which the impedance component of FIG. 1 is constituted by MOS transistors as active elements as shown in FIG. The gate of the P-channel transistor 53 is connected to the drain 56 of the N-channel transistor 15 having a negative power source, and the gate of the N-channel transistor 54 is connected to the drain 55 of a P-channel transistor having a positive power source. The gate of the channel transistor 15 and the gate of the P-channel transistor 14 are used as the common input terminal 13. The source of the N-channel transistor 54 and the P-channel transistor 5
3 are commonly connected.

As described above, by crossing the gates of the P-channel transistor 53 and the N-channel transistor 54 of the load, V.sub.
The relationship between i and Vo approaches an ideal quadratic function. This figure 5
FIG. 6 illustrates the input voltage / output voltage characteristics of FIG.

FIG. 8 shows a fourth embodiment (corresponding to claim 3) in which a load component 84 and a load component 85 are connected in parallel with a P-type transistor 14 and an N-type transistor 15 as shown in FIG. However, it approaches the ideal quadratic function as shown in FIG. As a developed version, as shown in FIGS. 9 and 10, a load component may be connected in parallel to one of the P-type transistor 14 and the N-type transistor 15 (corresponding to claim 4). As a fifth embodiment, as shown in FIG. 11, a load component 19 that can control the value of the load component connected in parallel with the P-type transistor 14 and the N-type transistor 15 by the external terminals 199 and 197 is used.
8 and 196, the similarity of the quadratic function can be easily controlled from the outside by the control terminals 199 and 197 (corresponding to claim 5).

FIG. 7 (sixth embodiment, corresponding to claim 7) shows an embodiment in which a specific difference operation circuit of the differential amplifier in FIG. 3 is realized by a general-purpose OP amplifier.

FIG. 13 shows an embodiment of the entire system of the chaos generating circuit. FIG. 13 shows that the point corresponding to the output of the one-dimensional mapping circuit in FIG. 7 is connected to the input of the terminal 91 of the transistor switch 93 connected to the sample-and-hold capacitor 94, and the other of the transistor switch 93 is connected to the input of the OP amplifier 96. And both ends of the second transistor switch 99 are connected between the output 97 of the OP amplifier 96 and the second sample and hold capacitor 100. Further, the potential of the sample and hold capacitor 100 is connected to a terminal corresponding to the input of the one-dimensional mapping circuit in FIG. Hereinafter, the function of FIG. 13 will be briefly described.

The output potential of the one-dimensional mapping circuit is applied to the sample-and-hold capacitor 9 through the transistor switch 93.
4 and the transistor switch 93 is turned off at the next timing to prevent reverse flow of charge from the sample-and-hold capacitor 94. At the next timing, the transistor switch 9 is turned on by the OP amplifier 96.
9, the potential is held in the sample-hold capacitor 100, and the transistor switch 99 is turned off at the next timing to prevent the reverse flow of the current from the sample-hold capacitor 100. Chaos is generated by repeating the same operation as above as the input voltage of the one-dimensional mapping circuit based on the potential of the sample-and-hold capacitor 100.

[0035]

According to the present invention, the dynamic range is increased by using the same P-channel and N-channel transistors as those used in the digital LSI.
It is excellent in noise resistance and can be realized by using a MOS transistor for a conventional digital LSI. In addition, N of the semiconductor wafer substrate
There is an effect that a circuit can be freely configured including a combination with another circuit regardless of the type or the P type.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment.

FIG. 2 is a graph showing an input voltage and a power supply through current according to the first embodiment;

FIG. 3 is a block diagram showing a second embodiment.

FIG. 4 is a graph showing an input voltage and an output voltage according to the second embodiment;

FIG. 5 is a block diagram showing a third embodiment.

FIG. 6 is a graph showing an input voltage and an output voltage according to the third embodiment;

FIG. 7 is a block diagram showing a sixth embodiment.

FIG. 8 is a block diagram showing a fourth embodiment.

FIG. 9 is a block diagram showing an application of the fourth embodiment.

FIG. 10 is a block diagram showing an application of the fourth embodiment.

FIG. 11 is a block diagram showing a fifth embodiment.

FIG. 12 is an input voltage-output voltage graph of the fourth embodiment.

FIG. 13 is a diagram showing an embodiment of a chaos generation circuit using the one-dimensional mapping circuit of the present invention.

FIG. 14 is a block diagram of a chaos generation circuit using a one-dimensional mapping circuit.

FIG. 15 is a diagram showing a conventional one-dimensional mapping circuit;

FIG. 16 is a diagram showing input / output characteristics of a conventional diode clamp.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Positive power supply 12 Negative power supply 13 Input terminal 14 P-channel MOS transistor 15 N-channel MOS transistor 16, 17, 86, 87 Output terminal 18 Load component 31, 75, 96 OP amplifier 32, 55, 56 Output terminal 53 P channel MOS transistor 54 N-channel MOS transistor 71, 72, 73, 74, 76, 111 Resistance 77, 114 Output 83, 84, 85 Load component 91 One-dimensional mapping output 92 OP amplifier input terminal 93 Transistor switch 94 Sample hold capacitor 95 Sample Hold clock 97 OP amplifier output 98 Connection terminal (one-dimensional mapping circuit input) 99 Transistor switch 100 Sample-hold capacitor 101, 103 Sample-hold circuit 102 One-dimensional mapping circuit 104 Clock 1 105 Clock 2 110 Input 112, 113 Diode 115 GND

Claims (8)

[Claims] 1. A CMOS circuit using a positive power supply as a current source.
A load component for generating a voltage by current is connected in series between the drain of the P-channel transistor and the drain of the CMOS-N-channel transistor having a negative power source as a current source, and the gate of the CMOS-P-channel transistor is connected to the negative terminal. A chaos generating circuit, comprising: a one-dimensional mapping circuit that commonly receives a gate of a CMOS-N-channel transistor having a power source as a current source and outputs a voltage between both ends of the load. 2. A CMOS circuit using a positive power supply as a current source.
A one-dimensional mapping circuit comprising a MOS transistor as an active element as a load component for generating a voltage by current between a drain of a P-channel transistor and a drain of a CMOS-N-channel transistor having a negative power supply as a current source; The chaos generation circuit according to claim 1, wherein 3. A first CM using a positive power supply as a current source.
A first circuit for generating a voltage by current between a drain of an OS-P channel transistor and a drain of a first CMOS-N channel transistor having a negative power supply as a current source
Are connected in series, the gate of the first CMOS-P-channel transistor and the gate of the first CMOS-N-channel transistor having a negative power supply as a current source are commonly input, and a positive power supply is further provided. Is connected between a drain of a first CMOS-P-channel transistor having a current source as a current source and a second load component for generating a voltage by a current, and a first power source having a negative power source as a current source. A one-dimensional mapping circuit that connects a third load component that generates a voltage with a current between the drain of the CMOS-N-channel transistor and a negative power supply and outputs the voltage across the first load. 2. The chaos generating circuit according to claim 1, wherein: 4. The chaos generation circuit according to claim 3, further comprising a one-dimensional mapping circuit having one of the second load component and the third load component. 5. The chaos generating circuit according to claim 3, further comprising a one-dimensional mapping circuit including a load component capable of appropriately changing both or one of the second load component and the third load component. 6. A first CM using a positive power supply as a current source
A load component that generates a voltage with current between the drain of the OS-P channel transistor and the drain of the first CMOS N-channel transistor that uses a negative power supply as a current source, or a load component that uses a positive power supply as a current source. 1 CM
A load component that generates a voltage with a current between the drain of the OS-P channel transistor and the positive power supply, or a current between the drain of the first CMOS N-channel transistor using the negative power supply as a current source and the negative power supply. 6. The chaos generating circuit according to claim 3, wherein any one of the load components generating a voltage or all of the load components are constituted by MOS transistors as active elements. 7. A CMOS circuit using a positive power supply as a current source.
The potential of a load component that generates a voltage by current between the drain of a P-channel transistor and the drain of a CMOS-N-channel transistor having a negative power supply as a current source is expressed by a positive input and a negative input as inputs of a differential amplifier. And a one-dimensional mapping circuit connected to the first and second terminals for outputting an output voltage based on a positive or negative power supply.
6. The chaos generation circuit according to any one of items 5 to 5. 8. The neurocomputer system according to claim 1, wherein a plurality of chaos generating circuits are used.