JP2000215081A - Trace information gathering mechanism - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record trace information of a processor including software invisible information in the execution order and description order of instructions and to access it. SOLUTION: An order tag issue part 2310 attach an order tag to an instruction decoded by an instruction decoder 151. Function units 170, 171, 172, and 173 informs an instruction completing the process of the appended order tag and the execution status of the instruction. A write part, 211 writes the order tag reported in instruction execution order trace information gathering mode to a trace memory 213 at every clock cycle by using a clock cycle as an address and writes the execution status reported in instruction description trace information gathering mode to the trace memory 213 by using the reported order tag as an address. A read part 214 transfers the contents of the trace memory 213 to the register of a register file 152.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a trace information collecting mechanism for collecting trace information indicating an execution history in a processor of a computer system, and particularly to a trace information including information invisible from software (hereinafter referred to as software invisible information). The present invention relates to a trace information collecting mechanism that enables software to collect itself.

[0002]

2. Description of the Related Art There have been known several methods for collecting various states during operation of a processor as trace information.

[0003] Japanese Patent Application Laid-Open Nos. Hei 5-173838 and Hei 8-161195 disclose techniques for recording the history of addresses of machine language instructions executed by a processor. These techniques are mainly intended to record the addresses of executed machine language instructions on a program for a long period of time.

Japanese Patent Application Laid-Open No. 6-83670 discloses that
A technique is disclosed in which operand information and the like of an executed instruction are stored as trace information in a storage area, and a comparison is made with the correct trace information described in advance. The main purpose of this technique is to efficiently test a program.

[0005]

The above-mentioned prior art has several problems.

The first problem is that only the history of information observable from software such as instruction addresses and operands is collected, and the history of software invisible information is not collected. Trace information including software invisible information such as instruction execution timing is important in developing and debugging a processor that implements advanced functions such as superscalar instructions and out-of-order execution of instructions.

A second problem is that the collection control of the trace information and the use of the collection result cannot be flexibly performed by software. For example, JP-A-5-1738
In the technology disclosed in Japanese Patent Application Laid-Open Publication No. 38-138 and Japanese Patent Application Laid-Open No. 8-161195, only the history of instruction addresses is collected. Must be scanned. The technique disclosed in Japanese Patent Application Laid-Open No. H6-83670 is a method specialized for matching and matching with correct trace information described in advance.

These conventional techniques are used for purposes such as, for example, automatically verifying a processor using a large-scale test program, and improving the performance of an application program based on collected trace information. Was not easy.

A first object of the present invention is to provide processor trace information including software invisible information that cannot be directly known from software, such as the state of an instruction execution pipeline and the presence or absence of a cache hit, by using the instruction execution order and instruction execution order. An object of the present invention is to provide a trace information collecting mechanism for recording information in the order of description.

A second object of the present invention is to make it possible to easily and flexibly access collected trace information from software, thereby enabling not only autonomous processor inspection by software in processor development but also application It is an object of the present invention to provide a trace information collecting mechanism useful for improving performance in program development.

[0011]

According to the present invention, there is provided a trace information collecting mechanism for a processor having an instruction decoder, each functional unit, and a register file, each time an instruction is decoded by the instruction decoder, a different tag is attached to the instruction. The tag issuing unit (210 in FIG. 1), the functional unit (170, 171, 172, and 173 in FIG. 1) for notifying the tag attached to the processed instruction, and the instruction decoder A cycle counter (FIG. 1) which is reset to an initial value determined when decoded and increases in value every clock cycle of the processor.
212), a trace memory (213 in FIG. 1) for recording trace information, and a tag notified from the functional unit in the trace memory using the clock cycle value of the cycle counter as an address for each clock cycle of the processor. Write unit for writing (21 in FIG. 1)
1) and a reading unit (214 in FIG. 1) for transferring the contents of the trace memory to the register of the register file
And characterized in that:

Further, the trace information collecting mechanism of the present invention
In a processor including an instruction decoder, each functional unit, and a register file, each time an instruction is decoded by the instruction decoder, a tag issuing unit (210 in FIG. 1) for attaching a different tag to the instruction; The functional unit (170, 171, 17 in FIG. 1) for notifying the attached tag and the execution status of the instruction.
2, 173), a trace memory (213 in FIG. 1) for recording trace information, and a writing unit (213) for writing the execution status notified from the functional unit to the trace memory using the tag notified from the functional unit as an address. 1 and a reading unit (214 in FIG. 1) for transferring the contents of the trace memory to the register of the register file.

Further, the trace information collecting mechanism according to the present invention, in a processor having an instruction decoder, each functional unit and a register file, is instructed by the trace information selection instruction when the instruction decoder decodes the trace information selection instruction. A trace information selecting unit (215 in FIG. 1) for holding the trace mode, and a tag issuing unit (210 in FIG. 1) for attaching a different tag to the instruction each time the instruction is decoded by the instruction decoder.
And the functional unit (1 in FIG. 1) for notifying the tag attached to the instruction after the processing and the execution status of the instruction.
70, 171, 172, 173) and a cycle counter (212 in FIG. 1) which is reset to an initial value determined when the initialization instruction is decoded by the instruction decoder and increases every clock cycle of the processor.
And a trace memory (2 in FIG. 1) for recording trace information.
13) When the trace mode held in the trace information selecting unit is the instruction execution order trace information collection mode, the tag notified from the functional unit is stored in the trace memory using the clock cycle value of the cycle counter as an address. A tag which is written in each clock cycle of the processor, and the execution status notified from the functional unit when the trace mode held in the trace information selecting unit is the instruction description order trace information collecting mode, is a tag notified from the functional unit. A writing unit (21 in FIG. 1) for writing in the trace memory as an address
1) and a reading unit (214 in FIG. 1) for transferring the contents of the trace memory to the register of the register file
And characterized in that:

Still further, according to the present invention, there is provided a trace information collecting mechanism, wherein a processor provided with an instruction decoder, each functional unit and a register file has an initial value determined when a trigger instruction of a trace information collecting operation is decoded by the instruction decoder. A sequence tag issuing unit that has an internal counter that is reset to a value and increases each time the instruction is decoded by the instruction decoder, and attaches the count value of the internal counter as an order tag to the instruction decoded by the instruction decoder (210 in FIG. 1) and the functional unit (170, 171, 172, 173 in FIG. 1) for notifying the order tag attached to the instruction after the processing.
A cycle counter (212 in FIG. 1) which is reset to an initial value determined when a trigger instruction of a trace information collecting operation is decoded by the instruction decoder and increases in value every clock cycle of the processor; A trace memory (213 in FIG. 1) for recording
A writing unit (211 in FIG. 1) for writing the order tag notified from the functional unit to the trace memory using the clock cycle value of the cycle counter as an address for each clock cycle of the processor, and writing the contents of the trace memory to the register A reading unit (214 in FIG. 1) for transferring the data to a file register.

Further, the trace information collecting mechanism of the present invention comprises:
In a processor including an instruction decoder, each functional unit and a register file, a reset instruction is reset to an initial value determined when a trigger instruction of a trace information collecting operation is decoded by the instruction decoder, and each time the instruction is decoded by the instruction decoder. An order tag issuing unit (210 in FIG. 1) having an internal counter for increasing the value and attaching the count value of the internal counter as an order tag to the instruction decoded by the instruction decoder; The functional unit (170, 1 in FIG. 1) for notifying the executed order tag and the execution status of the instruction.
71, 172, 173), a trace memory (213 in FIG. 1) for recording trace information, and the execution status notified from the functional unit is written to the trace memory using the order tag notified from the functional unit as an address. It is characterized by comprising a writing unit (211 in FIG. 1) and a reading unit (214 in FIG. 1) for transferring the contents of the trace memory to the register of the register file.

Further, a trace information collecting mechanism according to the present invention, in a processor having an instruction decoder, each functional unit and a register file, is instructed by the trace information selection instruction when the instruction decoder decodes the trace information selection instruction. A trace information selecting unit (215 in FIG. 1) for holding the trace mode, and resetting to an initial value determined when a trigger instruction of a trace information collecting operation is decoded by the instruction decoder, and the instruction is decoded by the instruction decoder. A sequence tag issuing unit (210 in FIG. 1) having an internal counter that increases each time the instruction is read, and attaching the count value of the internal counter as an order tag to the instruction decoded by the instruction decoder; Order tag attached to the instruction and the execution style of the instruction. The functional unit (170, 171, 172, 173 in FIG. 1) for notifying the status, and the instruction decoder resets a clock signal of the processor to an initial value determined when a trigger instruction of a trace information collecting operation is decoded. A cycle counter (212 in FIG. 1) whose value increases in each cycle, a trace memory (213 in FIG. 1) for recording trace information, and a trace mode held in the trace information selector are used to collect instruction execution order trace information. When the mode is the mode, the order tag notified from the functional unit is written to the trace memory every clock cycle of the processor using the clock cycle value of the cycle counter as an address, and the trace mode held in the trace information selecting unit is In the instruction description order trace information collection mode A writing unit (211 in FIG. 1) for writing the execution status notified from the functional unit to the trace memory using the order tag notified from the functional unit as an address, and writing the contents of the trace memory into the register of the register file. And a read-out unit (214 in FIG. 1) for transferring the data.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of a processor 110 incorporating a trace information collecting mechanism according to an embodiment of the present invention. This processor 110
Are connected to the instruction memory 100 and the data memory 101, and the instruction cache 150, the instruction decoder 15
1, register file 152, reorder buffer 15
3, a superscalar processor including a data cache 160, a branch unit 170, an arithmetic unit 171, a load unit 172, and a store unit 173, and an order tag issuing unit 210, a writing unit 211, a cycle counter 212, a trace memory 213, and a reading unit. 214 and a part of a trace information collecting mechanism comprising a trace information selecting unit 215.

The super scalar processor is described in "Super Scalar Processor" (authored by Mike Johnson, translated by Kazuaki Murakami, Nikkei BP Publishing Center, 19
(1994), pp. 44 et seq., And corresponds to the standard superscalar processor model. The configuration and operation limited to the superscalar processor are described in the above references. It is detailed on the page.

First, the configuration of the super scalar processor will be briefly described.

The super scalar processor includes, as functional units, a branch unit 170, an arithmetic unit 171,
One load unit 172 and one store unit 173 are provided. Each functional unit (170, 171,
172, 173) are provided with reservation stations 180, 181, 182, 183 at their entrances, respectively.
2,183, the order tag fields 220, 22
One or more entries including 1, 222, and 223 are provided.

The instruction cache 150 includes the instruction memory 10
The instruction fetched from 0 is temporarily stored.

The instruction decoder 151 has an instruction cache 1
An instruction is taken out of the function unit 50, one of the functional units (170, 171, 172, 173) capable of processing the instruction is selected, and a reservation station (180, 18 depending on the functional unit) provided at the entrance of the functional unit is selected.
The operation code (instruction type) and the operand information (operand register value) of the instruction are stored in the empty entry of any one of (1, 182, 183).

The register file 152 stores an operand register value required by each functional unit (170, 171, 172, 173) in each functional unit (170, 17).
1,172,173) to the reservation stations 180,181,182,183 at the entrance.

The reorder buffer 153 manages the operation result of each processed instruction, and writes the register value of the calculation result for the processed instruction to the register file 152. The reorder buffer 153 stores the operand register values required by each functional unit (170, 171, 172, 173) in each functional unit (170, 17).
1,172,173) to the reservation stations 180,181,182,183 at the entrance.

The branch unit 170 extracts the operation code and the operand information from the reservation station 180 provided at the entrance, performs the branch processing, and sends the result to the reorder buffer 153.

The operation unit 171 extracts the operation code and the operand information from the reservation station 181 provided at the entrance, performs the operation processing, and sends the result to the reorder buffer 153.

The load unit 172 extracts the operation code and the operand information from the reservation station 182 provided at the entrance, and
0, the data is read from the data memory 101, and the data is sent from the data cache 160 to the reorder buffer 153.

The store unit 173 extracts the operation code and the operand information from the reservation station 183 provided at the entrance, and
Data is written to the data memory 101 via “0”.

Next, the configuration of the trace information collecting mechanism according to the present embodiment will be described.

The order tag issuing section 210 has an internal counter. This internal counter is used when the instruction decoder 151 decodes a trigger instruction instructing the start of the trace information collecting operation, for example, a predetermined initial value, for example. Reset to value 0.

The order tag issuing unit 210 is provided with the instruction decoder 1
51 decodes the instruction and converts each functional unit (170, 1
71, 172, 173), every time the operation code and operand information are sent to the reservation stations 180, 181, 182, 183, the count value of the internal counter is incremented by one, and the count value of the internal counter is used as an order tag, and Reservation station 18 to which opcode and operand information has been sent
0, 181, 182, and 183 are stored in the order tag fields 220, 221, 222, and 223 of the entries.

Each functional unit (170, 171, 17)
2,173) are reservation stations 180,
When the processing of the opcode and operand information of one instruction in the entries in 181, 182 and 183 is completed,
The order tag of the command and the execution status related to the processing of the command are sent to the writing unit 211. That is, for an instruction requiring a plurality of clock cycles for processing, the functional unit (170, 171, 172, 173) outputs the order tag and the execution status only in the last clock cycle.

The trace information selecting section 215 has an internal register and holds a trace mode, that is, an operation mode of the trace information collecting mechanism. The trace mode is set in the trace information selection unit 215 when the instruction decoder 151 decodes the trace information selection instruction. The trace mode includes a trace mode for collecting trace information in the order of instruction execution (hereinafter referred to as an instruction execution order trace information collection mode) and a trace mode for collecting trace information in the order of instruction description (hereinafter referred to as an instruction description order trace information collection mode). ).

The cycle counter 212 is provided for the processor 1
This counter is incremented by one every ten clock cycles, and is reset to a predetermined initial value, for example, initial value 0 when the instruction decoder 151 decodes a trigger instruction of a trace information collecting operation.

The writing unit 211 receives the clock cycle value CY sent from the cycle counter 212 in accordance with the trace mode held in the trace information selection unit 215.
C and each functional unit (170, 171, 172, 17)
Using the sequence tag and execution status sent from 3) as input, a set of a write address and write data for writing trace information to the trace memory 213 is generated. Note that a plurality of sets of the write address and the write data may be generated in the same clock cycle. The writing unit 211 writes the trace information in the trace memory 213 along the set of the write address and the write data.

The trace memory 213 is a set of memory cells addressed at a row position and a column position. The capacity required for the trace memory 213 is the capacity of a rectangular memory area in which the maximum number of bits of information to be recorded in one clock cycle is in the column direction, and the longest clock cycle number or the longest instruction number in which the history is to be recorded is the row direction. For example, in this embodiment, the memory has a small capacity of 20 bits in the column direction and 32 rows in the row direction.

Generally, the trace memory 213 has a plurality of write ports. The number of write ports is determined by the functional units (170, 171, 1) of the processor 110.
72, 173), and in this embodiment, 4
It is a book. The trace memory 213 must be able to write data every clock cycle,
The writing can be performed only in row units, that is, it is only necessary to perform writing with the row position as an address.

The trace memory 213 has two read ports, one of which must be capable of reading one row of data at a time and the other being capable of reading one column of data at a time. Unlike a write operation, a read operation need not necessarily be possible every clock cycle.

The reading unit 214 is provided in the trace memory 21
3 is read out, and sent to the reorder buffer 153.

Next, the generation of the write address and the write data in the writing section 211 will be described in more detail with reference to FIGS. 2, 3 and 4.

FIG. 2 is a diagram showing input / output data of the writing unit 211. Arrows in the figure indicate a group of signal lines transmitting each data, and one arrow does not necessarily mean 1-bit data.

The writing unit 211 stores each functional unit (1
70, 171, 172, 173) from the order tag TAG
BR, TAGALU, TAGLD, TAGST and execution status STATBR, STATALU, STAT
LD, STATST, trace mode MODE from the trace information selection unit 215, cycle counter 212
Receives the clock cycle value CYC as an input.

The output signal from the write unit 211 includes write valid signals WE0, WE1, WE2, and WE3 indicating that valid write data exists, and a write address WA indicating a write row position in the trace memory 213.
0, WA1, WA2, and WA3 and write data WD0, WD1, WD2, and WD3 that are values to be actually written.
Is a set of three, and a total of four sets of write information.
These are sent to four write ports # 0, # 1, # 2, and # 3 of the trace memory 213.

FIG. 3 shows a data flow in the instruction execution order trace information collecting mode in the writing unit 211.

When the trace mode MODE indicates the instruction execution order trace information collection mode, the writing unit 211
Is a write enable signal WE for write port # 0.
Enable only 0.

The write section 211 outputs the clock cycle value CYC as the write address WA0 of the write port # 0, and the write data WD0 is sent from each functional unit (170, 171, 172, 173). 5-bit order tag TAGBR, TAG
ALU, TAGLD, TAGST bit-connected 20
Output the value of a bit. Note that the execution status TAGB
The specific bits R, TAGALU, TAGLD, and TAGST indicate a valid bit, and this bit is not on, that is, the functional unit (1
70, 171, 172, 173), a 5-bit value 000000 is used as the order tag.

FIG. 4 shows the flow of data in the instruction description order trace information collection mode in the writing unit 211.

When the trace mode MODE indicates the instruction description order trace information collection mode, the writing unit 211
For write ports # 0, # 1, # 2, # 3
Corresponding functional units (170, 171, 172, 17
Execution status STATBR, S sent from 3)
It outputs TATALU, STATLD, and STATST, respectively.

Further, the writing unit 211 responds to each of the write addresses WA0, WA1, WA2, and WA3 with the corresponding functional unit (170, 171, 172, 173).
Order tags TAGBR, TAGALU,
TAGLD and TAGST are output.

Further, the write unit 211 responds to each of the write valid signals WE0, WE1, WE2, and WE3 with the corresponding functional unit (170, 171, 172, 17).
Valid execution status STATBR, STAT from 3)
Enable is output only when ALU, STATLD, and STATST are sent. Note that the execution status S
TATBR, STATALU, STATLD, STAT
Only when the ST valid bit is ON, the write valid signals WE0, WE1, WE2, and WE3 are enabled.

Next, the operation of the thus configured trace information collecting mechanism according to the present embodiment will be described with reference to FIGS.
This will be specifically described with reference to FIG.

Here, the instruction issue specification of the processor 110 is assumed as follows. Instruction issuance is in order. That is, instructions are issued in the order described in the program. Each functional unit (170, 171, 172, 1
73) includes reservation stations 180, 181, 182, 183 having two entries. The instruction decoder 151 can issue up to three instructions in one clock cycle if there are empty entries in the reservation stations 180, 181, 182, 183 of the functional units (170, 171, 172, 173) that perform the processing. The operation unit 171 can execute the operation instruction in one clock, and the load unit 172 and the store unit 173 can execute the load and store instruction in two clocks.

FIG. 5 is a diagram showing a list of processor instructions related to the operation of the trace information collecting mechanism according to the present embodiment.

The PSEL instruction is a trace information selection instruction, and indicates a trace mode by a bit pattern of a parameter mode (which may include one or more parameters). The designated trace mode is held in the trace information selecting unit 215, and is used for signal selection in the writing unit 211 in the subsequent trace information collecting operation.
For example, if the first parameter is unit, the instruction execution order trace information collection mode is specified, and the type of the trace information to be collected is a functional unit (170, 171, 171).
172, 173) The order tag TA of the instruction after completion of each process.
GBR, TAGALU, TAGLD, and TAGST are selected (see FIG. 6). Also, if the first parameter is stat
If us, the instruction description order trace information collection mode is designated, and the execution status STATBR, STATALU, STA of each instruction is set as the type of trace information to be collected.
TLD and STATST are selected (see FIG. 10). Note that the designation of the second parameter reset resets the entire contents of the trace memory 213 to the initial value 0 (see FIGS. 6 and 10).

The PTRIG instruction is a trigger instruction for a trace information collecting operation. The PTRIG instruction sets the count value of the internal counter of the order tag issuing unit 210 to an initial value 0, and sets the cycle counter 21
In addition to resetting the clock cycle value CYC of No. 2 to the initial value 0, the entire trace information collecting mechanism is made to operate thereafter.

The PSTOP instruction is a command for stopping the trace information collecting operation. The PSTOP instruction stops the counting operation of the internal counter of the order tag issuing unit 210 and the cycle counter 212, and the trace memory 2 of the writing unit 211.
13 is stopped.

The PRDR instruction and the PRDC instruction are instructions for reading the trace information collected in the trace memory 213 into the register of the register file 152. The PRDR instruction reads the contents of the row of the trace memory 213 specified by the second parameter row #,
Transfer to the register specified by parameter reg #.
The PRDC instruction reads the contents of the column of the trace memory 213 specified by the second parameter col # and transfers the read contents to the register specified by the first parameter reg #.

FIG. 6 is a diagram showing a part of a program for collecting trace information. The numbers 1 to 12 at the left end are instruction numbers assigned to each instruction for explanation. In the figure, instruction numbers 1 and 2 are a part for preparing to collect trace information, instruction numbers 3 to 11 are a part for collecting trace information, and an instruction number 12 is a part for stopping the collection of trace information. is there. This program is an example of the instruction execution order trace information collection mode. That is, the trace information is collected not in the order of description of the instructions in the program but in the clock cycle of the execution of the instructions.

FIGS. 7 and 8 show the issued instructions and the reservations stored in the reservation stations 180, 181, 182, 183 of the functional units (170, 171, 172, 173) in the execution of the program shown in FIG. Instructions (RVST in the figure stands for reservation station), each functional unit (170, 17
1, 172, 173), and the write address and write data sent to the write unit 211 are shown for each clock cycle.

FIG. 9 is a diagram showing trace information in the trace memory 213 at the stage when the execution of the program shown in FIG. 6 has been completed.

Next, an operation when collecting trace information in the instruction execution order trace information collecting mode based on the example of the program shown in FIG. 6 will be described.

The instruction decoder 151 outputs the PS of the instruction number 1
When the EL instruction is decoded, the instruction execution order trace information collection mode (the type of trace information to be collected is a functional unit (170, 1
71, 172, 173) The order tag TAGBR, TAGLU, TAGLD, TAGs of the instruction that has been processed for each process.
T) is selected and set in the trace information selection unit 215.
Further, the instruction decoder 151 outputs the second parameter
At t, the entire contents of the trace memory 213 are reset to the initial value 0.

Next, the instruction decoder 151 sets the instruction number 2
Decodes the PTRIG instruction of
The internal counter 10 is reset to an initial value 0, and the cycle counter 212 is reset to an initial value 0.
Put the entire trace information collection mechanism in operation. here,
The LW instruction (load instruction) of instruction number 3 is the instruction decoder 1
The clock cycle decoded from 51 is set to clock cycle 0 based on the cycle clock value CYC (= 0) of the cycle counter 212.
Each clock cycle of 0 is referred to as clock cycle 1, clock cycle 2,...

The operation in clock cycle 0 is as follows.

The instruction decoder 151 outputs the LW of the instruction number 3
When the instruction is decoded, the operation code and the operand information are stored in a free entry of the reservation station 182 of the load unit 172.

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one, and
Issued as an order tag for the instruction,
1 writes the order tag field 222 in the corresponding entry in the reservation station 182 of the load unit 172 in which the operation code and operand information of the LW instruction are stored (see FIG. 7).

Next, when the instruction decoder 151 decodes the following LI instruction (constant load instruction) of instruction number 4,
The operation code and the operand information are stored in an empty entry of the reservation station 181 of the arithmetic unit 171 during the same clock cycle 0.

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one, and
Issued as an order tag for the instruction,
1 writes the order code field 221 in the corresponding entry in the reservation station 181 of the arithmetic unit 171 in which the operation code and the operand information of the LI instruction are stored (see FIG. 7).

Subsequently, the instruction decoder 151 decodes the next ANDI instruction (logical operation instruction) of the instruction number 5. The instruction decoder 151 stores the operation code and operand information of the decoded instruction in an empty entry of the reservation station 181 of the arithmetic unit 171 during the same clock cycle 0 because there is still an empty entry in the reservation station 181.

At the same time, the order tag issuing section 210 increments the value of the internal counter by one, and
It is issued as an order tag for the DI instruction, and is written by the instruction decoder 151 into the order tag field 221 in the corresponding entry in the reservation station 181 of the arithmetic unit 171 in which the operation code and operand information of the ANDI instruction are stored (see FIG. 7).

In clock cycle 0, the writing section 211 sends the clock cycle value CYC (= 0) of the cycle counter 212 to the trace memory 213 as a write address. In addition, the writing unit 211 transmits valid sequence tags TAGBR, TAGALU, and TAGL from each functional unit (170, 171, 172, 173).
D, TAGST is not sent, so 5-bit value 0
The 20-bit write data 0000000000000000000, which is obtained by concatenating four 0000 bits, is sent to the trace memory 213 (see FIG. 7).

As a result, the write data 000000 is stored in row 0 of the trace memory 213 indicated by the write address.
000000000000000 is written as trace information (see FIG. 9).

Next, the operation in clock cycle 1 is as follows.

The operation unit 171 executes processing of the LI instruction based on the operation code and the operand information issued in the clock cycle 0 and stored in the entry of the reservation station 181, and finishes the processing of L.
The value 2 of the order tag and the execution status for the I instruction are sent to the writing unit 211 (see FIG. 7).

Similarly, load unit 172 is issued at clock cycle 0, and starts processing the LW instruction based on the operation code and the operand information stored in the entry of reservation station 182. Since the processing of the load instruction requires two clocks, the load unit 172 does not send the order tag and the execution status to the writing unit 211 in this clock cycle (see FIG. 7).
reference).

On the other hand, the instruction decoder 151 outputs the instruction number 6
When the SLLV instruction (logical operation instruction) is decoded, its operation code and operand information are
1 is stored in an empty entry of the reservation station 181.

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one and
The instruction is issued as an order tag for the LV instruction, and the instruction decoder 151 writes the operation code and operand information of the SLLV instruction in the order tag field 221 in the corresponding entry in the reservation station 181 of the arithmetic unit 171 (see FIG. 7).

On the other hand, the writing section 211 sends the clock cycle value CYC (= 1) of the cycle counter 212 to the trace memory 213 as a write address.
In addition, the writing unit 211 stores the function units (170,
171, 172, 173), and transmits the 20-bit long write data 000000001000000000000 to the trace memory 213 by bit-concatenating the 5-bit sequence tags (see FIG. 7).

As a result, 20-bit write data 00000001000000000000000 is written as trace information in row 1 of the trace memory 213 indicated by the write address (see FIG. 9).

As described above, the order tag is attached together with the instruction operation code and the operand information and sent to the functional unit that performs the processing.
When the instruction is processed in (1, 172, 173), the order tag attached to the opcode and the operand information of the instruction is written as trace information to the trace memory 213 via the writing unit 211 every clock cycle. Go.

Finally, the instruction decoder 151 sets the instruction number 1
2 fetches the PSTOP instruction, the instruction decoder 1
51, waits until all preceding instructions (instructions with an instruction number of 11 or less) have been completed, that is, when there is no preceding instruction in the reorder buffer 153, decodes the PSTOP instruction, and issues the opcode to the sequence tag. Part 21
0, sent to the trace information selection unit 215 and the cycle counter 212.

Thus, the order tag issuing unit 210 stops issuing a new order tag, and
Stops the counting operation and sets the trace information selection unit 215
Is instructed to the writing unit 211 and the trace memory 213
The writing of the new trace information to the trace information collection is stopped, and the operation of the entire trace information collection mechanism stops.

As described above, in the instruction execution order trace information collection mode, since the writing unit 211 records the order tag using the clock cycle as an address, the trace information is stored in the trace memory 213 every clock cycle in which the instruction is executed. Can be recorded.

FIG. 10 is a diagram showing a part of another program for collecting trace information. This program is
This is an example of collecting trace information in the instruction description order trace information collection mode. That is, trace information is collected not in the order of clock cycles of instruction execution but in the order of instruction description in a program.

FIG. 11 shows each functional unit (170, 171, 17) in executing the program shown in FIG.
2, 173) output order tags TAGBR, TAGA
LU, TAGLD, TAGST and execution status S
TATBR, STATALU, STATLD, STAT
ST, and the write address and write data sent to the write unit 211 are shown in order for each clock cycle.

FIG. 12 shows trace information in the trace memory 213 obtained by executing the program part shown in FIG.

Next, the operation of collecting trace information in the instruction description order trace information collection mode based on the example of the program shown in FIG. 10 will be described.

The instruction decoder 151 outputs the PS of the instruction number 1
When the EL instruction is decoded, the first parameter statu
According to s, the instruction description order trace information collection mode (the execution status of each instruction as the type of trace information to be collected) is selected and set in the trace information selection unit 215.
Further, the instruction decoder 151 outputs the second parameter
At t, the entire contents of the trace memory 213 are reset to the initial value 0.

Next, the instruction decoder 151 outputs the instruction number 2
Decodes the PTRIG instruction of
The internal counter 10 is reset to an initial value 0, and the cycle counter 212 is reset to an initial value 0.
Put the entire trace information collection mechanism in operation. here,
The LW instruction (load instruction) of instruction number 3 is the instruction decoder 1
The clock cycle decoded from 51 is set to clock cycle 0 based on the cycle clock value CYC (= 0) of the cycle counter 212.
Each clock cycle of 0 is referred to as clock cycle 1, clock cycle 2,...

The operation in clock cycle 0 is as follows.

The instruction decoder 151 outputs the LW of the instruction number 3
When the instruction is decoded, the operation code and the operand information are stored in a free entry of the reservation station 182 of the load unit 172.

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one, and
Issued as an order tag for the instruction,
1 writes the order code field 222 in the corresponding entry in the reservation station 182 of the load unit 172 in which the operation code and the operand information of the LW instruction are stored (see FIG. 11).

Next, when the instruction decoder 151 decodes the following LW instruction of instruction number 4, it stores the operation code and the operand information in the reservation station 18.
Since there is still an empty entry in 2, it is stored in the empty entry of the reservation station 182 of the load unit 172 during the same clock cycle 0.

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one, and
Issued as an order tag for the instruction,
1 writes the order code field 222 in the corresponding entry in the reservation station 182 of the load unit 172 in which the operation code and the operand information of the LW instruction are stored (see FIG. 11).

Next, when the instruction decoder 151 decodes the following LI instruction (constant load instruction) of instruction number 5,
The operation code and the operand information are stored in an empty entry of the reservation station 181 of the arithmetic unit 171 during the same clock cycle 0.

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one, and
Issued as an order tag for the instruction,
1 writes the order code field 221 in the corresponding entry in the reservation station 181 of the arithmetic unit 171 in which the operation code and the operand information of the LI instruction are stored (see FIG. 11).

In the clock cycle 0, the writing unit 211 transmits the function units (170, 171, 172,
From 173), the effective execution status STATBR, ST
Since ATALU, STATLD, and STATST have not been sent, the write address and write data are not sent to the trace memory 213 (see FIG. 11).

The operation in clock cycle 1 is as follows.

The operation unit 171 executes the processing of the LI instruction based on the operation code and the operand information issued in the clock cycle 0 and stored in the entry of the reservation station 181 and finishes the processing.
The value 3 of the order tag for the I instruction and the execution status "---" (encoded into a binary number of an appropriate number of bits, the same applies hereinafter) are sent to the writing unit 211 (see FIG. 11). The execution status is information indicating a flag change of a calculation result in the calculation unit 171 and indicates a change of a carry flag, an overflow flag, a sign flag, and a zero flag in order from the left. "---
"-" Means that none of the four flags change.

Similarly, the load unit 172 executes the processing of the LW instruction of the instruction number 3 based on the operation code and the operand information which are issued in the clock cycle 0 and stored in the previous entry of the reservation station 182. However, during clock cycle 0, LW
Since the processing of the instruction is not completed, the load unit 172
Does not send the value 1 and the execution status of the order tag for the processed LW instruction to the writing unit 211 (see FIG. 11).

On the other hand, the instruction decoder 151 outputs the instruction number 6
When the AND instruction (logical operation instruction) is decoded, its operation code and operand information are
Is stored in a free entry of the reservation station 181.

At the same time, the order tag issuing unit 210 increments the value of the internal counter by one, and
Issued as an order tag for the D instruction, the instruction decoder 1
At 51, the operation code and the operand information of the AND instruction are written into the order tag field 221 in the corresponding entry in the reservation station 181 of the arithmetic unit 171 (see FIG. 11).

Next, the instruction decoder 151 sets the instruction number 7
When the CMP instruction (comparison instruction) is decoded, since the reservation station 181 still has an empty entry, the operation code and the operand information are stored in the empty entry of the reservation station 181 of the arithmetic unit 171 in the same clock cycle 1. .

At the same time, the order tag issuing unit 210 increases the value of the internal counter by one, and
Issued as an order tag for the P instruction, the instruction decoder 1
At 51, the operation code and the operand information of the CMP instruction are stored in the order tag field 221 in the corresponding entry in the reservation station 181 of the arithmetic unit 171 (see FIG. 11).

On the other hand, the writing section 211 sends the value 3 of the order tag sent from the arithmetic unit 171 to the trace memory 213 as a write address, and
The execution status “−−−−” sent from the arithmetic unit 171 is used as write data in the trace memory 2.
13 (see FIG. 11).

As a result, the write data “−−−−” is stored in row 3 of the trace memory 213 indicated by the write address.
"-" Is written as trace information (see FIG. 12).

The operation in clock cycle 2 is as follows.

The load unit 172 stores the L of the instruction number 3
The processing of the W instruction is completed, and the value 1 of the order tag and the execution status "hit" (however, encoded in a binary number having an appropriate number of bits, the same applies hereinafter) are output. The execution status “hit” means that the data cache 160 has been hit in the load processing by the load unit 172. In this clock cycle 2, no other functional unit has completed the processing, and only the value 1 of the order tag and the execution status “hit” are sent to the writing unit 211.

The writing unit 211 includes the load unit 17
2 is sent to the trace memory 213 as a write address, and the execution status “h” sent from the load unit 171 is sent.
is transmitted to the trace memory 213 as write data (see FIG. 11).

As a result, the write data “hit” is stored in row 1 of the trace memory 213 indicated by the write address.
Is written as trace information (see FIG. 12).

As described above, the order tag is attached together with the instruction's operation code and operand information, sent to the functional unit for processing, and is sent to each functional unit (170, 17).
When the instruction is processed in (1, 172, 173), its execution status is written as trace information to the trace memory 213 using the order tag attached to the operation code and operand information of the instruction as a write address.

Finally, when the instruction decoder 151 fetches the PSTOP instruction of the instruction number 8, the instruction decoder 151
51, waits until all preceding instructions (instructions with an instruction number of 7 or less) have been completed, that is, when there is no preceding instruction in the reorder buffer 153, decodes the PSTOP instruction, and issues the opcode to the order tag. Part 21
0, sent to the trace information selection unit 215 and the cycle counter 212.

As a result, the order tag issuing unit 210 stops issuing a new order tag, and
Stops the counting operation and sets the trace information selection unit 215
Is instructed to the writing unit 211 and the trace memory 213
The writing of the new trace information to the trace information collection is stopped, and the operation of the entire trace information collection mechanism stops.

As described above, in the instruction description order trace information collection mode, since the writing unit 211 records the execution status using the order tag indicating the instruction description order as an address, regardless of the clock cycle in which the instruction is executed. The trace information can be recorded in the trace memory 213 according to the description order of the instructions in the program.

In the above description of the embodiment, the order tag issuing section 210 has an internal counter and the count value of the internal counter is attached to the instruction as an order tag. Is not limited to an order tag that takes an integer value, and may be an arbitrary code or the like. In this case, the order tag issuing unit 210
May simply be a tag issuing unit, and the logic for issuing the tag can be appropriately selected. For example, a tag uniquely corresponding to an operation code may be issued.

In the description of the above embodiment, the trace information collecting mechanism is set to the processor 11 that issues the in-order instruction.
Although the example in which it is mounted on 0 has been described, the present invention is similarly applicable to a processor that issues an out-of-order instruction. This is because the order tag issuing unit 210 assigns order tags to instructions in accordance with the instruction description order on the program, so that even if the subsequent processing differs from the instruction description order, there is no problem in collecting trace information.

[0118]

The first effect is that the operation history of the instruction execution pipeline and the presence / absence of a cache hit can be known from software. That is, the trace information that the user wants to know, such as the operation history of the instruction execution pipeline and the presence / absence of a cache hit, can be instructed by the software and left in the history. The reason is that a unique order tag is attached to the instruction to be executed, and a means for collecting the order tag of the instruction being executed from the functional unit and recording the same for each clock cycle is provided.

A second effect is that the history of the operation result of each instruction can be flexibly referred to from software. Therefore, for example, after executing a series of instruction sequences, it is possible to collectively check the validity of the execution status of each instruction. The reason for this effect is that there is provided a means for recording the history of the operation status using the order tag attached to the instruction as an address.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a processor including a trace information collecting mechanism according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating details of a writing unit in FIG. 1;

FIG. 3 is a diagram illustrating an operation of a writing unit in FIG. 2;

FIG. 4 is a diagram illustrating another operation of the writing unit in FIG. 2;

FIG. 5 is a diagram showing an example of a processor instruction related to use of the trace information collecting mechanism according to the embodiment.

FIG. 6 is a diagram showing a part of a program for explaining an operation of the trace information collecting mechanism according to the embodiment;

7 is a diagram showing the first half of the internal operation of the processor according to the program of FIG. 6;

8 is a diagram illustrating the latter half of the internal operation of the processor in the program of FIG. 6;

FIG. 9 is a diagram showing a result of trace information obtained by the program of FIG. 6;

FIG. 10 is a diagram showing a part of a program for explaining another operation of the trace information collecting mechanism according to the present embodiment.

11 is a diagram showing an internal operation of the processor according to the program of FIG. 10;

12 is a diagram showing a result of trace information obtained by the program of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 instruction memory 101 data memory 110 processor 150 instruction cache 151 instruction decoder 152 register file 153 reorder buffer 160 data cache 170 branch unit 171 operation unit 172 load unit 173 store unit 180 to 183 reservation station 210 order tag issue unit 211 write unit 212 cycle Counter 213 Trace memory 214 Reading unit 215 Trace information selecting unit 220-223 Order tag field

Claims (10)

[Claims] 1. A processor comprising an instruction decoder, each functional unit and a register file, wherein each time an instruction is decoded by the instruction decoder, a tag issuing unit for attaching a different tag to the instruction; The functional unit for notifying the generated tag, a cycle counter that is reset to an initial value determined when an initialization instruction is decoded by the instruction decoder and increases in value every clock cycle of the processor, and trace information. A trace memory for recording, a writing unit for writing a tag notified from the functional unit to the trace memory using a clock cycle value of the cycle counter as an address for each clock cycle of the processor, and a register file for storing contents of the trace memory. Transfer to register A trace information collecting mechanism, comprising: 2. A processor comprising an instruction decoder, each functional unit and a register file, wherein each time an instruction is decoded by the instruction decoder, a tag issuing unit for attaching a different tag to the instruction; A functional unit that notifies the execution status of the instruction and the instruction that has been executed, a trace memory that records trace information, and the trace memory that uses the tag that is notified of the execution status notified by the functional unit as an address. And a reading unit for transferring the contents of the trace memory to the register of the register file. 3. A processor comprising an instruction decoder, each functional unit, and a register file, wherein, when a trace information selection instruction is decoded by said instruction decoder, a trace information selection holding a trace mode specified by said trace information selection instruction. A tag issuing unit that attaches a different tag to the instruction each time the instruction is decoded by the instruction decoder; and the functional unit that notifies the tag attached to the processed instruction and the execution status of the instruction. A cycle counter that is reset to an initial value determined when the instruction decoder decodes the initialization instruction and increases in value every clock cycle of the processor; a trace memory that records trace information; The trace mode held in the The tag notified from the functional unit in the execution order trace information collection mode is written to the trace memory using the clock cycle value of the cycle counter as an address for each clock cycle of the processor, and is stored in the trace information selection unit. A writing unit that writes the execution status notified from the functional unit to the trace memory using the tag notified from the functional unit as an address when the trace mode is the instruction description order trace information collection mode, and the contents of the trace memory. And a reading unit for transferring the data to the register of the register file. 4. A processor including an instruction decoder, each functional unit and a register file, wherein the instruction decoder resets a trigger instruction of a trace information collecting operation to an initial value determined when the instruction is decoded, and resets the instruction by the instruction decoder. An order tag issuing unit that has an internal counter that increases each time it is decoded, and attaches the count value of the internal counter as an order tag to the instruction decoded by the instruction decoder, and is attached to the instruction that has been processed. A functional unit for notifying the sequence tag, and a cycle counter which is reset to an initial value determined when a trigger instruction of a trace information collecting operation is decoded by the instruction decoder and increases in value every clock cycle of the processor. Trace memory to record trace information, A writing unit that writes the order tag notified from the functional unit to the trace memory using the clock cycle value of the cycle counter as an address every clock cycle of the processor, and transfers the contents of the trace memory to the register of the register file A trace information collecting mechanism, comprising: 5. A processor comprising an instruction decoder, each functional unit, and a register file, wherein the instruction decoder resets a trigger instruction of a trace information collecting operation to an initial value determined when the instruction is decoded and resets the instruction by the instruction decoder. An order tag issuing unit that has an internal counter that increases each time it is decoded, and attaches the count value of the internal counter as an order tag to the instruction decoded by the instruction decoder, and is attached to the instruction that has been processed. A functional unit for notifying the execution order of the instruction and the execution status of the instruction; a trace memory for recording trace information; and the execution status notified from the functional unit, using the order tag notified from the functional unit as an address. A writing unit for writing to a memory; A reading unit for transferring the contents of the trace memory to the register of the register file. 6. A processor comprising an instruction decoder, each functional unit, and a register file, wherein a trace information selection instruction held by a trace information selection instruction when the instruction decoder decodes the trace information selection instruction. And an internal counter that is reset to an initial value determined when a trigger instruction of a trace information collecting operation is decoded by the instruction decoder and increases each time the instruction is decoded by the instruction decoder, An order tag issuing unit that attaches the count value of the internal counter as an order tag to the instruction decoded by the instruction decoder, and the functional unit that notifies the order tag attached to the processed instruction and the execution status of the instruction. Trace information by the instruction decoder A cycle counter, which is reset to an initial value determined when a trigger instruction of a sampling operation is decoded and increases in value every clock cycle of the processor, a trace memory for recording trace information, and held in the trace information selecting unit When the trace mode is the instruction execution order trace information collection mode, the sequence tag notified from the functional unit is written to the trace memory with the clock cycle value of the cycle counter as an address for each clock cycle of the processor, and When the trace mode held in the trace information selector is the instruction description order trace information collection mode, write the execution status notified from the functional unit into the trace memory using the order tag notified from the functional unit as an address. Department , Trace information collection mechanism, characterized in that it comprises a reading unit for transferring the contents of the trace memory into a register of the register file. 7. The trace memory is a set of memory cells addressed at a row position and a column position. The maximum number of bits of information to be recorded in one clock cycle is determined in the column direction, the longest clock cycle number to record a history. Or a capacity of a rectangular memory area having the longest instruction number in the row direction.
7. A trace information collecting mechanism according to claim 6. 8. The read unit can read the contents of a designated line of the trace memory and transfer the contents of the designated line to a register of the register file, and can read the contents of a designated column of the trace memory to read the contents of the register file. 7. The trace information collecting mechanism according to claim 1, wherein the trace information can be transferred to a register. 9. The method according to claim 1, wherein said instruction decoder resets the contents of said trace memory to an initial value according to a parameter when decoding a trace information selection instruction. Claim 5 or Claim 6
Trace information collection mechanism described. 10. The processor is a superscalar processor having a reservation station at the entrance of each functional unit, comprising a sequence tag field for storing a sequence tag attached to an instruction in the reservation station, wherein each functional unit performs processing. 7. The trace information collecting mechanism according to claim 1, wherein said write unit is notified of an order tag of said order tag field corresponding to the instruction which has been completed. .