JP2000209046A - Driver circuit for modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the output voltage of large amplitude by respectively connecting the gate and source of a first FET with a signal input and the source of a second FET, connecting the drain of the second FET with the source of a third FET and utilizing the drain of the third FET as a signal output terminal. SOLUTION: A driver circuit is provided with FETs 11-16, resistors 22-25 and a level shift circuit 31. The level shift circuit 31 is composed of serially connected two diodes. In the driver circuit, an electrode 1 is a signal input terminal and an electrode 7 is a signal output terminal. Prescribed constant voltage sources are respectively connected to electrodes 2-5. When integrating the driver circuit into an integrated circuit, respective electrodes 1-10 become simple nodes. Concerning the configuration of the driver circuit, the electrode 7 connected with the drain of the FET 13 as the output of a differential circuit is utilized as a terminal for extracting an output signal. The level shift circuit 31 is connected between the gate of the FET 12 and the electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator driver circuit which can be realized by an integrated circuit or the like, and more particularly to a modulator driver circuit suitable for applications requiring a large output amplitude in a high frequency range.

[0002]

2. Description of the Related Art An optical modulator used in an optical transmission system requires a large amplitude modulation drive voltage. For example, when optical transmission is performed at a transmission rate of 10 [Gbit / s] or more and a (LiNbO ₃ ) optical modulator is used, modulation with a large amplitude of about 3 [Vpp] to 4 [Vpp] is currently performed. A drive voltage is required.

[0003] As a modulation driver circuit of such an optical modulator, a single-end type, a differential type or the like can be considered. In any case, the output amplitude of the circuit (the amplitude of the modulation drive voltage) depends on the integrated circuit. It is limited by the withstand voltage of the constituent elements.
In particular, the higher the speed of the device, the lower the breakdown voltage, and it becomes difficult to obtain a large output amplitude. For example, see Reference 1 (Yoshida et al., “Low Power 10Gb / s EA Modulator Driver IC” C-10-1
6, 1998 IEICE Electronics Society Conference, pp. 63) shows a differential driver circuit as shown in FIG.

In this driver circuit, three FEs
T (field effect transistor) 111, 112 and 116
Is used. Two FETs 11 constituting a differential circuit
The electrode 101 connected to one of the gates 1 and 112 is used as a signal input. The electrode 150 connected to the gate of the other FET 112 is used as a negative-phase signal input. A reference voltage may be applied to the electrode 150 in some cases.

A predetermined constant voltage source is connected to each of the electrodes 102, 103, 104 and 105. The output signal is extracted from the electrodes 106 and 151. FET1
The drain-gate voltage (Vdg) of the electrode 12 is
When the input signal applied to 1 is at a high level, it becomes maximum, and at that time, a voltage having an output amplitude or more appears as Vdg. In the case of high-speed operation, the withstand voltage of the element is reduced. Therefore, if the voltage Vdg is suppressed to be equal to or lower than the withstand voltage of the FET 112, there is a problem that a large output amplitude cannot be obtained.

For example, reference 2 (GWHaines and R. Renes)
i, “An integrated high-swing video amplifier” Int.
Solid State Ckts. Conf., Digest Tech. Papers, 196
9, pp. 94-95.) Shows a driver circuit as shown in FIG. In this driver circuit, bipolar transistors 211 and 212 are used as amplification elements. Further, a circuit for reducing a voltage applied to the transistor 212 is included.

The transistor 213 includes the transistor 21
2 in cascade. Also, the resistors 221 and 221
22 and 223, and a resistor 22
A voltage divider composed of 4,225 is provided in the feedback circuit,
In each voltage dividing circuit, transistors 212, 213, 214, 2
15 are generated. Thus, the collector-base voltage (Vcb) of the transistor 212 is reduced as described below.

The electrodes 205, 206, 207, 2 of FIG.
08, 209 and 210 are set to Vs, Vout,
Assuming that VA, VC, VB and VD, and the resistance values of the resistors 221, 222 and 223 are R1, R2 and R3, the potentials of VA, VB, VC and VD are respectively expressed as follows. VA = Vout + Vbe (1) (1) VB = (R3 · Vs + (R1 + R2) Vout) / (R1 + R2 + R3) (2) VC = VB−Vbe (2) (3) VD = ( (R2 + R3) Vs + R1.Vout) / (R1 + R2 + R3) (4) Here, Vbe (1) and Vbe (2) represent the base-emitter voltages of the transistors 214 and 213, respectively.

If the collector-base voltages of the transistors 212 and 213 are Vcb (3) and Vcb (4), respectively, Vcb (3) and Vcb (4) are expressed as follows. Vcb (3) = VC-VD = R2 (Vout-Vs) / (R1 + R2 + R3) -Vbe (2) (5) Vcb (4) = VA-VB = R3 (Vout-Vs) / (R1 + R2 + R3) + Vbe (1) ... (6) According to the above formulas (5) and (6), the transistor 212
And the voltage between the collector and the base of the transistor 213 can be selected by appropriately selecting the resistance value of the voltage dividing circuit.
Can be reduced to 以下 or less as compared with the case where no is connected.

[0010]

If the bipolar transistors 211 to 215 in the circuit shown in FIG. 15 are replaced with FETs, a driver circuit can be formed as shown in FIG. Further, each FE of the driver circuit shown in FIG.
If circuits are integrated using high-frequency elements typified by (InPHEMT) as T111 to T116, a high-speed modulator driver circuit can be realized.

However, as shown in FIG.
It has been found by simulation analysis that a problem described below arises when a driver circuit is configured by using. The graph of FIG. 13 shows (InPH) as each of the FETs 111 to 116 of the driver circuit shown in FIG.
Input voltage when using EMT) (voltage of electrode 101)
The figure shows the result obtained by simulation of the relationship between the voltage and the voltage of each node. 13, the voltages at the nodes of the electrodes 106 to 110 in FIG. 12 are indicated by V6 to V10, respectively.

In this simulation, the following conditions are assumed. Regarding the main characteristics of the (InPHEMT) element, the threshold value is about -650 [mV], the transconductance is about 1.2 [mS / mm], and the fT
Is about 130 [GHz] and fMAX is about 300 [GHz]. The allowable value of the drain-gate voltage of the FET is about 2.6 V or less.

The electrodes 102, 103, 104 and 1
05 are -5.1, respectively.
[V], -2 [V], 0 [V], and -5.2 [V]. In this simulation, the voltage V1 of the input signal is given in a range from -2 [V] to -5 [V].
Considering the drain-gate breakdown voltage of the FET 111,
The actual input signal voltage is limited to -4.6 [V].

For example, when the input voltage range is from -4.5 [V] to
When it is determined to be −3 [V], the drain-gate voltage of the FET 112 becomes 2.2 V or less. In the example of FIG. 13, the maximum amplitude of the output node voltage V6 is about 2.8 [Vpp].
It is difficult to obtain an amplitude of 3 [Vpp] or more. This is for the following reasons. The gate potential dependency of the gate-source voltage of the FET 114 is larger than the base potential dependency of the base-emitter voltage of the bipolar transistor. Therefore, as is clear from FIG. 13, the voltage change of the output node voltage V6 is smaller than the change of the differential output node voltage V7. Therefore, the amplitude obtained by the differential circuit of FIG. 12 is smaller than that of the differential circuit of FIG.

Further, since negative feedback is applied to the gate potential of the FET 112, the voltage change of the differential output node voltage V7 is suppressed as compared with the voltage change of the input voltage V1. Therefore, the amplitude obtained from the output node voltage V6 is smaller than the amplitude obtained from a general differential circuit. That is, FIG.
When the driver circuit is configured as shown in FIG.
11, 112, 113) can be greatly reduced, but at the expense of obtaining a large amplitude, which is the original purpose, with the disadvantage that a sufficient amplitude cannot be obtained. Occurs.

The output waveform of the driver IC shown in FIG. 3 of Document 1 shows an eye opening when operated at a speed of 10 [Gbit / s]. Judging from this waveform shape, it is considered that the operation as expected in the present invention is impossible at a higher operation speed of 40 [Gbit / s].
An object of the present invention is to reduce the voltage applied to each element and obtain an output voltage having a large amplitude in the modulator driver circuit as described above.

[0017]

According to a first aspect of the present invention, there is provided a modulator driver circuit comprising a first FET, a second FET, and a third FE.
T, fourth FET, fifth FET, sixth FET, first FET
, A second resistor, a third resistor, a fourth resistor, and a conductive element, and a first electrode, a second electrode, a third electrode, and a fourth electrode each connected to a predetermined voltage source. And an electrode,
A high potential side terminal of the conductive element is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor, and a gate of the first FET, A drain and a source connected to the signal input, the first electrode, and the source of the second FET, respectively,
Is connected to the source of the third FET, the low potential side terminal of the conductive element is connected to the second electrode, and the gate of the third FET is connected to the other end of the first resistor and The third FE connected to one end of the second resistor;
The drain of T is connected to the gate of the fourth FET and the third FET.
And the source and the drain of the fourth FET are connected to the other end of the second resistor and the source of the fifth FET, respectively, and the gate of the fifth FET is connected to the 3 is connected to the other end of the resistor and one end of the fourth resistor, and the drain of the fifth FET is connected to the third resistor.
The other end of the fourth resistor is connected to the third electrode, and the drain of the sixth FET is connected to the source of the first FET and the source of the second FET. A modulator driver circuit in which a gate and a source of the sixth FET are connected to the fourth electrode and the second electrode, respectively, wherein a drain of the third FET is used as a signal output terminal It is characterized by the following.

That is, in the driver circuit as shown in FIG. 12, the signal output is directly extracted from the output of the differential circuit. As a result, a larger output amplitude is obtained as described later. Claim 2
In the modulator driver circuit according to claim 1, the conductive element is configured by a plurality of diodes connected in series,
The high potential side anode of the diode is connected to one end of the first resistor, and the low potential side cathode of the diode is connected to the second electrode.

Compared with the change in the current flowing through the diode,
The change in the forward terminal voltage is very small. Therefore,
By using a diode instead of a resistor as the conductive element, the amount of feedback fed back from the output to the input (gate) of the second FET is reduced, and a decrease in the level difference between the differential inputs is prevented. As a result, the allowable range of the output voltage change becomes large.

According to a third aspect of the present invention, in the modulator driver circuit according to the first aspect, a level shift circuit comprising a plurality of diodes connected in series is connected to the third electrode and the first electrode.
Connected between the drain of the first FET and the first FET
Is characterized in that the potential of the drain is lower than the potential of the third electrode. By using the level shift circuit, a voltage to be applied to the drain of the first FET can be generated from the voltage of the third electrode, so that the number of necessary voltage sources can be reduced. Further, since the level shift circuit is used, the potential of the drain of the first FET is lower than the potential of the third electrode.

Therefore, it is effective to suppress the drain-gate voltage of the first FET within its breakdown voltage. Further, since the level shift circuit is formed using the diodes, the change in the drain voltage becomes very small with respect to the change in the current flowing through the first FET. Claim 4
According to a third aspect of the present invention, in the modulator driver circuit according to the third aspect, a bypass capacitor connected in parallel with the level shift circuit is provided.

Since the high frequency signal component bypasses the level shift circuit by connecting the bypass capacitor, it is effective in suppressing the fluctuation of the drain voltage of the first FET in the high frequency region. According to a fifth aspect, in the modulator driver circuit according to any one of the first, second, third, and fourth aspects, the gate of the second FET is connected to a high potential side terminal of the conductive element and the first FET. And one end of the resistor.

Since the potential of the gate of the second FET is substantially constant, an output signal corresponding to the input signal applied to the gate of the first FET can be obtained. According to a sixth aspect of the present invention, in the modulator driver circuit according to any one of the first, second, third, and fourth aspects, the gate of the second FET is connected to a negative-phase signal input. .

A differential signal can be input between the signal input and the negative-phase signal input. As a result, an output signal having a larger amplitude can be obtained. According to a seventh aspect of the present invention, in the modulator driver circuit according to the first aspect, an input matching circuit, at least one source follower circuit, and at least one full feedback type differential circuit are connected to the gate of the first FET and the gate of the second FET. An input circuit constituted by a dynamic circuit is connected.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An example of a driver circuit for implementing a modulator driver circuit of the present invention will be described with reference to FIGS. This form
It corresponds to claim 1, claim 2 and claim 5.

FIG. 1 is a block diagram showing the configuration of a modulator driver circuit according to this embodiment. FIG. 2 is a graph showing the relationship between the input voltage of the circuit of FIG. 1 and each node voltage. In this embodiment, the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FE according to claim 1 are described.
T, the first resistor, the second resistor, the third resistor, the fourth resistor, the conductive element, the signal input, the first electrode, the second electrode, the third electrode, and the fourth electrode are respectively FET11, FE
T12, FET13, FET14, FET15, FET
16, the resistor 22, the resistor 23, the resistor 24, the resistor 25, the level shift circuit 31, the electrode 1, the electrode 3, the electrode 5, the electrode 4, and the electrode 2.

The driver circuit shown in FIG.
16, a resistor 22 to 25 and a level shift circuit 31. The level shift circuit 31 includes two serially connected
It consists of two diodes. In the driver circuit shown in FIG. 1, the electrode 1 is a signal input terminal and the electrode 7
Is a signal output terminal. A predetermined constant voltage source is connected to each of the electrodes 2 to 5.

When this driver circuit is incorporated in an integrated circuit, each of the electrodes 1 to 10 is simply a connection point, that is, a node. The configuration of the driver circuit of FIG. 1 is very similar to the circuit of FIG. 12 already described, but the configuration of the following points is changed. (A) FE which is the output of the differential circuit
The electrode 7 connected to the drain of T13 is used as a terminal for extracting an output signal. (B) Resistance 121
Instead, a level shift circuit 31 composed of a plurality of diodes is connected between the gate of the FET 12 and the electrode 5.

FIG. 2 is a graph showing the relationship between the input voltage (the voltage V1 of the electrode 1) and the voltages V6 to V10 of each node when (InPHEMT) is used as each of the FETs 11 to 16 of the driver circuit shown in FIG. The result obtained by simulation is shown. In FIG. 2, the electrodes 6 to 6 of FIG.
10 at V6 to V
Indicated at 10.

In this simulation, the following conditions are assumed. As for the main characteristics of the (InPHEMT) element, the threshold value is about -650 [mV], the transconductance is about 1.2 [mS / mm], and the fT
Is about 130 [GHz] and fMAX is about 300 [GHz]. The allowable value of the drain-gate voltage of the FET is about 2.6 V or less.

The voltage values of the voltage sources connected to the electrodes 2, 3, 4 and 5 are. -5.1 [V], -2 respectively
[V], 0 [V], and -5.2 [V]. In this simulation, the voltage V1 of the input signal is given in the range of -2 [V] to -5 [V], but in consideration of the drain-gate breakdown voltage of the FET 11, the actual voltage of the input signal is -4. It is limited to 0.6 [V].

Referring to FIG. 2, when the change range of the input voltage V1 is -4.5 [V] to -3 [V], the drain-gate voltage (potential difference between V8 and V10) of the FET 12 is 2.2V. This is the same as the case of the driver circuit of FIG. On the other hand, the output of the driver circuit of FIG. 1 is a node voltage V7 extracted from the electrode 7. When the change range of the input voltage V1 is -4.5 [V] to -3 [V],
The maximum amplitude of the node voltage V7 is about 3.5 [Vpp]. This amplitude corresponds to the output of the driver circuit of FIG.
V6) is increased by 0.7 [V].

That is, by changing the configurations (a) and (b), a large increase in output amplitude can be expected without increasing the drain-gate voltage of the FET 12. The reason will be described below. In the driver circuit shown in FIG. 1, when the node voltages of the electrodes 6 and 7 are V6 and V7, respectively, and the gate-source voltage of the FET 14 is Vgs, the node voltage V6 becomes (V7-Vgs).

Here, when the node voltage V7 increases in the direction of the high level corresponding to the input voltage V1, the node voltage V7 increases.
6, the current flowing through the FET 14 increases, and the voltage Vgs increases accordingly. Therefore, the node voltage V6 does not rise as much as the node voltage V7 due to the increase in the voltage Vgs. Conversely, when the node voltage V7 decreases toward the low level, the node voltage V6 decreases and the current flowing through the FET 14 decreases, and accordingly, the voltage Vgs decreases. Therefore, the node voltage V6 does not decrease as much as the node voltage V7 due to the decrease in the voltage Vgs.

As described above, the change in the node voltage V6 is smaller than the change in the node voltage V7. This is clear from the graph of FIG. Therefore, a larger output is obtained when the output signal is directly taken out from the drain of the FET 13 which is the output of the differential circuit as in the driver circuit shown in FIG. The amplitude is obtained.

In the differential circuit, an output is obtained according to the level difference between the differential inputs (between the gate of the FET 11 and the gate of the FET 12). Therefore, the larger the level difference, the larger the output amplitude. Become. However, in the case of the driver circuit shown in FIG. 12, the influence of a change in the voltage between the terminals of the resistor 121 appears on the gate of the FET 12 on the opposite phase input side of the differential circuit. Positive feedback is applied. That is, as can be seen from the relationship between the input voltage V1 and the node voltage V10 in FIG. 13, the node voltage V10 increases with an increase in the input voltage V1, and acts in a direction to reduce the level difference between the differential inputs.

On the other hand, in the driver circuit shown in FIG. 1, a level shift circuit 31 using a diode instead of the resistor 121 is provided. The current flowing through the diode is represented by an exponential function of the applied voltage, and the forward voltage change of the diode is smaller than the current change. Therefore, a voltage change at the gate of the FET 12 is suppressed, and the influence of the voltage change due to feedback is reduced.

Therefore, it is possible to suppress the level difference between the inputs of the differential circuit from decreasing due to the feedback effect. For example, FIG.
The change in the node voltage V10 shown in FIG. 13 is smaller than the change in the node voltage V10 shown in FIG. (Second Embodiment) An example of a driver circuit for implementing the modulator driver circuit of the present invention will be described with reference to FIGS. This mode is defined in claims 1 and 6
Corresponding to

FIG. 3 is a block diagram showing the configuration of the modulator driver circuit of this embodiment. FIG. 4 is a graph showing the relationship between the input voltage of the circuit of FIG. 3 and each node voltage. This embodiment is a modification of the first embodiment. 3, elements corresponding to those in FIG. 1 are denoted by the same reference numerals. The changed part will be described below.

In the driver circuit shown in FIG.
The gate of T12 is separated from the electrode 10 and connected to the electrode 50. In this embodiment, an input signal is applied between the electrode 1 that is a positive-phase input and the electrode 50 that is a negative-phase input.
In the driver circuit shown in FIG. 3, a resistor 21 is provided instead of the level shift circuit 31 shown in FIG. FIG. 4 shows the result of a simulation performed on the driver circuit of FIG. The simulation conditions are the same as those in the first embodiment, and the electrodes 6 to 1 in FIG.
The voltage at each of the nodes 0 and 50 is V
6 to V10 and V50.

Referring to FIG. 4, when the change range of the input voltage V1 is -4 [V] to -3 [V], the drain-gate voltage of the FET 12 becomes 2.4 V or less. The maximum amplitude of the node voltage V7 obtained as an output is 2.8.
[Vpp], which is larger than the node voltage V6. That is, by extracting an output signal from the electrode 7, an amplitude larger than that of the driver circuit of FIG. 12 can be obtained.

When FIG. 2 and FIG. 4 are compared, in FIG. 4, a large change of about 2.8 [V] is obtained in the output node voltage V7 due to the change of the input voltage V1 in a relatively small range. This is because the driver circuit of FIG. 3 uses both inputs of the electrode 1 and the electrode 50, and is a general characteristic of a differential circuit. However, such characteristics are obtained only when the operation of the differential circuit is within the linear operation range.

(Third Embodiment) An example of a driver circuit for implementing the modulator driver circuit of the present invention will be described with reference to FIGS. This embodiment corresponds to claims 1, 2 and 6. FIG. 5 is a block diagram showing the configuration of the modulator driver circuit of this embodiment. FIG. 6 is a graph showing the relationship between the input voltage of the circuit of FIG. 5 and each node voltage. This embodiment is a modification of the second embodiment, in which the resistor 21 in FIG. 3 is replaced by the level shift circuit 31 in FIG. For other configurations,
It is the same as FIG.

FIG. 6 shows the result of a simulation performed on the driver circuit shown in FIG. The simulation conditions are the same as those in the first embodiment, and the voltages at the nodes of the electrodes 6 to 10 and 50 in FIG. 5 are indicated by V6 to V10 and V50, respectively. Referring to FIG. 6, the change range of the input voltage V1 is-
In the case of 4 [V] to -3 [V], the drain of the FET 12
The gate-to-gate voltage becomes 2.4 V or less. The maximum amplitude of the node voltage V7 obtained as an output is about 3 [Vpp], which is improved as compared with the driver circuit of FIG.

When the result of FIG. 6 is compared with FIG.
2 drain-gate voltage (V8 and V10 or V50
Is increased by about 0.2 V, but is maintained within the breakdown voltage range. Further, an output amplitude of 3 [Vpp] is obtained with the input voltage V1 having a small amplitude of 1 [Vpp]. (Fourth Embodiment) An example of a driver circuit for implementing the modulator driver circuit of the present invention will be described with reference to FIG. This form is claimed in claim 1, claim 2, claim 3
And claim 5. FIG. 7 is a block diagram showing the configuration of the modulator driver circuit of this embodiment.

In this embodiment, the level shift circuit of claim 3 corresponds to the level shift circuit 32. The driver circuit of FIG. 7 is a modified example of the driver circuit of FIG. 3 and the following points are changed. That is, the level shift circuit 32 composed of three diodes is connected between the electrode 4 and the drain of the FET 11.

In this embodiment, the voltage to be applied to the electrode 3 is generated based on the voltage applied to the electrode 4 by the level shift circuit 32. Therefore, compared to the driver circuit of FIG. The number can be reduced by one. That is, the voltage from one voltage source connected to the electrode 4 is
ET11 and FET12 can be used in common. The level shift circuit 32 applies a voltage lower than the voltage applied to the electrode 4 to the drain of the FET 11. As a result, the voltage between the gate and the drain of the FET 11 is suppressed, which is effective in maintaining the voltage within the breakdown voltage. Since the change in the forward voltage of the diode is smaller than the change in the current flowing therethrough, the change in the drain voltage of the FET 11 is smaller than the change in the input voltage V1 applied to the electrode 1. Therefore, the same operation as the driver circuits shown in FIGS. 1 and 3 is realized also in the driver circuit of FIG.

The influence of the drain voltage fluctuation of the FET 11 in the high frequency region can be reduced by connecting a bypass capacitor in parallel with the level shift circuit 32. (Fifth Embodiment) An example of a driver circuit for implementing the modulator driver circuit of the present invention will be described with reference to FIGS. This form is defined in claims 1 to 4,
This corresponds to claims 6 and 7.

FIG. 8 is a block diagram showing the configuration of the modulator driver circuit of this embodiment. FIG. 9 is a block diagram showing a configuration example of the entire modulator driver circuit. FIG. 10 is a time chart showing the output response waveform of the circuit of FIG.
FIG. 11 is an electric circuit diagram showing the details of the circuit components of FIG. The driver circuit in FIG. 8 is a modification of the driver circuit in FIG. 7, and differs from FIG. 7 in that the gate of the FET 12 is separated from the electrode 10 and connected to the electrode 50.
In the driver circuit of FIG. 8, a bypass capacitor 35 is connected in parallel with the level shift circuit 32. The bypass capacitor 35 is an FET in a high frequency region.
11 is effective in suppressing the fluctuation of the drain voltage.
8, elements corresponding to those in FIG. 7 are denoted by the same reference numerals.

The driver circuit for the modulator shown in FIG.
And a circuit is further added to the input side of the driver circuit shown in FIG. 1 and specifically designed on the assumption that the driver circuit operates at a transmission speed of 40 Gbit / s. That is, the driver circuit 70 of FIG. 8 is connected to the final driver stage of the modulator driver circuit of FIG. The modulator driver circuit of FIG. 9 includes an input matching circuit 61 and three source follower circuits 62 (1), 62 (2), and 62 in addition to the driver circuit 70.
(3) and two full feedback type differential circuits 63 (1) and 63 (2).

Input matching circuit 61, source follower circuit 62
The details of the differential circuit 63 of the full feedback type are shown in FIG. The three source follower circuits 62 (1), 62 (2), and 6 shown in FIG.
2 (3) have the same configuration, and the two full feedback differential circuits 63 (1) and 63 (2) in FIG. 9 have the same configuration. In the modulator driver circuit of FIG. 9, the outputs O1 and O2 of the input matching circuit 61 are connected to the source follower circuit 62 (1).
And the outputs O1 and O2 of the source follower circuit 62 (1) are
The outputs O1 and O2 of the differential circuit 63 (1) of the full feedback type are connected to the inputs I1 and I2 of the source follower circuit 62 (2), respectively. 2) are connected to the inputs I1 and I2 of the full feedback differential circuit 63 (2), respectively, and the outputs O1 and O2 of the full feedback differential circuit 63 (2) are connected to the source follower circuit 62 ( 3) are connected to inputs I1 and I2, respectively, and outputs O1 and O2 of source follower circuit 62 (3) are connected to electrodes 1 and 50, respectively.

The inputs I1 and I2 of the input matching circuit 61
Are connected to the terminals 81 and 82, respectively. Terminal 81
Is used as a signal input terminal, and the terminal 82 is used as a negative-phase signal input terminal. A constant voltage applied to the terminal 83 is applied to the input matching circuit 61 and the source follower circuit 62.
(1), 62 (2), 62 (3), all feedback type differential circuit 63 (1),
63 (2) is applied to each terminal Vcs and the electrode 2 of the driver circuit 70.

Similarly, a constant voltage applied to terminal 84 is applied to input matching circuit 61, source follower circuits 62 (1),
2 (2), 62 (3), full feedback type differential circuit 63 (1), 63 (2)
Are applied to each terminal Vss and the electrode 5 of the driver circuit 70. Further, a constant voltage applied to the terminal 85 is applied to the input matching circuit 61, the source follower circuits 62 (1), 62 (2),
62 (3), the terminal VDD of each of the differential circuits 63 (1) and 63 (2) of the full feedback type and the electrode 4 of the driver circuit 70.

FIG. 10 shows a result obtained by examining the response characteristics of the modulator driver circuit of FIG. 9 by simulation. In this example, 40 [Gbit / s] corresponding to 7 stages of PN
NRZ signal was input to a terminal 81, a predetermined reference voltage was applied to a terminal 82, and a response waveform of an output signal obtained at an electrode 7 of a driver circuit 70 was obtained by simulation. Terminal 8
The amplitude of the signal input to 1 is 0.9 [Vpp]. Referring to FIG. 10, it can be seen that an output amplitude of about 3 [Vpp] is obtained at the eye opening.

[0055]

As described above, according to the present invention, a larger output amplitude can be obtained by extracting an output signal directly from the output of the differential circuit. In addition, since the conductive element used in the feedback circuit is composed of a plurality of diodes connected in series, the feedback effect is alleviated. Therefore, the voltage of 3 Vpp or more can be obtained without excessively increasing the drain-gate voltage of the FET. A large output amplitude is obtained.

Therefore, a modulator driver circuit can be constructed using a high-frequency element having a small drain-gate voltage, and a high-speed region (for example, a transmission speed of 40 [Gbit / s])
However, a usable modulator driver circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a modulator driver circuit according to a first embodiment.

FIG. 2 is a graph showing a relationship between an input voltage of the circuit of FIG. 1 and each node voltage.

FIG. 3 is a block diagram illustrating a configuration of a modulator driver circuit according to a second embodiment.

FIG. 4 is a graph showing a relationship between an input voltage of the circuit of FIG. 3 and each node voltage.

FIG. 5 is a block diagram illustrating a configuration of a modulator driver circuit according to a third embodiment.

FIG. 6 is a graph showing a relationship between an input voltage of the circuit of FIG. 5 and each node voltage.

FIG. 7 is a block diagram illustrating a configuration of a modulator driver circuit according to a fourth embodiment.

FIG. 8 is a block diagram illustrating a configuration of a modulator driver circuit according to a fifth embodiment.

FIG. 9 is a block diagram illustrating a configuration example of an entire modulator driver circuit.

FIG. 10 is a time chart showing an output response waveform of the circuit of FIG. 9;

FIG. 11 is an electric circuit diagram showing the details of each circuit in FIG. 9;

12 is an electric circuit diagram showing a driver circuit in which each transistor of FIG. 15 is replaced by an FET.

FIG. 13 is a graph showing a relationship between an input voltage of the circuit of FIG. 12 and each node voltage.

FIG. 14 is an electric circuit diagram showing a driver circuit of a conventional example (1).

FIG. 15 is an electric circuit diagram showing a driver circuit of a conventional example (2).

[Explanation of symbols]

1,2,3,4,5,6,7,8,9,10,50 electrode 11,12,13,14,15,16 FET 21,22,23,24,25 resistance 31,32 level shift circuit 35 bypass capacitor 61 input matching circuit 62 source follower circuit 63 differential circuit of full feedback type 70 driver circuit 81 to 85 terminal V1 input voltage V6, V7, V8, V9, V10, V50 node voltage

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/06 F term (Reference) 5J066 AA01 AA12 CA32 CA62 FA20 HA02 HA09 HA19 HA25 HA29 KA00 KA18 KA29 KA53 MA02 MA08 MA13 ND01 ND11 ND22 ND23 PD01 SA00 TA02 TA06 5J092 AA01 AA12 CA32 CA62 FA20 HA02 HA09 HA19 HA25 HA29 KA00 KA18 KA29 KA53 MA02 MA08 MA13 SA00 TA02 TA06 5K002 AA02 CA03 CA14

Claims (7)

[Claims] 1. A first FET, a second FET, and a third F
ET, a fourth FET, a fifth FET, a sixth FET, a first resistor, a second resistor, a third resistor, a fourth resistor, and a conductive element, each of which is connected to a predetermined voltage source. A first electrode, a second electrode, a third electrode, and a fourth electrode, wherein a high-potential side terminal of the conductive element is connected to one end of the first resistor; Is connected to one end of the second resistor, and the gate, drain and source of the first FET are connected to a signal input, the first electrode and the source of the second FET, respectively. The drain of the second FET is connected to the source of the third FET, the low potential side terminal of the conductive element is connected to the second electrode, and the gate of the third FET is connected to the first resistor. And the drain of the third FET is connected to one end of the second resistor and one end of the second resistor. Is connected to the gate of the fourth FET and one end of the third resistor, and the source and drain of the fourth FET are connected to the other end of the second resistor and the source of the fifth FET, respectively. Connected, the gate of the fifth FET is connected to the other end of the third resistor and one end of the fourth resistor, the drain of the fifth FET is connected to the third electrode, 4, the other end of the resistor is connected to the third electrode, the drain of the sixth FET is connected to the source of the first FET and the source of the second FET, and the gate of the sixth FET And a source, respectively, a modulator driver circuit connected to the fourth electrode and the second electrode, respectively, wherein a drain of the third FET is used as a signal output terminal. circuit. 2. The modulator driver circuit according to claim 1, wherein said conductive element is constituted by a plurality of diodes connected in series, and an anode on a high potential side of said diode is connected to one end of said first resistor. A driver circuit for a modulator, wherein a cathode on a low potential side of the diode is connected to the second electrode. 3. The modulator driver circuit according to claim 1, wherein a level shift circuit composed of a plurality of diodes connected in series is connected between said third electrode and a drain of said first FET. A driver circuit for a modulator, wherein the potential of the drain of the first FET is lower than the potential of the third electrode. 4. The modulator driver circuit according to claim 3, further comprising a bypass capacitor connected in parallel with said level shift circuit. 5. The modulator driver circuit according to claim 1, wherein a gate of said second FET is connected to a high potential side terminal of said conductive element and said first FET. A driver circuit for a modulator, wherein the driver circuit is connected to one end of a resistor. 6. The modulator driver circuit according to claim 1, wherein a gate of said second FET is connected to a negative-phase signal input. Modulator driver circuit. 7. The modulator driver circuit according to claim 1, wherein an input matching circuit, at least one source follower circuit, and at least one full feedback type differential circuit are connected to the gate of the first FET and the gate of the second FET. A driver circuit for a modulator, wherein an input circuit constituted by a dynamic circuit is connected.