JP2000208751A - Image sensor with electronic shutter function - Google Patents

Abstract

(57) [Summary] [Objective] To improve an image sensor having an electronic shutter function. The image sensor includes a plurality of pixels each having a control switch connected to one terminal of the optical storage cell and a reset switch connected to the other of the optical storage cell. Each pixel of the image sensor senses light to generate a charge and stores an induced charge corresponding to the generated charge by controlling both switches to obtain an electronic shutter effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor, and more particularly, to an image sensor having an electronic shutter function without using a charge-coupled device (CCD).

[0002]

2. Description of the Related Art At present, there are two types of image sensors, a CCD image sensor and a MOS image sensor.

In a CCD image sensor having a plurality of pixels, the charge generated by the light sensing of each pixel is CC
D and stored, and the stored charge is then transferred to CC
It is output one after another from the terminal of D. When the charges contained in each pixel are simultaneously transferred to the CCD, an effect as an electronic shutter is achieved, and as a result, an appropriate signal is obtained at an appropriate time.

A MOS image sensor does not use a CCD. Referring to FIG. 1, which shows a 4 × 3 image sensor array, the array has four word lines (word li).
nes) 93, three bit lines 94,
A horizontal scanning circuit 95, a vertical scanning circuit 96, and an intersection circuit 9;
7 and an output terminal 98. Each pixel includes a photosensitive diode 91 as a light receiving element and a control transistor 9
2 is included. Each word line 93 has three words in one row.
Connected to one pixel 90. Each bit line 94
Are connected to four pixels 90 in one column. The horizontal scanning circuit 95 and the vertical scanning circuit 96 scan the photosensitive diodes 91 one after another. The photosensitive diode 91 of each pixel 90 senses light to generate an induced charge, which is provided to one of the corresponding bit lines 94. The electric charge induced in each pixel is output to an output terminal 98.
, Are sequentially transferred to an external circuit (not shown), whereby the electric charges are converted into image signals.

[0005] MOS image sensors are easy to manufacture, have the advantage of low power consumption and low cost, but do not function as electronic shutters as do CCD image sensors.

The control transistor 92 of each pixel 90 transfers a charge from the photosensitive diode 91 to the corresponding bit line 9.
Transfer to 4. The control transistor 92 does not store charge. While the control transistor 92 of each pixel 90 is on, while other pixels continue to sense changes in external light,
The control transistor 92 transfers the charge of the photosensitive diode 91. Thus, when an accurate image is to be obtained, the pixels 90 should sense light one after another and the induced charge in each pixel should be read out one after another, so that light is sensed by each pixel. The period will be the same.

[0007]

Therefore, MOS image sensor arrays can only be applied to slowly changing or still images, such as those of surveillance cameras. That is, ordinary MOS image sensor arrays are not suitable for dynamic or fast-changing images.

An object of the present invention is to provide an improved image sensor having an electronic shutter function.

It is another object of the present invention to provide an image sensor having a simple configuration without using a CCD.

[0010]

According to a first aspect of the present invention, an image sensor includes a plurality of pixels. Each pixel has a control switch connected to the optical storage cell and a reset switch connected to the optical storage cell. Both switches of each pixel are controlled to induce charge and store the induced charge. Therefore, the image sensor can obtain an electronic shutter effect.

According to a second aspect of the present invention, an optical storage cell of each pixel of an image sensor includes an upper layer acting as an electrode plate and a silicon lower layer.

According to a third aspect of the present invention, the electrode plate layer of the optical storage cell is connected to the bit line via an extraction holding switch, while the silicon layer is connected to a reference power supply via a reset switch. Connected to. The operation of the optical storage cell is as follows: the optical storage cell resets, senses light, stores charge,
And the output of the electric charge is controlled by both switches so as to perform the operations one after another.

According to a fourth aspect of the present invention, the optical storage cell of each pixel of the image sensor is a MOS transistor having a transparent gate.

According to a fifth aspect of the invention, the optical storage cell is an NMOS or PMOS transistor having a transparent gate.

According to a sixth aspect of the present invention, an optical storage cell includes a photosensitive diode and a capacitor connected in series with each other.

According to a sixth aspect of the present invention, an optical storage cell includes a photosensitive diode and another diode connected in series with each other.

[0017] Other objects, advantages and novel features of the present invention will become apparent from the following description with reference to the accompanying drawings.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an image sensor according to the present invention comprises a pixel array arranged in rows and columns, a plurality of word lines each connected to a plurality of pixels in a column, and It includes a plurality of bit lines connected to a plurality of pixels in a row, a horizontal scanning circuit, and a vertical scanning circuit for scanning the pixels, and is similar to that of the ordinary MOS image sensor array shown in FIG. However, the pixels of an image sensor according to the present invention are quite different from the pixels of a conventional image sensor array.

Referring to FIG. 2A, the pixels used in the image sensor according to the present invention include an optical storage cell or optical storage cell 10 and a sample-and-hold switch SH as a control switch. And a reset switch RST.

The optical storage cell 10 includes an upper layer 11 serving as an electrode plate and a lower layer 12 made of silicon. The upper layer 11 and the lower layer 12 are separated from each other by an appropriate space. The upper layer 11 is made of a conductive material, preferably a transparent conductive material.

[0021] external light is incident on the lower layer 12, the lower layer 12 generates a negative charge e ^over senses the light. The lower layer 12 receives the reference voltage V through a reset switch RST.
1 terminal. The lower layer 12 includes a bit line B.I. L. Pixel operations such as reset, sensing, charge accumulation, and charge output can be performed continuously by controlling the on / off of the switches SH, RST.

FIG. 2B shows two switches SH and RS.
The operation of T is shown.

At time t1, when the two switches SH and RST are closed (high level), the voltage V
2 is the bit line B. L. Therefore,
The two terminals of the optical storage cell 10 have voltages V2 and V1, respectively.
, Whereby the optical storage cell 10 is reset.

After the discharge, at time t2, the reset switch RST is opened, whereby the lower layer 2 of the optical storage cell 10 floats. Lower layer 12 lifted generates photoelectrons e ^over senses the light. Meanwhile, the upper layer positive charges corresponding to photoelectrons (negative charge) e ^over the lower layer 12 11
Is induced. This step is called "frame integration (frame i
ntegration).

At time t3, the reset switch R
ST is connected to the reference voltage V1, and the extraction hold switch SH
Are released, and the upper layer 11 rises. Thereby,
The induced positive charges are stored in the upper layer 11.

Finally, at time t4, the extraction holding switch SH is closed, and the stored positive charges are transferred to the bit line B.B. Output to L.

At time t3, positive charges corresponding to photoelectrons in the lower layer 12 are stored in the upper layer 11 by electrostatic coupling. In addition, lower layer 12 is coupled to reference voltage V1. Therefore, even if external light continuously enters the lower layer 12, additional photoelectrons are absorbed by the reference voltage V1. That is, the lower layer 12 is turned off so that it no longer stores charge. Therefore, the oversensing phenomenon is avoided.

The sensing period is determined by the symbol Δt in FIG. The optical storage cell 10 senses light only during the period Δt, but is turned off in which no electric charge is stored in all other periods. Since the induced charges are stored in the upper layer 11, the charges do not escape. Thus, an electronic shutter function is provided by the structure.

In another embodiment of the present invention, optical storage cell 10 includes a polysilicon gate structure.
te structure) and the upper layer 11 is MOS
It is a silicon substrate of a transistor. Referring to FIG. 3, the pixel is an optical storage cell 20 which is a MOS transistor.
Having. The optical storage cell 20 is an NMOS or PMOS transistor. The gate of the MOS transistor 20 is connected to the bit line B. L. The source S and the drain D of the MOS transistor 20 are short-circuited via a reset switch RST to form an electrode connection connected to the reference voltage V1.

As shown in FIG. 4, a pixel of an image sensor according to another embodiment of the present invention has a MOS transistor 25.
including. The source S and the drain D of the MOS transistor 25 are short-circuited to form an electrode connection. The electrode connection portion further includes a base (sub) of the MOS transistor 25.
strate).

Referring to FIG. 5, a pixel of an image sensor according to another embodiment of the present invention includes a capacitor 30 and a photodiode 35 connected in series. The connection between one terminal of the capacitor 30 and the cathode of the photodiode 35 is connected to a reference voltage V1 via a reset switch RST. The anode of the photodiode 35 is connected to the voltage VSS. Capacitor 3
0 is connected to the bit line B.0 via the extraction hold switch SH. L.

Referring to FIG. 6, a pixel of an image sensor according to another embodiment of the present invention includes a MOS transistor 40 and a photodiode 45 connected in series with each other. The gate of the MOS transistor 40 is connected to the bit line B. L. The source and drain of the MOS transistor 40 are
It is short-circuited to form a connection connected to the reference voltage V1 and the cathode of the photodiode 45. The anode of the photodiode 45 is connected to the voltage VSS.

Referring to FIG. 7, a pixel of an image sensor according to another embodiment of the present invention includes a diode 50 and a photodiode 55 connected in series in opposite directions. The anode of the diode 50 and the anode of the photodiode 55 are connected to each other and to the reference voltage V1 via the reset switch RST. The cathode of the diode 50 is connected to the extraction holding switch S
H via a bit line B.H. L. The cathode of the diode 55 is connected to the voltage VDD.

Referring to FIG. 8, the pixels of another embodiment of the image sensor according to the present invention are similar to the pixels shown in FIG. The difference is that the photodiode 35 is connected in reverse to the capacitor 30. That is, the anode of the photodiode 35 is connected to the reset switch RST.
Connected to one terminal of a capacitor 30 to form a connection to the capacitor 30. The cathode of the photodiode 35 is connected to the voltage VDD.

Referring to FIG. 9, the pixel of the image sensor of another embodiment according to the present invention is similar to the pixel shown in FIG. 6, except that the photodiode 45 is connected in reverse to the MOS transistor 40. It is that you are. That is, the anode of the photodiode 45 is connected to the contact of the MOS transistor 40 and the reset switch RST, and the cathode of the photodiode 45 is connected to the voltage VDD.

Referring to FIG. 10A, an additional amplifying transistor 60 is connected to the upper layer 11 and the extraction holding switch S.
H, except that the pixel shown in FIG. The optical storage cell 10 includes an extraction holding switch SH.
, And to the bit line B. through the amplifying transistor 60. L. An image sensor having a plurality of pixels configured as shown in FIG. 10A functions as an active image sensor. The voltage signal or the current signal is applied to the bit line B. Read via L. FIG. 10B shows the operation of the pixel switch in FIG.

In practice, FIG. 2A or FIG.
Has a non-linear effect. FIG. 11A shows an equivalent circuit.
The non-linear effect is represented by the equivalent diode D1 connected to the lower layer 12 of the optical storage cell 10. The equivalent diode D1 has a capacitance C that varies with the voltage of the diode.
_Act as a variable capacitor with _D1 . Non-linear effects cause signal reading errors.

In order to solve the above problem, the correction circuit 8
0 is added as shown on the right side of FIG. The correction circuit 80 includes two operational amplifiers 81, 82, two switches φ1, φ2, a compensation diode _Dec , and three capacitors C1, C2, C3.

Referring to FIG. 11B, .DELTA.t1 represents a "pixel reset" period for resetting a pixel, .DELTA.t2 represents a "pixel sensing" period for sensing a pixel, and .DELTA.t3 represents a "charge storage" for storing a charge. Δt4 represents a “charge reading” period for reading charges, and Δt5 represents a “output correction” period for correcting an output. The operation of the pixel is shown in FIG.
This is the same as described for (B).

The operational amplifier 81, switch φ1, and capacitor C1 constitute a signal reading loop. FIG.
As shown in FIG. 1B, the switch φ1 is opened only during the charge reading period Δt4, and closed during the other periods, whereby the upper layer 11 of the optical storage cell 10 is maintained at the voltage level of V2. When the switch φ1 is opened, the charge QCm in the optical storage cell 10 is transferred to the capacitor C1,
An output voltage Vy is generated. The correction is mainly performed by the compensation diode _Dec.

The storage capacitance of the optical storage cell 10 is
Cm. This circuit is the capacitor of capacitor C1
The capacitance and the capacitance of the capacitor C2 are the optical storage cells.
10 so that it is equal to the storage capacitance of 10.
That is, it is designed so that Cm = C1 = C2. In addition
And security diode D_ecIs the equivalent capacitance C
_DecIs the equivalent capacitance C of the equivalent diode D1_D1Like
It has been selected to make it easier. Diode D_esNota
Is equal to the terminal voltage of the diode D1,
Signal errors due to non-linear effects are corrected.

Assuming that all of the switches SH, RST, φ1, φ2 and the operational amplifiers 81, 82 in the circuit shown in FIG. 11A are ideal, the operation principle of the correction circuit 80 is as follows.

Referring to FIG. 11B, in a period Δt1, the reset switch RST is closed and connected to the reference voltage V1. Therefore, the voltage level V _n1 at the connection point n 1 connecting the lower layer 12 of the optical storage cell 10 and the reset switch RST is equal to V ₁ , that is, V _n1
= V1. In the period Δt2, the reset switch SRT is opened, and the connection point n1 rises. The voltage level V _n1 becomes V _x , that is, V _n1 = V _x . The charge amount Q n1 at the connection point n ₁ is given by the following equation (1).

[0044]

Q _n1 = (V _x −V ₁ ) · (C _D1 + C m) (1) At the end of the charge storage period Δt 3, the charge amount QCm stored in the storage capacitor Cm of the optical storage cell 10 is Equation (2)
Is obtained by

[0045]

[Number 2] since it is _{QCm = Q n1 · {Cm /} (C D1 + Cm)} ......... (2) C1 = Cm, the voltage level Vy of the connection point Y is the output terminal of the signal read loop has the formula ( 3).

[0046]

Equation 3] _{Vy = {Q n1 / (C} D1 + Cm)} + V2 ......... (3) In the formula (3), the equivalent capacitance C _D1 varies with the base voltage supplied to the PN junction of the diode D1. Therefore, the relationship between the variations of Vy and Qn1 is
_{When n1} is changing, it becomes non-linear. The equivalent capacitance C _Des is selected to be equal to the equivalent capacitance C _D1, and the terminal voltage of the diode _Dec (V3−V2)
Is selected to be equal to the terminal voltage (V1-VSS) of the equivalent diode D1. Accordingly, in the period .DELTA.t4, correction charge Q _cor to the charge in the diode D _ec and the capacitor C2 is expressed by the following equation.

[0047]

(Equation 4) At this time, the resulting corrected output voltage Vz is expressed by the following equation.

[0048]

Equation 5] _{Vz = (Q n1 / C3)} + V3 C3 and because V3 is constant, the relationship between the variation conditions of output voltage Vz and the charge amount Q _n1 of the connection point n1 becomes linear. Therefore, the error caused by the equivalent diode D1 is corrected.

While many features and advantages of the invention have been described above together with the structure and function of the invention, the description is an example and the invention departs from the spirit of the invention as set forth in the appended claims. Various changes can be made without the need.

[Brief description of the drawings]

FIG. 1 is a diagram showing the structure of a conventional MOS image sensor array.

FIGS. 2A and 2B are diagrams for explaining a first embodiment of a pixel of the image sensor according to the present invention, wherein FIG. 2A is a diagram illustrating a pixel, and FIG. Diagram showing time chart

FIG. 3 is a diagram showing a second embodiment of the pixel of the image sensor according to the present invention.

FIG. 4 is a diagram showing a third embodiment of the pixel of the image sensor according to the present invention;

FIG. 5 is a diagram showing a fourth embodiment of the pixel of the image sensor according to the present invention.

FIG. 6 is a diagram showing a fifth embodiment of the pixel of the image sensor according to the present invention.

FIG. 7 is a diagram showing a sixth embodiment of the pixel of the image sensor according to the present invention.

FIG. 8 is a diagram showing a seventh embodiment of the pixel of the image sensor according to the present invention.

FIG. 9 is a diagram showing an eighth embodiment of the pixel of the image sensor according to the present invention.

10A and 10B are diagrams for explaining a ninth embodiment of the pixel of the image sensor according to the present invention, wherein FIG. 10A is a diagram illustrating a pixel, and FIG.・ Figure showing chart

FIG. 11 illustrates a tenth pixel of the image sensor according to the present invention.
FIGS. 3A and 3B are diagrams for explaining the embodiment of FIG. 3A, and FIG. 3A is a diagram illustrating a pixel, and FIG.

[Explanation of symbols]

Reference Signs List 10 optical storage cell 11 upper layer 12 lower layer 20, 25, 40, MOS transistor 30 capacitor 35, 45, 55 photodiode 50 diode 60 amplifying transistor 80 correction circuit 81, 82 operational amplifier B. L Bit line SH Extraction holding switch RST Reset switch D Drain S Source C1, C2, C3 Capacitor D1 Equivalent diode _Dec Compensation diode

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 1, 2000 (2000.5.1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

[0021] external light is incident on the lower layer 12, the lower layer 12 generates a negative charge e ^over senses the light. The lower layer 12 receives the reference voltage V through a reset switch RST.
1 terminal. The upper layer 11 includes a bit line B.I. L. Pixel operations such as reset, sensing, charge accumulation, and charge output can be performed continuously by controlling the on / off of the switches SH, RST.

Claims (13)

[Claims] 1. A pixel array arranged in rows and columns, a plurality of word lines each connected to a plurality of pixels in a column, and a plurality of bits each connected to a plurality of pixels in a row. A line, a horizontal scanning circuit, and a vertical scanning circuit for scanning the pixel, wherein each pixel has a lower layer for sensing light to generate an accumulated charge, and corresponds to the charge generated in the lower layer. An optical storage cell having an upper layer that induces a charge to accumulate and accumulates the induced charge;
An extraction and holding switch connected to an upper layer of the optical storage cell for outputting the induced charge, wherein the reset switch and the extraction and holding switch are first closed to reset the optical storage cell, and then the optical storage cell The reset switch is closed, the reset switch is closed, and the extract and hold switch is closed so that the lower layer of the sensor floats to generate light upon sensing light and a corresponding charge is induced in the upper layer. Being released, the upper layer lifts up to store the induced charge,
Finally, the extract and hold switch is closed again to output the stored charge. 2. The image sensor according to claim 1, wherein an upper layer of the optical storage cell is made of a conductive material. 3. An upper layer of the optical storage cell is transparent.
The image sensor according to claim 2. 4. The image sensor according to claim 3, wherein the upper layer of the optical storage cell is made of polysilicon. 5. The image sensor according to claim 2, wherein the upper layer of the optical storage cell is made of polysilicon. 6. The optical storage cell according to claim 1, further comprising a gate as the upper layer and a silicon substrate as the lower layer.
The image sensor according to claim 1, wherein the image sensor is an OS transistor. 7. The image sensor according to claim 6, wherein a source and a drain of the MOS transistor are connected to each other to form an electrode connection of the lower layer. 8. The image sensor according to claim 6, wherein a source and a drain of the MOS transistor are connected to the base to form an electrode connection of the lower layer. 9. The optical storage cell includes a capacitor and a photodiode connected in series to each other.
The image sensor according to claim 1. 10. The image sensor according to claim 1, wherein said optical storage cell comprises a MOS transistor and a photodiode connected in series to each other. 11. The image sensor according to claim 1, wherein the optical storage cell includes a diode and a photodiode connected in series to each other. 12. An amplifier transistor connected between the optical storage cell and the extraction holding switch.
The image sensor according to claim 1. 13. The image of claim 1, further comprising a compensating diode connected to said extract and hold switch, said compensating diode having a terminal voltage and a capacitance equal to a terminal voltage and an equivalent capacitance of said optical storage cell. Sensor.