JP2000207899A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the test time and to reduce the chip cost by providing a dummy memory cell in which an internal memory value is fixed outside a memory cell being remotest from decoders of word lines and bit lines of an address signal, and enabling a test of word lines and bit lines to be performed by only reading successively data of a dummy memory cell at the time of a test. SOLUTION: When a bit line is tested, a row decoder 2 prohibits decoding operation of a row address signal by a test signal TSTC and starts a word line WLD connected to a dummy cell 4 in a timing being the same as that of a normal word line. A column address signal is varied in this state, bit line is successively selected, data of the dummy cell 4 is read out (n) times, verified with an internal memory value in the dummy cell 4 previously set, and a test is performed. In the same way, a word test is performed. Thus, as a simple test is performed by selecting simply and successively word lines and bit lines, a test can be performed in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a simple test for word lines and bit lines.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, as shown in a block diagram around a memory cell in FIG. 2, a signal obtained by pre-decoding an externally input address signal is input to a row decoder 2 as a row address signal. The row decoder further decodes the row address signal and selects one of the m word lines WL1 to WLm. On the other hand, similarly, the column decoder 3 receiving the column address signal obtained by pre-decoding the externally input address signal selects one of the n bit lines BL1 to BLn. Although the bit line may be a pair of complementary data lines, only one bit line is shown for simplicity. The configuration around the memory cell of the semiconductor memory device shown in FIG.
Readable RAM (Random Access)
Memory (Read Only) ROM (Read)
Only Memory). In order to perform an operation test of the semiconductor memory device shown in FIG. 2, one word line is selected and one (one pair) bit line is selected at the same time, and data is read / written to verify input / output data. It is done by taking. In the case of a ROM, it is only necessary to read data several times m × n times in a memory cell array and check it against an expected value. However, in the case of a RAM, after writing data once,
Since the written data is read and the data is collated, the test time is about twice as long as that of the ROM in simple consideration. In addition, with the recent miniaturization of the semiconductor process, the memory capacity has followed a path of increase, and accordingly, a huge amount of time has to be devoted to the test time of the semiconductor device, leading to an increase in the cost of the semiconductor device. I will.

[0003]

A semiconductor device is usually tested for all memory cells in a wafer state, and the same test is performed after being packaged in a molded product or the like. The test time for this directly repels the cost of the semiconductor device. Therefore, although it is necessary to reduce the test time, the conventional method has a disadvantage that the test must be performed on all the memory cells, and the test time cannot be reduced.

[0004]

A plurality of word lines and bit lines selected by decoding an externally input address signal and a memory cell provided at the intersection of each word line and each bit line are provided. A dummy memory cell having an internally stored value fixed outside a memory cell farthest from a word line and a bit line decoder of the address signal.

[0005]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram around a memory cell in one embodiment of the present invention. In the figure, 1 is an array of memory cells arranged in a matrix of m rows and n columns, 2 is a row decoder for selecting a word line, 3 is a column decoder for selecting a bit line, and 4 and 5 have fixed internal storage values. Dummy memory cells. In a normal operation, an address signal input from outside the semiconductor device is input to the row decoder 2 as a row address signal after being predecoded as necessary through an address input circuit. In response to this, the row decoder further performs a decoding operation and selects only one word line from the m word lines WL1 to WLm. Similarly, an externally input address signal is input to the column decoder 3 as a column address signal after being pre-decoded as necessary via an address input circuit, and the column decoder further performs a decoding operation to obtain n (n)
By selecting one (one pair) of the (paired) bit lines BL1 to BLn, the memory cell existing at the intersection of the selected word line and bit line becomes active, so that reading and writing to the memory cell can be performed. Write becomes possible. The above operation is not different from the conventional semiconductor memory device. Next, when a semiconductor test is performed, a test signal is input from outside the semiconductor device. When a bit line is tested, a test signal TS is input.
The TC is input to the row decoder 2, and the row decoder inhibits the decoding operation of the row address signal and raises the word line WLd connected to the dummy cell 4 at the same timing as the normal word line. In this state, the bit line is sequentially selected by changing the column address signal, the data of the dummy memory cell is read n times, and a test is performed by comparing the data with the preset internal storage value of the dummy memory cell. Similarly,
Since the test signal TSTR is input to the column decoder 3 when testing the word line, the column decoder inhibits the decoding operation of the column address signal and sets the bit line BLd connected to the dummy cell 5 at the same timing as the normal bit line. To select. In this state, the word line is sequentially selected by changing the row address signal, the data of the dummy memory cell is read m times, and the test is performed by comparing the data with the preset internal storage value of the dummy memory cell. In this way, a simple test is performed by sequentially selecting one word line and one bit line, so that a short-time test of reading data of the dummy cell (m + n) times becomes possible.

FIG. 3 shows a part of a circuit diagram of the memory cell array and dummy cells in FIG. Memory cells 11 to 14 surrounded by dashed lines are full CMOS type memories each including a transmission transistor and a driving transistor each including two N-channel transistors and a load transistor including two P-channel transistors. Cell. Although a full CMOS type memory cell is used in the figure, the load transistor may be a TFT or a high resistance type. Reference numerals 41 to 44 denote N-channel transistors whose gates are connected to a word line WLd selected at the time of testing a bit line. The drain or source has a complementary bit line pair XBLn-1 / BLn-.
1 and XBLn / BLn, and the other terminal is a dummy cell connected to a power supply potential or a ground potential. Reference numerals 51 to 54 denote N-channel transistors whose gates are connected to a word line selected at the time of normal operation, whose drain or source is connected to a complementary bit line pair XBLd / BLnd selected at the time of testing and the other terminal. Are dummy cells connected to the power supply potential or the ground potential. First, a normal operation will be described with reference to FIG. An address signal input from the outside of the semiconductor device passes through an address input circuit, is pre-decoded as necessary, and then is input to a row decoder as a row address signal. The row decoder receives the signal and performs a decoding operation. , One word line is selected from the word lines WL1 to WLm, the logic level becomes "H", and the transmission transistor of the memory cell connected to this word line is turned on. Similarly, an externally input address signal passes through an address input circuit, and after being predecoded as necessary, is input to a column decoder as a column address signal. The column decoder further performs a decoding operation, and the n pairs of bit lines XBL
By selecting a pair from 1 / BL1 to XBLn / BLn, the memory cell at the intersection of the selected word line and bit line becomes active, and reading and writing to the memory cell become possible. . For example, the word line WL1 and the bit lines XBLn-1 / BLn-1
Is selected, the memory cell 11 can be accessed. Although not shown in the figure, when data is read, the potential difference of the storage node of the memory cell appears on the bit line pair via the transmission transistor. A minute potential difference is amplified by a sense amplifier. If the storage node of the memory cell connected to XBLn-1 via the transmission transistor is at “H” level and the opposite node is at “L” level,
A potential lower than XBLn-1 appears at BLn-1, and the corresponding memory cell holds "0" data. Conversely, if the storage node of the memory cell connected to XBLn-1 via the transmission transistor is at the “L” level and the opposite node is at the “H” level, the corresponding memory cell holds “1” data. Will be. At the time of writing data, a potential having a large potential difference is applied to a pair of bit lines from a write buffer connected to a selected bit line, and the data is written as logic data to a memory cell via a transmission transistor. That is, to write "0" data to a memory cell, an "H" level potential is applied to BLn-1 and an "L" level potential is applied to XBLn-1.
When writing "1", the opposite potential is applied.
In a conventional semiconductor memory device, during a test, data of a specific pattern is written into a memory cell by such an operation, data is read from the memory cell, data is collated in a test device, and the quality of the semiconductor memory device is determined. Deciding. However, if the dummy memory cell of FIG. 3 which is one embodiment of the present invention is used, there is no need to write data. First, when testing a bit line, a dummy word line W
Only Ld is selected at the same timing as a normal word line and is raised to "H" level. Next, the bit line is changed to XB by changing the externally applied column address signal.
From L1 / BL1 to XBLn / BLn, data of the dummy memory cell is sequentially read out n times, and a test is performed by comparing the data with a preset internal storage value of the dummy memory cell. Similarly, when testing a word line, dummy bit lines XBLd / BLd are selected at the same timing as a normal bit line. In this state, an externally applied row address signal is changed to change word lines from WL1 to WLm.
, The data of the dummy memory cell is read m times, and a test is performed by comparing the data with the preset internal storage value of the dummy memory cell. That is, as long as there is no defect such as a shorted bit line during the bit line test, XBLn-1
/ BLn-1 and XBLn / BLn are sequentially selected, X
Since an "L" level potential appears at BLn-1, an "H" level potential appears at BLn-1, "1" data is read out, and an "H" level potential is applied to XBLn and "L" is applied to BLn. Since a "level" potential appears, "0" data is read. Similarly, if WL1 is selected during the word line test as long as there is no defect such as a broken word line, XB
Since an “L” level potential appears at Ld and an “H” level potential appears at BLd, “1” data is read out and WL2 is read out.
Is selected, XBLd has an “H” level potential, BL
Since an “L” level potential appears at d, “0” data is read. As described above, in the conventional test method and the semiconductor memory device, data must be written to the memory cell at least (m × n) times, and then the data must be read to perform data collation. At least (2 × m × n) accesses are required. On the other hand, when the semiconductor memory device according to the embodiment of the present invention is used, data can be read out and verified by (m + n) accesses, so that the time required for the test is greatly reduced, and the bit capacity of the semiconductor memory device is reduced. A larger value can contribute to a reduction in manufacturing cost.

FIG. 4 is a schematic diagram of a pattern of a well region of a semiconductor substrate of a memory cell array according to one embodiment of the present invention. This figure shows a well region when a complete CMOS type memory cell is used. A blank region 6 is an N well region in which a P-channel transistor is formed, and a hatched region 7 is an N channel transistor. P well region. Although only a part of the memory cell array is shown in FIG. 4, a dummy memory cell is formed in the outermost P-well region, and continuously surrounds the upper side and the right side of the memory cell. Generally, a layout pattern is dense in a memory cell array in order to increase the degree of integration of a semiconductor device, and is sparse in a peripheral circuit such as an input / output circuit as compared with a memory cell array from the viewpoint of improving yield. At such a boundary of sparse / dense, that is, at the outer peripheral portion of the memory cell array, the well region becomes thin due to resist receding or a loading effect, which may cause a leak. Also, in order to prevent the fluctuation of the power supply voltage when the peripheral circuit operates to destroy the data stored in the memory cell, a guard ring including a dummy memory cell is conventionally arranged on the outer periphery of the memory cell array. I was However, the conventional dummy is simply a dummy with only a shape,
In many cases, only a diffusion region was arranged, or even if a transistor was formed, a gate electrode was fixed in voltage or a source / drain was floated. In addition, the location where the memory cell array is arranged does not surround the periphery of the memory cell array. In FIG. 4, the memory cell array is often arranged only on the upper side of the memory cell array. However, in FIG. 4, which is an embodiment of the present invention, the semiconductor chip does not become large because the area where the dummy memory cells are conventionally arranged is effectively used. In addition, since the dummy memory cell surrounds two sides of the memory cell array adjacent to the peripheral circuit and the well region for forming the transistor of the dummy memory cell can be continuously arranged, the leakage between wells is strong, and the leakage from the peripheral circuit is reduced. There is also a merit that it is hard to be affected.

[0008]

As described above, by arranging a dummy memory cell having a fixed internal storage value outside a memory cell farthest from the word line and bit line decoder, this fixed memory cell is tested during testing of the semiconductor memory device. The word line and the bit line can be tested only by sequentially reading the read data, which has the effect of shortening the test time and reducing the chip cost. In addition, since the dummy cell is arranged at the place where the conventional shape dummy is arranged, there is an effect that a memory cell which does not increase the chip area and is less susceptible to noise from peripheral circuits can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram around a memory cell in an embodiment of the present invention.

FIG. 2 is a block diagram around a conventional memory cell.

FIG. 3 is a circuit diagram around a dummy memory cell in the embodiment of the present invention.

FIG. 4 is a well layout diagram near a dummy memory cell in an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Row decoder 3 Column decoder 4,5 Dummy cell 11-14 Complete CMOS type memory cell 41-44,51-54 N channel type transistor 6 N well region 7 P well region

Claims (5)

[Claims] A plurality of word lines and bit lines selected by decoding an externally input address signal;
A dummy memory having a memory cell provided at an intersection of each word line and each bit line, wherein an internal storage value is fixed outside a memory cell farthest from a word line and a bit line decoder of the address signal; A semiconductor memory device comprising a cell. 2. A dummy memory cell according to claim 1, wherein the dummy memory cell is connected to a complementary bit line pair selected by a test means, and is connected to a word line selected by decoding an externally input address signal. A semiconductor memory device characterized by the above. 3. A dummy memory cell according to claim 1, wherein the dummy memory cell is connected to a word line selected by a test means, and a transmission transistor is connected to a complementary bit line selected by decoding an externally input address signal. A semiconductor memory device characterized by being performed. 4. A source or a drain is connected to one bit line of the dummy memory cell, and a gate is a word line selected by decoding an address signal inputted from the outside or a word selected at the time of a test. A transmission transistor to which a line is connected is provided, a terminal of the transmission transistor opposite to a terminal connected to the bit line is fixed to the first power supply voltage, and the other bit line has a similar configuration. A semiconductor memory device, wherein a terminal of a transmission transistor opposite to a terminal connected to a bit line is fixed to a second power supply voltage. 5. A transistor forming the dummy memory cell is of a single conductivity type and is arranged in the same well region.
A semiconductor memory device, wherein the well region continuously surrounds the periphery of a memory cell array.