JP2000207444A - Method and device for extracting common part logical expression, and record medium recorded with extraction program of common part logical expression - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce processing time for extracting a common part logical expression from plural product-sum type logical expressions in logic design. SOLUTION: This device is provided with a kernel graph generating part 122 that generates a candidate of a common part logical expression which is called a kernel from plural product-sum type logical expressions, a kernel graph storing part 132 which stores the generated kernel and the generating process by using a directed graph consisting of nodes and branches and a node managing part 123 which decides the equivalent property of nodes of the directed graph, and ignores the kernel generation processing when what is equivalent to a node of a graph to be generated already exists in the kernel generating process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can be applied to the extraction of a common part of a product-sum logical expression in a logic design support system. The present invention relates to a technique for converting into a multi-stage expression. Since the product-sum logic expression corresponds to a logic circuit using a NOT / AND / OR gate, a smaller-scale logic circuit can be designed by reducing the number of characters of the product-sum logic expression.

[0002]

2. Description of the Related Art First, a product-sum type logical expression will be described. A literal is a variable (a, b, c,...) That takes a value of 0 or 1.
.) And its negation (a ', b', c ',...). A product term is the product of one or more literals, for example, a
b'de, cde, and f are product terms. The product-sum formula is 1
It is the sum of two or more times, for example, ab'de + cde +
f is a product-sum formula. The product-sum logical expression is NOT / AN
It can be realized as a logic circuit using a D / OR gate. For example, F ₁ = ab'de + cde + f is equivalent to (A) in FIG.
A logic circuit as shown in FIG. Hereinafter, if it is clear from the context, the product-sum type logical expression may be simply referred to as a logical expression.

When a plurality of product-sum logical expressions are given, if the product terms can be shared, the cost of a logic circuit for realizing them can be reduced. For example, F ₂ = ab'f along with F ₁ = ab'de + cde + f
+ Cde + f, G ₁ = cde + f is defined as a common partial logical expression, and F ₁ = ab'de + G ₁ , F ₂ = a
It can be a b'f + G _1.

A product-sum logical expression can be transformed into a general mathematical expression by dividing by a product of literals that appear multiple times. For example, F ₁ = ab'de + cde + f has two product terms including the literal product de, and (ab'de +
cde) / (de) = ab '+ c, so that F ₁ = ab'de + cde + f = (ab' + c) d
It can be transformed to e + f. By performing such an operation, a partial logical expression may be shared between a plurality of logical expressions not having the same product term. For example, F ₁ = ab'de + cde
+ F along with F ₃ = ab'f + cf + cg ', there is no common product term, but F ₃ = (ab' +
c) By transforming to f + cg ′, G ₁ = G ₂ de + f and F ₃ = G ₂ f where G ₂ = ab ′ + c is a common partial logical expression.
+ Cg ', and as shown in FIG. 8C, the cost of the logic circuit for realizing the whole can be reduced. FIG. 8B shows the original logic circuit of F3.

In the above example, a common sub-logical expression could be found by successfully modifying F _{1.
In the case of 1} = (ab'd + cd) e + f, a common partial logical expression cannot be found. This is because a literal d that appears in all product terms exists in the partial logical expression ab'd + cd. Hereinafter, such a literal is referred to as a common literal. In general, a quotient obtained by dividing a given logical expression by a product of literals that appear multiple times and not including a common literal is called a kernel,
It is considered to be suitable as a candidate for a common sub-logical formula (references: RK Brayton, R. Rudell, A. Sang
iovanni-Vincentelli and AR Wang, "MIS:
A Multiple-Level Logic Optimization System
m, "IEEE Transactions on Computer-Aided D
esign, vol. CAD-6, no. 6, pp. 1062-108
1, Nov. 1987).

The following is known as a technique for generating all kernels for a given logical expression. 1. If a common literal exists in a given logical expression, the logical expression is divided by all the literals, and the logical expression of the quotient is set to F. If it does not exist, the given logical expression is set to F as it is. 2. Ordering all the literals of the logical expression F, l _n , l
_n-1 ,..., l ₁ . 3. The recursive procedure shown in FIG.
Call in n).

In the recursive procedure shown in FIG. 9, basically,
Recursively performs the operation of dividing the given logical expression by literals that occur multiple times (operator / indicates division), and if there is a common literal in the resulting logical expression, further divides them and registers them as a kernel. ing. In addition, control is performed by ordering literals so that the same kernel is not registered twice or more. The part that the enumerated literal is equal to or less than the topIndex given as an argument, and the part that the subsequent processing is not performed if a literal whose subscript is greater than i exists in the comCube, play the role.

As an example, the logical expression F ₄ = abcg '+ ab
FIG. 10 shows how all kernels are generated for d + ae + bc'fg + c'fh. Since there is no common literal in the given logical expression, this is set to F as it is. The order of the literals is shown in FIG.
Call Kernel (F, 10). Literals that appear a plurality of times and have a suffix of 10 or less are a, b, c ', and f, and the processing proceeds for each. A common literal comCube does not occur for the result of dividing by a and b,
For the result of dividing by c 'and f, the common literal comCube
Occurs. In the case of f, the subscript of comCube is 4 (f =
l ₄ ) Since there is a literal c ′ = l ₇ larger than l ₄ ), the subsequent processing is not performed.

FIG. 11 shows a procedure of extracting a common partial logical expression, which is generally performed conventionally. First, kernels are generated for all given logical expressions (steps 1100 and 1110). Then, the most effective kernel is selected as the common partial logical expression, and another logical expression using it is updated (steps 1120, 1130). For the updated logical expression, a kernel is generated again, and the selection of the most effective kernel as the common partial logical expression is repeated as long as a valid one exists.

As an example, a logical formula F ₄ = ab shown in FIG.
When cg '+ abd + ae + bc'fg + c'fh and formulas _{F 5 = abg + ah + c} ' is given, consider to extract the common partial logical expressions. Figure ₄ shows the F4 kernel
Is as shown in 0, the kernel of F ₅ is itself and bg
+ H only. Therefore, it can be seen that bg + h is a valid kernel as a common partial logical expression. When this is registered as a new logical expression G ₃ = bg + h and the logical expression using this is updated, F ₄ = abcg ′ + abd + ae +
c′fG ₃ , F ₅ = aG ₃ + c ′ After that, the kernel is generated again for each updated. Figure 12 shows the state of the kernel generation for F ₄ which is updated.
With respect to the F ₅ that have been updated, it kernel other than its own does not exist. Accordingly, there is no longer any effective common partial logical expression, and the process is terminated.

[0011]

In the prior art, after a common partial logical expression is selected and the logical expression is updated, kernel generation processing is performed again on the new logical expression. However, as can be seen when compare to FIGS. 10 and 12 of the previous example of F _4,
The same kernel is often generated in the formula before the update and the formula after the update.

[0012] An object of the present invention is to omit the generation process when a kernel generation request is issued for the same partial logical expression as that already generated in the extraction of the common partial logical expression. In order to eliminate the processing time.

[0013]

In order to achieve the above object, according to the present invention, there is provided a means for generating a candidate for a common partial logical expression called a kernel for a logical expression, and a method for generating the generated kernel and its generation process by using a directed graph. And means for determining the equivalence of the nodes of the directed graph.

In the present invention, the generated kernel and its generation process are stored using a directed graph, and the graph is gradually constructed in the kernel generation process. In the process of generating a kernel, a given logical expression is analyzed, and what kind of nodes are required to construct the graph is calculated. For a request for a required node, the means for determining the equivalence of the node can check whether or not an equivalent to the required node already exists. Therefore, in the kernel generation process, if there is no equivalent to the required node, a new node is generated and the subsequent processing proceeds, but if there is already an equivalent to the required node, this node is Subsequent processing can be omitted using the nodes.

For example, regarding the above-mentioned logical expression F ₄ , the generation of the kernel for the partial logical expression bcg ′ + bd + e has been conventionally performed by both the logical expression before the update and the logical expression after the update. When the present invention is applied, these processes need only be performed once.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a configuration example when the present invention is applied to a logic design support system. In the figure, 110 is an input / output unit for inputting or outputting a set of logical expressions, 120 is a processing unit for extracting common logical expressions, and 130 stores a set of input logical expressions and a generated kernel graph. These are storage units, which are actually configured using computer resources. Here, the processing unit 120 includes a logical expression management unit 121, a kernel graph generation unit 122, a node management unit 123, and a common partial logical expression selection unit 124. The storage unit 130 includes a logical expression storage unit 131 and a kernel graph storage unit 132.

A set of logical expressions to be processed is input from the input / output unit 110 and stored in the logical expression storage unit 131 through the logical expression management unit 121. After the extraction of the common partial logical expression, the logical The resulting set of logical expressions is returned to the input / output unit 110 through the expression management unit 121. The logical expression management unit 121 stores the set of logical expressions given from the input / output unit 110 in the logical expression storage unit 131 and manages the state of the logical expression. Each time is selected, the set of logical expressions is updated, and the set of logical expressions as the final result is returned to the input / output unit 110. The kernel graph generation unit 122 receives a logical expression from the logical expression management unit 121, analyzes the logical expression, generates a kernel graph, stores the generated kernel graph in the kernel graph storage unit 132, and manages necessary kernel graph nodes. Request to the unit 123. The node management unit 123 checks whether the requested node already exists in the kernel graph storage unit 132, and if so, notifies the kernel graph generation unit 1 of that fact.
Tell 22. If it does not exist, a node is created and the kernel graph generation unit 122 is notified that a new node has been created. After the generation of the kernel graphs for all the logical expressions stored in the logical expression storage unit 131, the common partial logical expression selection unit 124 refers to the kernel graph storage unit 124 to determine the most common common logical expression. A valid one is selected from the generated kernels and reported to the logical expression management unit 121. In response to this, the logical expression management unit 121 updates the set of logical expressions in the logical expression storage unit 131.

The outline of the procedure for extracting the common part logical expression according to the present invention is basically substantially the same as that of FIG. 11, except for the part for generating the kernel. Therefore, hereinafter, in particular, the kernel graph generation unit 122, the node management unit 123,
The kernel graph storage unit 132 will be described in detail.

[Kernel Graph Storage Unit] The kernel graph storage unit 132 stores a directed graph named a kernel graph. As shown in FIG. 2, the kernel graph is composed of nodes and branches, and expresses all kernels for a given logical expression. The structure is based on the operation of the kernel graph generation unit 122 described later. A node has a corresponding partial logical expression F, an integer value topLitIndex, and a set of edge pointers edgePointers. topLitInd
ex is the largest suffix of a literal appearing in a branch of the node, and is 0 when there is no branch. The branch has a product comCube of a common literal of the literal Lite and F / lit and a pointer nodePointer to a node.

As an example, the logical expression F ₄ = abcg '+ ab
d + ae + bc'fg + c'fh and F ₅ = abg + ah
The kernel graph for + c 'is shown in FIG.

Note that storage of logical expressions, determination of coincidence of logical expressions,
As a method for efficiently realizing division of logical expressions, enumeration of common literals and multiple literals in logical expressions, etc.
A method of expressing a logical expression using a graph structure is known (for example, Shinichi Minato, “Zero Suppressed Binary Decision Diagram and Its Application”, IEICE Spring Meeting, 1993, p.
p. 1.368-1.369, SA-2-2). In this method, since the same logical expression is expressed by the same node, it is possible to immediately determine whether the logical expressions match. Even if many logical expressions are expressed, a large amount of storage is not required because many nodes of the graph are shared between different logical expressions.

[Node Management Unit] The node management unit 123 determines equivalence of nodes when the kernel graph generation unit 122 requests a node generation. If an equivalent node already exists at that time, generation of the node can be omitted. An equivalent node is equivalent to a branch coming out of the node (lit and com
Cubes are equal), the nodes pointed to by those branches are also equivalent. According to the operation of the kernel graph generation unit 122 described later, if the following two conditions are satisfied, 2
Two nodes are equivalent. 1. The partial logical expressions F are the same. 2. The integer value topLitIndex is the same.

Hereinafter, the node having F and topLitIndex will be represented as node (F, topLitIndex). The node node (bg + h, 0) in FIG. 3 is used in both the logical expressions F ₄ and F ₅ . This is because an equivalent node generation request was made in the process of generating the kernel graph for each logical expression.

[Kernel Graph Generation Unit] The kernel graph generation unit 122 generates a kernel graph for the logical expression given by the logical expression management unit 121. The procedure is shown below. This is roughly the same as the procedure for generating a kernel shown in the prior art, but is a recursive procedure.
generateKernel (F, n) is genKernelGr here
aph (F, n). 1. If a common literal exists in a given logical expression, the logical expression is divided by all the literals, and the resulting logical expression is set to F. If it does not exist, the given logical expression is
And 2. Ordering all the literals of the logical expression F, l _n ,
_Let l _n−1 ,..., l ₁ . 3. The recursive procedure shown in FIG. 4 and FIG.
Called by raph (F, n).

FIGS. 4 and 5 are flowcharts of genKernelGraph, which is a main procedure for generating a kernel graph. genKernelGraph is a logical expression F and an integer value top
Given an Index, the process proceeds.

First, as shown in FIG. 4, literals appearing in a logical expression a plurality of times and whose subscripts are equal to or smaller than topIndex are enumerated, and for each literal l _i , comCube _i and cube
Register for FreePart _i . Gener shown in Fig. 9
Like ateKernel (F, n), control is performed by ordering literals so that the same kernel is not processed twice or more.

Next, as shown in FIG. 5, the maximum subscript of the registered literal is set to topLitIndex (if there is no registered literal, this is set to 0), and the logical expressions F and to
An inquiry is made to the node management unit 123 as to whether or not a node equivalent to a pair of pLitIndex already exists. The node management unit 123 returns an existing node if it exists. If it does not exist, create a new node,
Return this. If a node already exists, the subsequent processing in the kernel graph generation unit 122 is omitted.
If not present, the registered literal
genKernelGraph (cubeFreePart _i , i-1) is called, a branch is provided between the resulting node and itself, and li of the branch
Let t and comCube _i be l _i and comCube _i , respectively.

[Example 1 in which the processing can be omitted] Here, an example in which the kernel generation processing can be omitted according to the present invention will be described. As in the example shown in the prior art, the logical expression F ₄ = abcg ′
+ Abd + ae + bc′fg + c′fh and F ₅ = abg
+ Ah + c ′, a kernel graph is generated for each of them, and a common partial logical expression G ₃ = bg + h is selected. Then, F ₄ and F ₅ are respectively F _4R
= Abcg '+ abd + ae + c'fG 3, F 5R = aG 3
+ C 'is updated.

After that, a kernel graph is generated for F _4R . First, literals are ordered as shown in FIG. Since the common literal does not exist in the F _4R, gen
KernelGraph (abcg '+ abd + ae + c'fh
G ₃ , 11) is called. Literals that appear multiple times are l ₁₀ = a and l ₈ = b, and since they are registered as literals to be processed, topLitIndex is 10.
The node (abcg '+ abd + ae +
When c'fhG ₃ , 10) is inquired as to whether it already exists, since it does not exist, this node is newly created. afterwards,
First, for a literal l ₁₀ = a, genKernelGraph (bc
g '+ bd + e, 9) is called. Since the only literal to be registered is l ₉ = b, node (bcg ′ + bd +
e, 9) is inquired to the node management unit 123 as to whether or not there is. In this case, since this node already exists, the subsequent processing can be omitted. Similarly, the literal l
₉ = b for genKernelGraph (bcg '+ ad + c'
When fg, 8) is called, there is no literal that appears multiple times and has a subscript of 8 or less, so node (acg '+ ad +
Check whether c′fg, 0) exists. In this case as well, it already exists and subsequent processing can be omitted.

[Example 2 in which processing can be omitted] An example in which processing can be omitted in the process of generating a kernel for one logical expression according to the present invention will be described. FIG. 7 shows the logical expression F ₆
7 shows a kernel graph for == acd + ace + af + bcd + bce + bf. Node node (cd + ce + f,
4) and node (a + b, 0) are indicated by a plurality of branches. In particular, the fact that node (cd + ce + f, 4) is pointed out from two branches means that the processing for the partial logical expression cd + ce + f is performed twice in the related art.
The present invention means that the process only needs to be performed once.

The embodiment of the present invention has been described above.
The procedure and algorithm of the common part logical expression extraction according to the present invention, which are executed by the processing unit 120 of FIG. CD-ROM) or the like.

[0032]

As described above, according to the present invention,
In the process of extracting common sub-logical expressions in logical design,
It is possible to omit the generation of a kernel for the same partial logical expression as the one for which the kernel has already been generated.

In the process of extracting the common partial logical expression,
A process is repeated in which a kernel is generated for a given logical expression, a certain kernel is selected as a common partial logical expression, and a logical expression using this is updated. Among them, a given logical expression gradually changes, and a logical expression before update and a logical expression after update often differ only partially. Therefore, when the kernel is repeatedly generated, many processes for the same partial logical expression appear. Also, even in the process of generating a kernel for one logical formula, the process of generating a kernel for the same partial logical formula may be performed. Therefore, there are many opportunities to omit the process of generating the kernel for the same partial logical expression in the process of extracting the common partial logical expression from the product-sum logical expression. By using the present invention,
In the entire process of extracting the common part logical expression from the plurality of product-sum logical expressions, there is an effect that the total processing time for kernel generation can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example when the present invention is applied to a logic design support system.

FIG. 2 is a diagram illustrating a data structure of nodes and branches of a kernel graph.

FIG. 3 is a diagram illustrating an example of a kernel graph.

FIG. 4 is a diagram showing a procedure for generating a kernel graph.

FIG. 5 is a diagram illustrating a continuation of the procedure for generating the kernel graph in FIG. 4;

FIG. 6 is a diagram illustrating an example of a kernel graph for an updated logical expression.

FIG. 7 is a diagram illustrating an example of a kernel graph in which nodes are shared by only one logical expression.

FIG. 8 is a diagram illustrating an example of extracting a common part of a logical expression.

FIG. 9 is a diagram showing a general procedure of kernel generation.

FIG. 10 is a diagram illustrating an example of general kernel generation.

FIG. 11 is a diagram showing an outline of a conventional procedure for extracting a common partial logical expression.

FIG. 12 is a diagram illustrating an example of general kernel generation for an updated logical expression.

[Explanation of symbols]

 Reference Signs List 110 input / output unit 120 processing unit 121 logical expression management unit 122 kernel graph generation unit 123 node management unit 124 common partial logical expression selection unit 130 storage unit 131 logical expression storage unit 132 kernel graph storage unit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Akira Nagoya 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5B046 AA08 BA02 5J056 AA00 BB02 BB59 CC00 HH04

Claims (3)

[Claims] 1. A method for extracting a common sub-logical expression from a plurality of sum-of-products logical expressions in a logic design, comprising generating a common sub-logical expression candidate called a kernel, and generating the generated kernel and its generation process. Is stored using a directed graph composed of nodes and branches, and in the kernel generation process, it is determined whether or not there is already an equivalent to the node of the graph to be generated, and if an equivalent node already exists, Is a method for extracting a common partial logical expression, wherein the kernel generation processing is omitted. 2. An apparatus for extracting a common partial logical expression from a plurality of sum-of-products logical expressions in a logical design, comprising: means for generating a candidate for a common partial logical expression called a kernel; There are means for storing the process using a directed graph composed of nodes and branches, and means for determining the equivalence of the nodes of the directed graph.In the kernel generation process, there is already a node equivalent to the node of the graph to be generated In such a case, the kernel generating process is omitted, and a common partial logical expression extracting device is characterized in that the kernel generating process is omitted. 3. A computer-readable recording medium on which a program for extracting a common partial logical expression from a plurality of product-sum logical expressions in a logical design is recorded, wherein a process for generating a common partial logical expression candidate called a kernel is performed. Process, the generated kernel and its generation process,
In the process of storing using a directed graph composed of nodes and branches, and in the kernel generation process, determine whether there is already an equivalent to the node of the graph to be generated,
A process for skipping a kernel generation process when an equivalent node already exists, in which a common part logical expression extraction program is recorded.