JP2000207173A - Incrementor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the propagation speed of a carry value to a higher-order bit by outputting the multibit carry value, corresponding to an arithmetic result as a carry value from the most significant digit bit from among successive bits. SOLUTION: A logic circuit 24 for multibit arithmetic value arithmetic is connected to terminals 16 and 17 for the lowest-order bit and the 2nd bit from the lowest, which are inputted to a block 4, ANDs them, and outputs a multibit arithmetic value according to the result. A logic circuit 25 for multibit carry value operation has a carry value input terminal 20 connected thereto, inputs and ANDs multibit arithmetic values, and outputs the result as carry value of the most significant digit bit (2nd lowest bit from) of the block 4. Thus, a multibit arithmetic value of successive bits is calculated before the carry value reaches the least significant digit bit, and the carry value to a bit several bits above the least significant digit bit is generated immediately after the carry value reaches the least significant digit bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an incrementer for adding a predetermined fixed value to data consisting of a plurality of bits, and more particularly to an improvement for improving the arithmetic processing speed.

[0002]

2. Description of the Related Art FIG. 14 is a block diagram showing the configuration of a conventional incrementer disclosed in Japanese Patent Application Laid-Open No. 3-18926. In the figure, 1 is a data input terminal to which a bit input value of input data is input, 2 is a data output terminal to output a bit increment value of output data, 64 is a fixed value input terminal, and 65 is a data input terminal. And a data output terminal, and is a half adder for adding 1 to a bit input value.

The operation will be described. When data is input from the fixed value input terminal with the bit input value set for each data input terminal, first, the half adder to which this fixed value input terminal is connected performs the addition operation of the bit input value and the fixed value. Then, the bit increment value is output from the data output terminal. The remaining half adders perform the addition operation of the carry value, the bit input value, and the fixed value in order from the half adder to which the fixed value input terminal is connected, and output the bit increment value from the data output terminal.

[0004]

Since the conventional incrementer is configured as described above, unless the carry value is generated sequentially from the least significant bit of the data, the increment value of the most significant bit of the data is determined. However, there is a problem that an increment value of input data cannot be obtained unless a delay time corresponding to the number of gates corresponding to the number of bits of data handled by the incrementer has elapsed.

Therefore, a technique for reducing the propagation delay time of the carry value from the least significant bit to the most significant bit of data has been proposed in the past.

FIG. 15 is a block diagram showing the structure of a conventional incrementer having a carry look ahead circuit. In the figure, 1 is a data input terminal, 2 is a data output terminal, 66 is a data input terminal 1 corresponding to the least significant bit of input data, and a fixed value "1" is added to this input value. A fixed value addition operation block 67 for outputting the operation result from the data output terminal 2 of the least significant bit of the output data is connected to an arbitrary one data input terminal 1 of the input data, and the data is arranged in the bit arrangement direction. Is a carry-up value addition operation block for inputting a carry-up value from the lower block, adding the carry-up value to this input value, and outputting the operation result from an arbitrary data output terminal 2 of output data.

Reference numeral 5 denotes a selector to which a carry value for each of four blocks continuous in the data bit arrangement direction is input. Reference numeral 6 denotes a selector provided in correspondence with each selector 5. If the block-by-block switching signals output from the four blocks 67 are all “1”, a significant switching signal is output to the selector 5.
Is a switching signal generation circuit that outputs the switching signal.

FIG. 16 is a circuit diagram showing a fixed value addition operation block in the conventional incrementer. In the figure, reference numeral 7 denotes a first bit input terminal to which a bit input value of a least significant bit of data to which a fixed value “1” is added is input;
9 is a first bit output terminal from which the bit increment value of the least significant bit of the output data is output, 11 is connected between the first bit input terminal 7 and the first bit output terminal 9,
A fixed value addition inverter that inverts the bit input value input from the first bit input terminal 7 and outputs the inverted value as a bit increment value to the first bit output terminal 9. A carry value output terminal 15 outputs a carry value of the block 66, and a switching signal output terminal 15 outputs an input value of the first bit input terminal 7 as a block-by-block switching signal of the block 66.

FIG. 17 is a circuit diagram showing a carry-up value addition operation calculation block in this conventional incrementer. In the figure, 16 is a first bit input terminal, 18 is a first bit output terminal, 20 is a carry value input terminal connected to the carry value output terminals 14 and 26 of the lower block, and 21 is a carry value input terminal 20. A first bit input terminal 16 is connected, an exclusive OR of the input values of these two terminals 16 and 20 is calculated, and the calculation result is output to a first bit output terminal 18 as a bit increment value for a first bit. The exclusive OR operation circuit 22 is connected to the carry value input terminal 20 and the first bit input terminal 16 and calculates the logical product of the input values of these two terminals 16 and 20.
A first bit carry-and-arithmetic circuit for outputting the result of this calculation as a carry value, 26 is a carry value output terminal for outputting the carry value as a carry value of this block 67, and 27 is a first bit input terminal 16. A switching signal output terminal for outputting an input value as a block-by-block switching signal of the block 67.

The operation will be described. When input data is input from a plurality of data input terminals 1, first, the fixed value addition inverter 11 of the 2-bit fixed value addition operation block 66 outputs the least significant bit of the input data input from the first bit input terminal 7. The bit input value is inverted and output from the data output terminal 2 via the first bit output terminal 9. Therefore, the first bit output terminal 9 outputs a bit increment value obtained by adding the fixed value “1” to the bit input value of the first bit input terminal 7.

At the same time, the carry-up value addition operation block 67, which is the second block from the lowest side, operates. Specifically, the exclusive OR operation circuit 21 for the first bit in the block 67 performs an exclusive OR operation on the carry value of the fixed value addition operation block 66 and the bit input value input to the second data input terminal 1. And if one of the values is “1”, the bit increment value of “1” is output to the second data output terminal 2 via the first bit output terminal 18. At the same time, the logical product operation circuit 22 for calculating the carry value of the first bit carries out the lower block 3
AND operation of the carry-up value from the above and the second bit input value is performed, and if both are "1", the carry-up value of the second bit of "1" is output.

When the carry value from the lower bit is determined as described above, the bit increment value of the bit is output from the data output terminal 2 in accordance with the determination, and this operation is performed from the lower side to the upper side in the data array direction. By sequentially determining the carry value, the increment value of the input data is output from the data output terminal 2.

The above operation is performed in each block 66.
, While each block 66, 67
When a switch signal for each block is output from the switch group, a switch signal is output from the switch signal generation circuit 6. In response to this, the selector 5 sets the carry value of the most significant bit in the block group and the carry value from the lower block group. Is selected, and this is selected as the upper block 6
It is output as a carry-up value to 7.

Therefore, in the incrementer according to the first embodiment, since the selector 5 and the switching signal generating circuit 6 are provided for every four blocks, the carry value is propagated to the upper side earlier by that amount, and the increment of the upper side is performed. The value can be determined.

However, even if such a selector 5 is used, if the carry value from the lower bit arrives before the switching signal generating circuit 6 outputs the switch signal, the higher bit of the carry value is thereby changed. Therefore, if the propagation speed is to be increased, the propagation speed of the carry value between the selectors 5 and 5 is increased from the lower side. Must be faster than the propagation speed of the data, and as a result, a large number of selectors 5 must be provided to divide the data into small numbers of bits. When a large number of selectors 5 are provided in this manner, the operation delays of the large number of selectors 5 are cumulatively added, thereby limiting the propagation speed of the carry value to the upper bits. Will be lost. Therefore, even if such a selector 5 is used, there is naturally a limit in increasing the speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and can increase the propagation speed of the carry value to the upper bits by a completely different approach from the case where a selector is used. It is another object of the present invention to provide an incrementer which can realize an increment processing speed which cannot be obtained conventionally by combining the selector with the selector in a specific form.

[0017]

The incrementer according to the present invention receives a bit input value of a certain bit and a carry value from a bit lower than the certain bit, and performs an AND operation of these values. A plurality of carry value calculating logic circuits for outputting a carry value to a bit one bit higher than the bit in accordance with the result of the operation, and a bit input value of the bit and a carry value from the lower bit being input And
A plurality of bit value operation logic circuits that perform these exclusive OR operations and output the bits as increment values in accordance with the operation results, and add a predetermined fixed value to data composed of a plurality of bits. In an incrementer that outputs data including a plurality of increment values,
A bit input value of a plurality of continuous bits is input, a logical product of these is performed, and a multi-bit operation value operation logic circuit that outputs a multi-bit operation value in accordance with the operation result; The carry value to the least significant bit of the above and the multi-bit operation value are input, and a logical AND operation thereof is performed, and a multi-bit carry value according to the operation result is the most significant bit of the plurality of consecutive bits. And a multi-bit carry value operation logic circuit that outputs a carry value from the upper bit.

The incrementer according to the present invention has a certain
The bit input value of one bit and the carry value from the next lower bit are input, and a logical AND operation of these is performed, and the carry up to a bit higher than the relevant bit is performed according to the result of the operation. A plurality of carry value calculation logic circuits for outputting values, a bit input value of the above bit and a carry value from the lower bit are input, exclusive OR operation is performed on these, and the corresponding bit is calculated according to the calculation result. When a plurality of bit value operation logic circuits that are output as increment values of and a bit input value of a plurality of consecutive bits are input, an AND operation of these is performed, and when all the bits are the maximum value of the bits, A switching signal generating circuit for outputting a switching signal; a carry value to a least significant bit of the plurality of consecutive bits; The carry value from the most significant bit is input, and normally the carry value from the most significant bit is output as the carry value from the most significant bit of the plurality of consecutive bits, and the switching signal is input. A selector that outputs a carry value to the least significant bit as a carry value from the most significant bit, and a data consisting of a plurality of increment values by adding a predetermined fixed value to data consisting of a plurality of bits. In the incrementer that outputs a, a bit input value of at least two or more consecutive bits of the plurality of consecutive bits is input, an AND operation of these is performed, and a multi-bit operation value is calculated according to the operation result. A multi-bit operation value operation logic circuit to be output, and a plurality of continuous The carry value to the least significant bit of the bit and the multi-bit operation value are input, and a logical AND operation of these is performed, and a multi-bit carry value according to the operation result is used for the multi-bit operation value operation. And a logic circuit for calculating a multi-bit carry value which is output as a carry value from the most significant bit of a plurality of consecutive bits input to the logic circuit.

In the incrementer according to the present invention, the multi-bit operation value operation logic circuit receives a bit input value of 2 to 4 bits.

In the incrementer according to the present invention, the number of input bits of the multi-bit operation value operation logic circuit is different for each unit divided by the selector.

[0021] In the incrementer according to the present invention, the multi-bit operation value operation logic circuit uses a bit higher than the bit to which the fixed value is added as the bit input value.

The incrementer according to the present invention includes a fixed value addition bit position selection circuit for exclusively selecting one bit from among a plurality of bits to determine the position of a bit to which a fixed value is to be added. The bit operation value operation logic circuit uses the most significant bit or a higher order bit among the plurality of bits on which the fixed value addition operation is performed as the bit input value.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of an incrementer to which data consisting of a plurality of bits is input according to the first embodiment of the present invention. In the figure, 1 is a data input terminal to which a bit input value of input data having a value of “0” (low level, the same applies hereinafter) or “1” (high level, the same applies hereinafter) is input, and 2 is a 0 A data output terminal 3 for outputting a bit increment value of output data having a value of "1" or "1" is connected to two data input terminals 1 corresponding to the two least significant bits of the input data. A 2-bit input value for adding a fixed value "1" to a 2-bit input value input from the input terminal 1 and outputting the operation result from the two least significant 2 bits of the output data from the two data output terminals 2 The fixed value addition operation block 4 is connected to two data input terminals 1 corresponding to arbitrary two bits of the input data, respectively, and is a lower block in the data bit arrangement direction. A carry value is input from the data input terminal, a carry value is added to the 2-bit input value input from the two data input terminals 1, and the operation result is output to any two data output terminals of output data. 2 is a 2-bit carry value addition operation block output from 2.

The incrementer according to the first embodiment is divided into four blocks (eight bits) (division unit) from the least significant bit of data, and a carry look ahead circuit is provided for each of the four blocks. . Hereinafter, the four blocks serving as the division unit are collectively referred to as a block group. In the figure, reference numeral 5 denotes a selector to which carry-up values of two sets of blocks continuous in the data bit arrangement direction are input, and 6 denotes four blocks of the higher-order block group, which are provided corresponding to the respective selectors 5. If all the block-by-block switching signals output from 4 are “1”, a significant switching signal is output to the selector 5.
Is a switching signal generation circuit that outputs the switching signal.

FIG. 2 is a circuit diagram showing a 2-bit fixed value addition operation block 3 according to the first embodiment of the present invention.
In the figure, reference numeral 7 denotes a first bit input terminal to which a bit input value of a least significant bit of data to which a fixed value “1” is added is input, and 8 denotes a bit input value of a bit one bit higher than the least significant bit Is a second bit input terminal, 9 is a first bit output terminal from which a bit increment value of the least significant bit of the output data is output, and 10 is a bit increment value of a bit one bit higher than the least significant bit. The output second bit output terminal 11 is the first bit input terminal 7
A fixed value addition inverter connected between the first bit output terminal 9 and the inverter for inverting a bit input value input from the first bit input terminal 7 and outputting the inverted bit input value to the first bit output terminal 9 as a bit increment value; Reference numeral 12 denotes a connection between the first bit input terminal 7 and the second bit input terminal 8;
The exclusive OR of the bit input values of the two terminals 7 and 8 is calculated,
A second-bit exclusive OR operation circuit (bit value operation logic circuit) that outputs the operation result to the second bit output terminal 10 as a bit increment value.

Reference numeral 13 denotes a connection between the first bit input terminal 7 and the second bit input terminal 8, and these two terminals 7,
A logical AND operation circuit for a second bit carry value operation (a carry value operation logic circuit) for calculating a logical product of the bit input values of 8 and outputting the result of the operation as a carry value of the second bit. A carry value output terminal for outputting a carry value of a bit as a carry value of the block 3;
A switching signal output terminal 15 outputs the carry value of the second bit as a switching signal for each block of the block 3.

FIG. 3 is a circuit diagram showing a 2-bit carry value addition operation calculation block 4 according to the first embodiment of the present invention. In the figure, reference numeral 16 denotes a first bit input terminal to which a bit input value of the lowest bit of the two bits input to the block 4 is input, and 17 denotes a first bit input terminal to which two bits input to the block 4 are input. A second bit input terminal to which a bit input value of a second bit from the bottom is input;
Reference numeral 18 denotes a first bit output terminal for outputting a bit increment value corresponding to the lowest bit, 19 denotes a second bit output terminal for outputting a bit increment value corresponding to the second bit from the bottom, 20 Is a carry value input terminal connected to the carry value output terminals 14 and 26 of the lower block, 21 is a carry value input terminal 20 connected to the first bit input terminal 16, and these two terminals 1
Exclusive OR operation circuit for first bit (bit value operation logic circuit), which calculates the exclusive OR of the input values of 6, 6 and 20, and outputs the operation result to the first bit output terminal 18 as a bit increment value; Is connected to the carry-up value input terminal 20 and the first bit input terminal 16, calculates the logical product of the input values of these two terminals 16 and 20, and outputs the result of the calculation from the lower one, which is one higher than that. A first bit carry value operation AND circuit (bit value operation logic circuit) which outputs a carry value to the second bit is connected to the second bit input terminal 17 from the bottom and is connected to the second from the bottom. The carry value for the th bit is entered,
A second-bit exclusive-OR operation circuit (a bit-value operation logic circuit) that performs an exclusive-OR operation on these two input values and outputs the operation result to the second bit output terminal 19 as a bit increment value.

The reference numeral 24 denotes a connection between the lowest bit connection terminal 16 which is all the bits input to the block 4 and the connection terminal 17 of the second bit from the bottom, and performs a logical product operation on these. A multi-bit operation value operation logic circuit 25 for outputting a multi-bit operation value in accordance with the operation result; 25 is connected to the carry-up value input terminal 20 and receives the multi-bit operation value; A multi-bit carry value calculating logic circuit for performing a logical product operation and outputting the result of the calculation as a carry value of the most significant bit (the second bit from the bottom) of the block 4; 26 is a carry value of the most significant bit Is a carry-up value output terminal for outputting the carry-up value of the block 4 as a carry-up value of the block 4. Tsu is a switching signal output terminal for outputting a distinction switching signal.

Next, the operation will be described. When input data is input from a plurality of data input terminals 1, first, the fixed value addition inverter 11 of the 2-bit fixed value addition operation block 3 outputs the least significant bit of the input data input from the first bit input terminal 7. The bit input value is inverted and output from the data output terminal 2 via the first bit output terminal 9. Therefore, the first bit output terminal 9 outputs a bit increment value obtained by adding the fixed value “1” to the bit input value of the first bit input terminal 7.

At the same time, the exclusive OR operation circuit 12 for the second bit performs an exclusive logical operation based on the two bit input values input from the first bit input terminal 7 and the second bit input terminal 8, When one of the values is “1”, data of “1” is output to the second bit output terminal 10. At the same time, the AND operation circuit 13 for second bit carry value operation performs AND operation based on the bit input values of the first bit input terminal 7 and the second bit input terminal 8, and both of them are “1”. In the case of, "1" is output as the carry value of the second bit.

Next, a 2-bit carry value addition operation block 4, which is the second block in which the carry value input terminal 20 is connected to the carry value output terminal 14 of the 2-bit fixed value addition operation block 3, operates. . In particular,
Exclusive OR operation circuit 21 for first bit of block 4
Performs an exclusive OR operation on the carry-up value of the 2-bit fixed value addition operation block 3 and the bit input value input to the third data input terminal 1, and one of the values is "1"
, The bit increment value of “1” is output to the third data output terminal 2 via the first bit output terminal 18. At the same time, the AND operation circuit 22 for the first bit carry value operation performs a logical AND operation of the carry value from the lower block 3 and the third bit input value, and these are both "1". In this case, the carry value of the third bit of “1” is output, and the multi-bit operation value operation logic circuit 24 outputs the third bit input value, which is all the bits input to the block 4, and the fourth bit. AND operation is performed with the bit input value of, and when both are "1", a multi-bit operation value of "1" is output.

Next, the exclusive-OR operation circuit 23 for the second bit of the block 4 performs an exclusive-OR operation on the output of the carry-up value to the second and the fourth bit input value input to the second data input terminal 17. The sum operation is performed, and when one of the values is “1”, the bit increment value of “1” is output from the fourth data output terminal 2 via the second bit output terminal 19. At the same time, the multi-bit carry value operation logic circuit 25 performs a logical product operation of the carry value from the second bit and the multi-bit operation value, and when both are “1”, “1” is obtained. Is output as the carry value of the fourth bit.

When the carry value from the lower bit is determined in this manner, the bit increment value of the bit is output from the data output terminal 2 in response to the determination, and this operation is performed from the lower side to the upper side in the data array direction. By sequentially determining the carry value, the increment value of the input data is output from the data output terminal 2.

Such an operation is performed in each block 3,
4, while a switching signal for each block is output from each of the blocks 3 and 4, a switching signal is output from the switching signal generation circuit 6, and in response to this, the selector 5 sets the most significant bit in the block group. , And one of the carry values from the lower block group, and outputs this as the carry value to the block 4 connected to the upper block. More specifically, when a block-by-block switching signal having a value of “1” is output from all the blocks 4 in the block group, a switching signal having a value of “1” is output from the switching signal generation circuit 6. The selector 5 selects the carry value from the lower block group and outputs this as the carry value to the block 4 connected to the upper block. Conversely, when any one of the block-by-block switching signals of “0” is output, the switching signal generation circuit 6 outputs a switching signal of “0”,
In response to this, the selector 5 selects the carry value of the most significant bit in the block group and outputs this as the carry value to the block 4 connected to the higher order. Note that the carry value of the most significant bit in the block group selected under such conditions is always "0", and a significant carry value is not actually output from the selector 5.

Therefore, in the incrementer according to the first embodiment, in each block 4, a multi-bit operation value operation logic circuit 24 and a multi-bit carry value operation logic circuit 2
Therefore, although 2 bits of data are input to each block 4, the delay time of one logical operation circuit after the carry-up value is input from the lower block is obtained. The carry value can be determined and output for the upper block.

In combination with the provision of the selector and the switching signal generation circuit for every four blocks, for example, in the case of a conventional incrementer for sequentially determining the carry value, each selector 5 Until the carry-up value, which is the output of (1), is determined (the carry-up value calculation is
Times) or 23 (the carry-up value calculation is 23 times) logical operation circuits, but 5 carry-outs (the carry-up value calculation of the four lowest blocks and the selector 1) ) Or six (the lower four blocks and two selectors) logic operation circuits, the value of which can be determined. Until the carry value to the most significant bit is determined. , The number is remarkably reduced from 27 (15 carry-up operations) to 8 (4 lowermost blocks, 2 selectors and 2 uppermost blocks). .

As described above, according to the first embodiment, two consecutive bit input values are input, a logical AND operation is performed, and a multi-bit operation value is output according to the operation result. Multi-bit operation value operation logic circuit 24
And the carry value to the least significant bit of the two bits and the multi-bit operation value are input, perform an AND operation of these, and carry the operation result from the most significant bit of the two bits Since the multi-bit carry value calculation logic circuit 25 that outputs a value is provided, even if the carry value to the least significant bit of the two bits is later than the data input timing. ,
Before reaching the carry value, the multi-bit operation value operation logic circuit 24 calculates the multi-bit operation value of the plurality of consecutive bits, and the multi-bit carry value operation logic circuit 25 calculates the carry value to the least significant bit. Has an effect that a carry-up value to a bit several bits higher than the least significant bit can be generated immediately after.

Therefore, as compared with a conventional incrementer in which a circuit similar to the AND operation circuit 25 for multi-bit carry value calculation is provided for each bit, the propagation delay time of the carry value to the higher-order bit is reduced. Thus, the increment processing can be completed earlier than the conventional one.

In particular, since the delay time until a carry value is generated in one division unit (block group) divided by the selector 5 is shortened, it can be included in this division unit accordingly. Even if the number of bits is increased (here, the number of bits is increased to 8 bits), a carry value within the division unit is generated before a carry value from the lower part of the division unit is carried forward. Can be. Therefore, in the conventional case in which a plurality of bits are simply divided only by the selector 5 to increase the speed (for example, 4 bits).
The number of bits that can be included in one division unit (block group) divided by the selector 5 can be increased (for example, from 4 to 8) as compared with the case where a block is input with 4 bits. Can be)
As a result, the number of data divisions by the selector 5 can be reduced as a whole of the incrementer, and as a result, the carry value to the higher-order bits can be further increased as compared with the conventional case where a plurality of bits are simply divided by the selector 5. There is an effect that the propagation delay time can be shortened and an increment processing speed that can not be obtained by the conventional device can be realized.

Embodiment 2 FIG. 4 is a block diagram showing a configuration of an incrementer to which data consisting of a plurality of bits is input according to the second embodiment of the present invention. In the figure, reference numeral 28 denotes 3 corresponding to the least significant 3 bits of the input data.
The three data input terminals 1 are connected, a fixed value "1" is added to the 3-bit input value input from the three data input terminals 1, and the operation result is added to the least significant three bits of the output data. A 3-bit fixed value addition operation block 29 for outputting to the corresponding three data output terminals 2 is connected to three data input terminals 1 corresponding to arbitrary three bits of the input data, respectively, and at the lower side in the data array. The carry-up value from the block is input.
A 3-bit carry-up operation for adding a carry value to a 3-bit input value input from one of the data input terminals 1 and outputting the operation result to three data output terminals 2 corresponding to arbitrary 3 bits of output data This is a value addition operation block.

FIG. 5 is a circuit diagram showing a 3-bit fixed value addition operation block 28 according to the second embodiment of the present invention. In the figure, reference numeral 30 denotes a third bit input terminal to which a bit input value of a bit two higher bits than the least significant bit is input, and 31 denotes a bit increment value of a bit two bits higher than the lowest bit. The third bit output terminal 32 is connected to the first bit input terminal 7 and the second bit input terminal 8 and calculates the logical product of the input values of these two terminals 7 and 8, and calculates the result of this operation. A second bit carry value operation AND circuit (carry value operation logic circuit) which outputs a carry value to the third bit from the bottom, which is one higher order, and 33 is connected to the third bit input terminal 30. At the same time, the carry value to the third bit from the bottom is input, the exclusive OR of these two input values is calculated, and the calculation result is output to the third bit output terminal 31 as a bit increment value. A third bit for exclusive operation circuit for outputting (bit value calculation logic circuit).

Reference numeral 34 is connected to the first bit input terminal 7, the second bit input terminal 8, and the third bit input terminal 30, and calculates the logical product of the bit input values of these three terminals 7, 8, 30. A third-bit carry-value operation AND circuit (carry-value operation logic circuit) for outputting the result of this operation as a carry-up value of the third bit. The carry-value output terminal 14 and the switching signal output terminal 15 The carry value of the third bit is output.

FIG. 6 is a circuit diagram showing a 3-bit carry value addition operation calculation block 29 according to the second embodiment of the present invention. In the figure, 35 is a third bit input terminal to which the bit input value of the third bit from the bottom of the three bits input to the block 29 is input, and 36 corresponds to the third bit from the bottom. A third bit output terminal 37 from which the increment value is output, a carry-up value to the second bit from the bottom and a bit input value of the second bit input terminal 17 are input, and a logical product of these two input values is calculated. A second-bit carry-value operation AND circuit (carry-value operation logic circuit) for outputting the result of this operation as a carry value to the third bit from the bottom, which is one bit higher than that, The 3-bit input terminal 35 is connected, and the carry value to the third bit from the bottom is input. The exclusive OR of these two input values is calculated, and the calculation result is expressed as the third bit. A third bit for exclusive operation circuit for outputting to the force terminal 36 as the bit increment value (bit value calculation logic circuit).

Numeral 39 designates three bit input terminals 16, 1 which are all bits input to the block 29.
7 and 35 are multi-bit operation value operation logic circuits for performing a logical product operation of these and outputting a multi-bit operation value in accordance with the operation result. The multi-bit carry value operation logic circuit 25 The logical product of the multi-bit operation value and the carry value input from the carry value input terminal 20 is calculated,
This operation result is output as a carry value of the most significant bit (third bit from the bottom) of this block, and the switching signal output terminal 27 outputs this multi-bit operation value as a block-by-block switching signal of this block 29.

Next, the operation will be described. In the 3-bit fixed value addition operation block 28, the second bit carry value operation AND circuit 32 operates when the input values of the first bit input terminal 7 and the second bit input terminal 8 are both "1". , Outputs the value of “1” as the carry value to the third bit from the bottom, and the third bit exclusive OR operation circuit 33 outputs the carry value to the third bit from the bottom and the third bit input terminal. When any one of the third bit input values from the bottom 30 is “1”, the data of “1” is output to the third bit output terminal 31.
Further, a logical product operation circuit 34 for third bit carry value operation
Outputs the carry value of the third bit having a value of "1" when all the input values of the first bit input terminal 7, the second bit input terminal 8 and the third bit input terminal 30 are "1". .

In each of the 3-bit carry-value addition operation blocks 29, the second-bit carry-value logical AND operation circuit 37 calculates the input value of the second bit input terminal 17 and the carry value from the second bit from the bottom. When both are “1”, the value of “1” is output as the carry value to the third bit from the bottom, and the third-bit exclusive-OR circuit 38 outputs the value to the third bit from the bottom. Is output to the third bit output terminal 36 when either one of the carry value and the third bit input value from the third bit input terminal 35 is “1”. .
The multi-bit carry value calculating logic circuit 39 sets the value of “1” when all the input values of the first bit input terminal 16, the second bit input terminal 17, and the third bit input terminal 35 are “1”. Is output as the carry value of the third bit. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

Therefore, in the incrementer according to the second embodiment, since each block 29 uses the multi-bit operation value operation logic circuit 39 and the multi-bit carry value operation logic circuit 25, each block 29 has 3 bits. Despite the input of data for bits, the carry value can be determined and output to the upper block with a delay time of one logical operation circuit.

Combined with the provision of the selector 5 and the switching signal generating circuit 6 for every four blocks, for example, a 28-bit input is changed to a 42-bit input while maintaining the processing speed as an incrementer. The number of input bits can be increased. Conversely, if the number of bits is the same, the number of bits in the division unit (block group) divided by each selector 5 is increased, and the processing speed as an incrementer is further improved as compared with the first embodiment. You can do it.

Embodiment 3 FIG. 7 is a block diagram showing a configuration of an incrementer to which data composed of a plurality of bits is input according to the third embodiment of the present invention. In the figure, reference numeral 40 denotes 4 corresponding to the 4 least significant bits of the input data.
The four data input terminals 1 are connected, a fixed value "1" is added to the 4-bit input value input from the four data input terminals 1, and this operation result is added to the least significant four bits of the output data. A 4-bit fixed value addition operation block 41 for outputting to the corresponding four data output terminals 2 is connected to four data input terminals 1 corresponding to arbitrary four bits of the input data, respectively, and is connected to the lower side in the data array. The carry-up value from the block is input.
A 4-bit carry-up operation for adding a carry value to a 4-bit input value input from one data input terminal 1 and outputting the operation result to two data output terminals 2 corresponding to arbitrary 4 bits of output data This is a value addition operation block.

FIG. 8 is a circuit diagram showing a 4-bit fixed value addition operation block 40 according to the third embodiment of the present invention. In the figure, reference numeral 42 denotes a fourth bit input terminal to which a bit input value of a bit three bits higher than the least significant bit is input, and 43 denotes a bit increment value of a bit three bits higher than the least significant bit. The fourth bit output terminal 44 receives the input value of the third bit input terminal 30 and the carry-up value to the third bit, calculates the logical product of these two input values, and outputs the result of this operation. A third-bit carry-value operation AND circuit (carry-value operation logic circuit) that outputs a carry value to the fourth bit from the bottom, which is one higher order, and 45 is a fourth bit input terminal 42 from the bottom At the same time, the carry value to the fourth bit from the bottom is input and the exclusive OR of these two input values is calculated. The result of this calculation is bit-incremented to the fourth bit output terminal 43. Fourth bit for exclusive operation circuit for outputting a cement value (bit value calculation logic circuit)
It is.

Reference numeral 46 denotes a first bit input terminal 7, a second bit input terminal 8, a third bit input terminal 30, and a fourth bit input terminal 42, which are connected to each other.
A fourth-bit carry-value operation logical product operation circuit (a carry-value operation logic circuit) for calculating a logical product of the bit input values of 8, 30, and 42 and outputting the result of the calculation as a carry value of the fourth bit. The carry value output terminal 14 and the switching signal output terminal 15 output the carry value of the fourth bit.

FIG. 9 is a circuit diagram showing a 4-bit carry value addition operation calculation block 41 according to the third embodiment of the present invention. In the figure, reference numeral 47 denotes a fourth bit input terminal to which a bit input value of the fourth lowermost bit of the four bits input to the block 41 is input, and 48 corresponds to the fourth lowermost bit. The fourth bit output terminal from which the bit increment value is output, 49 is 3
Carry-up value to the third bit and third bit input terminal 35
The third bit carry-out calculates the logical product of these two input values and outputs the result of this operation as a carry-up value to the fourth bit from the bottom, which is one higher order. A logical AND circuit for value operation (logic circuit for carry value operation) 50 is connected to the fourth bit input terminal 47 from the bottom and receives the carry value to the fourth bit from the bottom, and these two bits are input. A fourth-bit exclusive-OR operation circuit (a bit-value operation logic circuit) that performs an exclusive-OR operation on the input value and outputs the operation result to the fourth bit output terminal 48 as a bit increment value.

Reference numeral 51 denotes four bit input terminals 16, 1 which are all bits input to the block 41.
7, 35 and 47 are connected, perform a logical product operation thereof, and output a multi-bit operation value in accordance with the operation result. The multi-bit operation value operation logic circuit 25 includes a multi-bit carry value operation logic circuit 25. Calculates the logical product of the multi-bit operation value and the carry value input from the carry value input terminal 20, and uses the result of this operation as the carry value of the most significant bit (fourth bit from the bottom) of this block 41. The switching signal output terminal 27 outputs the multi-bit operation value as a block-by-block switching signal of the block 41.

Next, the operation will be described. In the 4-bit fixed-value addition operation block 40, the third-bit carry-value operation AND circuit 44 has the carry-up value to the third bit and the input value of the third bit input terminal 30 both "1". At this time, a value of “1” is output as a carry value to the fourth bit from the bottom, and the exclusive OR operation circuit 45 for the fourth bit outputs the carry value to the fourth bit from the bottom and the fourth bit input. When one of the fourth bit input values from the terminal 42 input from the terminal 42 is “1”, a bit increment value of “1” is output to the fourth bit output terminal 48. Further, the AND operation circuit 46 for the fourth bit carry value operation is such that all the input values of the first bit input terminal 7, the second bit input terminal 8, the third bit input terminal 30, and the fourth bit input terminal 42 are "1". , A carry value of the fourth bit having a value of “1” is output.

Further, in each 4-bit carry-value addition operation block 41, the third-bit carry-value operation AND circuit 49 calculates the input value of the third bit input terminal 35 and the carry value to the third bit from the bottom. When both are “1”, the value of “1” is output as a carry value to the fourth bit from the bottom, and the exclusive OR circuit for the fourth bit 50 outputs the value to the fourth bit from the bottom. When either one of the carry value and the fourth bit input value from the fourth bit input terminal 47 is “1”, the bit increment value of “1” is output to the fourth bit output terminal 48. Output. The multi-bit operation value operation logic circuit 51 includes a first bit input terminal 16 and a second bit input terminal 1.
7. When all the input values of the third bit input terminal 35 and the fourth bit input terminal 47 are “1”, a carry value of the fourth bit having the value of “1” is output. Other operations are the same as those in the second embodiment, and a description thereof will be omitted.

Therefore, in the incrementer according to the third embodiment, since each block 41 uses the multi-bit operation value operation logic circuit 51 and the multi-bit carry value operation logic circuit 25, each block 41 has four bits. Despite the input of data for bits, the carry value can be determined and output to the upper block with a delay time of one logical operation circuit.

In combination with the provision of the selector 5 and the switching signal generating circuit 6 for every four blocks, for example, a 28-bit input is changed to a 56-bit input while maintaining the processing speed as an incrementer. The number of input bits can be increased. Conversely, if the number of bits is the same, the number of bits in the division unit (block group) divided by each selector 5 is increased, and the processing speed as an incrementer is further improved as compared with the second embodiment. You can do it.

Embodiment 4 FIG. 10 is a block diagram showing a configuration of an incrementer to which data consisting of a plurality of bits is input according to the fourth embodiment of the present invention. In the figure, the configuration of each part is the same as that described in the first to third embodiments, and the same reference numerals are given and the description is omitted.

Then, as described above, each of the blocks 4, 2
Since the number of input bits of 9 and 41 is limited from two to four, the number of input bits of the multi-bit operation value operation logic circuits 24, 39 and 51 in each of the blocks 4, 29 and 41 is two.
The number can be limited to four. Therefore, an arithmetic circuit having five or more inputs generally causes problems such as a reduction in processing speed as an arithmetic circuit and an increase in the area occupied on a chip.
When used as 4, 39, 51, there is a high possibility that it becomes impossible to appropriately secure a margin of the output timing of the multi-bit operation value with respect to the input timing of the carry value from the lower order. It is possible to increase the speed of the increment processing without causing any problem, and there is an effect that the increment processing speed can be realized with the delay time expected in the propagation path of the carry value from the lower bit to the upper bit.

According to the fourth embodiment, the number of input bits of the multi-bit operation value operation logic circuits 24, 39, 51 is determined by the unit (block group) divided by the selector 5.
For example, the delay of the carry value from the least significant bit input to the most significant bit output in the division unit (block group) of each selector 5 and the most significant value from the input of the carry value from the lower block are different from each other. There is an effect that the propagation path can be designed so as to optimize the delay of the carry value up to the upper bit output.

Embodiment 5 FIG. 11 is a block diagram showing a configuration of an incrementer to which data composed of a plurality of bits is input according to the fifth embodiment of the present invention. As shown in the figure, in the incrementer of the fifth embodiment, 2
The fixed value addition operation block 3 for the bit is the third input bit.
It is provided corresponding to the fourth and fourth. The configuration of each unit is the same as that of the first embodiment, and the description is omitted.

Therefore, in the fifth embodiment, since "1" is added to the third bit of the input data, a fixed value "4" is added to the input data.

The third value to which the fixed value is added as described above
By providing the multi-bit operation value operation logic circuit 24 in correspondence with the higher-order bits than the third bit, unnecessary operation processing of bits below the fixed value addition bit can be eliminated. There is an effect that the arithmetic processing speed can be increased.

Embodiment 6 FIG. FIG. 12 is a block diagram showing a configuration of an incrementer to which data composed of a plurality of bits is input according to the sixth embodiment of the present invention. In the figure, reference numeral 52 denotes a control signal input terminal, and 53 denotes a 2-bit variable value addition operation block (fixed value addition bit position selection circuit) to which the control signal is input.

FIG. 13 shows a second embodiment according to the sixth embodiment of the present invention.
FIG. 3 is a circuit diagram showing a variable value addition operation block for bits.
In the figure, 54 is a first control signal terminal to which a first control signal is input, 55 is a second control signal terminal to which a second control signal is input, and 56 is a third control signal terminal to which a third control signal is input , 57 are connected to the first bit input terminal 7 and the second control signal terminal 55, calculate the exclusive OR of these, and output the calculation result from the first bit output terminal 9 to the first bit exclusive OR. Arithmetic circuit (bit value arithmetic logic circuit),
58 is a control first OR operation circuit which is connected to the first bit input terminal 7 and the first control signal terminal 54, performs an OR operation on them, and outputs the operation result as a first bit provisional carry value; 59 is connected to the first control signal terminal 54 and the second control signal terminal 55, and calculates the logical sum of these,
A control second OR operation circuit 60 for outputting the operation result as a carry-prevention signal, 60 performs a logical AND operation of the provisional carry value of the first bit and the carry-prevention signal, and carries the operation result to a carry value to the second bit. Is a logical product operation circuit for carrying a first bit carry value (a carry circuit for carrying a carry value).

Reference numeral 61 denotes a second bit input terminal 8 connected thereto and a first bit provisional carry value input thereto.
A control first AND operation circuit for performing an AND operation of these values and outputting the operation result as a provisional carry value of a second bit, 62 performs a logical AND operation of the second provisional carry value and the carry inhibition signal , And outputs the operation result as a carry-up value of a second bit. A logical AND circuit for carry-up of a second bit carry value (logic circuit for carry-up value operation), 63
Is connected to the third control signal terminal 56 and
This is a control third OR circuit that receives a carry value of a bit, performs an OR operation on these, and outputs the operation result. The carry value output terminal 14 outputs the output value of the third control OR circuit 63 as a carry value of the block 53, and the switching signal output terminal 15 outputs the provisional carry value of the second bit to the block 53. Output as a switching signal for each block. The other configuration is the same as that of the first embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. First, according to the variable value to be added to the input data based on Table 1 below,
The levels of three control signals input to the 2-bit variable value addition operation block 53 are determined. However, in this table, L means low level "0" and H means high level "1".
Means

[0068]

[Table 1]

For example, when adding the variable value "2", the first control signal is set to a high level, the second control signal is set to a low level, and the third control signal is set to a low level. When such a control signal is set,
High level "1" regardless of the input value input to the first bit input terminal 7 from the control first OR operation circuit 58
Is output, the control second OR circuit 59 also outputs a high-level "1" carry value blocking signal, and the first bit carry value arithmetic circuit for carrying the first bit carry value From 60, the carry value of the high level “1” to the second bit is output. Accordingly, the exclusive OR operation circuit 12 for the second bit inverts the bit input value input from the second bit input terminal 8 and outputs the inverted value from the second bit output terminal 10. Since the second control signal is at the low level, the exclusive OR operation circuit 57 for the first bit outputs the bit input value input from the first bit input terminal 7 as it is from the first bit output terminal 9.

The first bit provisional carry value is "1".
Therefore, the control first AND operation circuit 61 outputs the same value as the input value from the second bit input terminal 8 as a provisional carry value of the second bit, and furthermore, the carry prevention signal is “1”. Therefore, the AND operation circuit for second bit carry value operation outputs the same value as the input value from the second bit input terminal 8 as the carry value of the second bit. And
Since the third control signal is at the low level “0”, the same value as the input value from the second bit input terminal 8 is output from the third control OR circuit 63 as a carry value to the upper block 4. Therefore, when the input value from the second bit input terminal 8 is “1”, a carry value having a value of “1” is output, and the input value from the second bit input terminal 8 is “0”.
In this case, a carry value having a value of "0" is output. Note that under this setting, the carry value does not change with the input value of the first bit input terminal 7.

According to Table 1, the variable value is set to “0”,
The operation when “1” and “4” are performed is as follows.
The description is omitted because it can be considered in the same way as the case described above.

Therefore, according to the sixth embodiment, the position of the bit to which the variable value is added is determined by exclusively selecting one bit from among the three least significant bits.
Variable values to be added to input data are "1,""2," and "4."
Can be switched between.

Moreover, the multi-bit operation value operation logic circuit 2
4 uses the most significant bit (that is, the third bit) of the plurality of bits on which the addition operation of the variable value is performed as its bit input value. On the other hand, even when the variable value is added, the input timing of the carry value from the lower order can be prevented from being earlier than the output timing of the multi-bit operation value. Therefore, the effect that the increment processing speed can be realized within the delay time expected in the propagation path of the carry value from the least significant bit to the most significant bit of the plurality of bits on which the addition of the variable value is performed. There is.

[0074]

As described above, according to the present invention, a bit input value of a plurality of consecutive bits is input, a logical AND operation is performed on these, and a multi-bit operation value is output according to the operation result. A multi-bit operation value operation logic circuit, a carry value to the least significant bit of the plurality of consecutive bits, and the multi-bit operation value are input, and a logical AND operation of these is performed. A multi-bit carry value calculation logic circuit for outputting the multi-bit carry value as a carry value from the most significant bit of the plurality of consecutive bits. Even in the case where the carry value to the bit is delayed from the data input timing, the multi-bit operation value operation logic circuit sets the plurality of continuous values before the carry value reaches the carry value. The multi-bit carry value calculation logic circuit generates a carry value to a bit several bits higher than the least significant bit as soon as the carry value to the least significant bit arrives. There is an effect that can be.

Therefore, the propagation delay time of the carry value to the upper bits can be reduced as compared with the conventional incrementer using only the carry value calculation logic circuit, and the increment processing can be performed faster than the conventional one. There is an effect that can be completed.

According to the present invention, a switching signal for receiving a bit input value of a plurality of consecutive bits, performing a logical AND operation on them, and outputting a switching signal when all bits have the maximum value of the bits. A generation circuit and a carry value to the least significant bit of the plurality of consecutive bits and a carry value from the most significant bit of the plurality of consecutive bits are input, and usually, The carry value is output as a carry value from the most significant bit of the plurality of consecutive bits, and when the switching signal is input, the carry value to the least significant bit is carried from the most significant bit. Along with the selector outputting the value, the bit input value of at least two or more consecutive bits of the plurality of consecutive bits is input. A multi-bit operation value operation logic circuit that performs a logical product operation of these and outputs a multi-bit operation value in accordance with the operation result; A carry value to the least significant bit of the bits and the multi-bit operation value are input, an AND operation of these is performed, and a multi-bit carry value according to the operation result is the multi-bit operation value operation logic circuit. And a multi-bit carry-value operation logic circuit that outputs a carry value from the most significant bit of a plurality of consecutive bits input to the Even when the value is delayed from the data input timing, the multi-bit operation value operation logic circuit sets the plurality of consecutive bits before reaching the carry value. The bit operation value is calculated, and the logic circuit for multi-bit carry value operation can generate a carry value to a bit several bits higher than the least significant bit as soon as the carry value to the least significant bit reaches. effective.

Since the delay time until the carry value is generated in one division unit divided by the selector can be shortened, the bits that can be included in this division unit are correspondingly reduced. Even if the number is increased, a carry value in the division unit can be generated before a carry value from a lower level than the division unit is carried forward. Therefore, the number of bits that can be included in one division unit divided by the selector can be increased as compared with the conventional case where the speed is increased by simply dividing a plurality of bits by the selector. Thus, the number of data divisions by the selector can be reduced as a whole of the incrementer, and as a result, the propagation delay to the upper bits of the carry value can be further reduced as compared with the conventional case where a plurality of bits are simply divided by the selector. This has the effect of shortening the time and realizing an increment processing speed that could not be obtained with the conventional device.

According to the present invention, the number of input bits of the multi-bit operation value operation logic circuit is limited from two to four, so that an operation circuit having five or more inputs generally has a processing speed of the operation circuit. Problems, such as a decrease in the occupied area on the chip and a decrease in the number of bits. Higher speed can be achieved, and there is an effect that the increment processing speed can be realized with the delay time expected in the propagation path of the carry value from the lower bit to the upper bit.

According to the present invention, since the number of input bits of the multi-bit operation value operation logic circuit differs for each unit divided by the selector, for example, from the least significant bit to the most significant bit in the division unit of each selector There is an effect that the delay of the propagation path to the bit output and the delay of the propagation path from the carry value input from the lower block to the most significant bit output can be optimized.

According to the present invention, a fixed value addition bit position selecting circuit for exclusively selecting and determining one bit from among a plurality of bits to determine the position of a bit to which a fixed value is added is provided, and a multi-bit operation is performed. Since the value operation logic circuit uses the most significant bit or the higher order bit of the plurality of bits on which the fixed value addition operation is performed as the bit input value, the A fixed value can be added to any bit,
Moreover, even if the bit for adding such a fixed value is switched, it is possible to prevent the input timing of the carry value from the lower end before the output timing of the multi-bit operation value. There is an effect that the increment processing speed can be realized within the delay time expected in the propagation path of the carry value from the least significant bit to the most significant bit among the plurality of bits on which the fixed value addition operation is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an incrementer to which data consisting of a plurality of bits is input according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a 2-bit fixed value addition operation block according to Embodiment 1 of the present invention;

FIG. 3 is a circuit diagram showing a 2-bit carry value addition operation calculation block according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of an incrementer to which data composed of a plurality of bits is input according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a 3-bit fixed value addition operation block according to Embodiment 2 of the present invention;

FIG. 6 is a circuit diagram showing a 3-bit carry value addition operation calculation block according to a second embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of an incrementer to which data consisting of a plurality of bits is input according to a third embodiment of the present invention;

FIG. 8 is a circuit diagram showing a 4-bit fixed value addition operation block according to Embodiment 3 of the present invention;

FIG. 9 is a circuit diagram showing a 4-bit carry value addition operation calculation block according to Embodiment 3 of the present invention;

FIG. 10 is a block diagram showing a configuration of an incrementer to which data consisting of a plurality of bits is input according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of an incrementer to which data composed of a plurality of bits is input according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of an incrementer to which data composed of a plurality of bits is input according to a sixth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a 2-bit variable value addition operation block according to a sixth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional incrementer.

FIG. 15 is a block diagram showing a configuration of a conventional incrementer having a carry look ahead circuit.

FIG. 16 is a circuit diagram showing a fixed value addition operation block in the conventional incrementer.

FIG. 17 is a circuit diagram showing a carry-up value addition operation calculation block in the conventional incrementer.

[Explanation of symbols]

5 selector, 6 switching signal generation circuit, 12 exclusive OR operation circuit for second bit (logic circuit for bit value operation), 13, 32, 37, 62 AND operation circuit for second bit carry value operation (carry value operation Logic circuit),
21, 57 Exclusive OR operation circuit for first bit (logic circuit for calculating bit value), 22, 60 First-bit AND operation circuit for calculating carry-up value (logic circuit for carry-up value), 24, 39, 51 Logic circuit for calculating a bit operation value, 25 logic circuit for calculating a carry-up value of a multi-bit, 33,
38 exclusive OR operation circuit for third bit (logic circuit for bit value operation), 34, 44, 49 AND operation circuit for third bit carry value operation (logic circuit for carry value operation), 45, 50 fourth bit Exclusive OR operation circuit (bit value operation logic circuit), 46th fourth bit carry value operation AND product operation circuit (carry value operation logic circuit),
53 Variable value addition operation block for 2 bits (fixed value addition bit position selection circuit).

Claims (6)

[Claims] 1. A bit input value of a certain bit and a carry value from a bit below it are input, and
A plurality of carry value calculating logic circuits for performing a logical AND operation thereof and outputting a carry value to a bit one bit higher than the bit in accordance with the result of the AND operation; a bit input value of the bit and the lower bit , And carry out the exclusive OR operation of these values.
A plurality of bit value operation logic circuits for outputting the incremented value of the bit in accordance with the operation result, and adding a predetermined fixed value to the data of the plurality of bits to output data of a plurality of increment values A multi-bit operation value operation logic circuit that receives a bit input value of a plurality of consecutive bits, performs a logical product operation of these, and outputs a multi-bit operation value in accordance with the operation result; A carry value to the least significant bit of the plurality of consecutive bits and the multi-bit operation value are input, and a logical AND operation of these is performed, and a multi-bit carry value according to the operation result is converted to the plurality of consecutive bits. A multi-bit carry value operation logic circuit for outputting as a carry value from the most significant bit of the bits Mentha. 2. A bit input value of a certain bit and a carry value from a bit below it are input, and
A plurality of carry value calculating logic circuits for performing a logical AND operation thereof and outputting a carry value to a bit one bit higher than the bit in accordance with the result of the AND operation; a bit input value of the bit and the lower bit , And carry out the exclusive OR operation of these values.
A plurality of logic circuits for calculating bit values, which are output as increment values of the bits in accordance with the calculation results, and bit input values of a plurality of consecutive bits are input, and a logical product of these is performed, and all the bits are calculated. A switching signal generation circuit that outputs a switching signal when the bit is the maximum value, and a carry value to a least significant bit of the plurality of consecutive bits, and a carry value from a most significant bit of the plurality of consecutive bits. The carry value is input, and normally, the carry value from the most significant bit is output as the carry value from the most significant bit of the plurality of consecutive bits, and when the switching signal is inputted, And a selector for outputting a carry value to the least significant bit as a carry value from the most significant bit. An incrementer that adds a predetermined fixed value to the data and outputs data composed of a plurality of increment values, wherein a bit input value of at least two or more consecutive bits of the plurality of consecutive bits is input. And a multi-bit operation value operation logic circuit that outputs a multi-bit operation value in accordance with the operation result, and a plurality of consecutive bits input to the multi-bit operation value operation logic circuit. The carry value to the least significant bit of the above and the multi-bit operation value are input, the logical product operation is performed, and the multi-bit carry value according to the operation result is input to the multi-bit operation value operation logic circuit. And a multi-bit carry value operation logic circuit that outputs a carry value from the most significant bit of the plurality of consecutive bits to be carried out. Incrementer. 3. The incrementer according to claim 1, wherein the multi-bit operation value operation logic circuit receives a bit input value of 2 to 4 bits. 4. The incrementer according to claim 2, wherein the number of input bits of the multi-bit operation value operation logic circuit differs for each unit divided by the selector. 5. The multi-bit operation value operation logic circuit according to claim 1, wherein a bit higher than a bit to which a fixed value is added is set as a bit input value.
The incrementer according to any one of the above. 6. A fixed value addition bit position selection circuit for exclusively selecting one bit from among a plurality of bits to determine a position of a bit to which a fixed value is added, and a multi-bit operation value operation logic 5. The circuit according to claim 1, wherein the circuit sets, as the bit input value, the most significant bit of the plurality of bits on which the addition operation of the fixed value is performed or a bit higher than the most significant bit. An incrementer according to any one of the preceding claims.