JP2000196958A - Video signal processor, video signal processing method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make characters displayed to be superimposed upon a video easily visible. SOLUTION: A system decoder 14 resolves digital television signals from a tuner 12 into audio information, video information, and accessory information and respectively output the information to an audio decoder 16, a video decoder 18, and a control circuit 20. The video decoder 18 decodes the video information from the decode 14 and outputs the reproduced video signals to a bit shifting circuit 28 and a selection circuit 30. The circuit 28 shifts the video data from the decoder 18 by one bit outputs the shifted data to the selection circuit 30. The control circuit 20 causes a character generating circuit 32 to generate dot signals indicating the characters to be displayed on a screen in accordance with the character information to be displayed and its related information contained in the accessory information from the system decoder 14. The circuit 30 selects the output of the decoder 18 outside a character displaying area, the output of the bit shifting circuit 28 inside the character displaying area, and a prescribed signal in a character section in accordance with a control signal from the character generating circuit 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus and method for processing a video signal in which characters are combined, and a storage medium.

[0002]

2. Description of the Related Art A television signal transmitted via a satellite, a terrestrial wave, or a cable is often broadcast with characters superimposed thereon. FIG. 12 shows a schematic block diagram of a conventional analog television signal receiving apparatus. Tuner 110
Extracts a TV signal of a desired channel from a signal received by an antenna, and applies the TV signal to a decoder 112. The decoder 112 separates and demodulates the video signal and the audio signal from the television signal from the tuner 110, applies the video signal to the display device 114, and applies the audio signal to the speaker.

[0003] Since a conventional television broadcast receiving apparatus basically has only a function of displaying an image, character information is generally broadcast by being superimposed on the image. In order to receive and display teletext, a dedicated decoder must be provided. For example, emergency information such as occurrence of an earthquake is also broadcast in a form superimposed on video.

[0004]

When transmitting a video signal in which characters are superimposed on a video, for example, as shown in FIG.
Depending on the background image and color, the superimposed characters are difficult to read. For example, when it is desired to superimpose the character “Earthquake” on the image at the screen position as shown in FIG. When the image is white, the characters are buried in the background image, and the characters cannot be read.

[0005] It is an object of the present invention to provide a video signal processing apparatus and method and a storage medium which prevent such a problem.

The present invention also provides a video signal processing apparatus and method and a storage medium which make character information easy to read without considering the relationship between characters and an image of a portion where the characters overlap on the transmission side. The purpose is to do.

[0007]

According to the present invention, there is provided a video signal processing apparatus comprising: input means for inputting video information and text information to be superimposed on a video of the video information; And a superimposing means for reducing the brightness of the video information from the input means in the display area of the text information and superimposing the text video signal in the display area of the text information. It is characterized by.

A video signal processing method according to the present invention comprises the steps of: inputting video information and text information to be superimposed on the video of the video information; and generating a text video signal corresponding to the text information. A superimposing step of reducing the brightness of the video information from the input step in the display area of the text information and superimposing the text video signal in the display area of the text information.

A storage medium according to the present invention stores program software for executing the above-described video signal processing method.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of a first embodiment of the present invention. Radio waves received by the antenna 10 are input to the tuner 12. The user can select a desired channel using the tuner 12. The digital television signal of the selected channel is input to the system decoder 14. The system decoder 14 decomposes the television signal from the tuner 12 into image information, audio information, and additional information (such as character information and control information), and outputs the audio information to the audio decoder 16, the image information to the video decoder 18, The information is output to the control circuit 20, respectively.

The audio decoder 16 decodes audio information from the system decoder 14 to reproduce an audio signal, and outputs the reproduced audio signal to a speaker 24 via an audio output terminal 22.

The video decoder 18 decodes the video information from the system decoder 14 using the memory 26, and outputs the video signal reproduced thereby to the bit shift circuit 28 and the selection circuit 30. The bit shift circuit 28 shifts the video data from the video decoder 18 by one bit and outputs it to the selection circuit 30.

The control circuit 20 includes the system decoder 14
In accordance with the character information to be displayed on the screen and the related information included in the supplementary information from, a dot signal (Char ON signal) indicating the character to be displayed on the screen is generated by the character generation circuit 32, and at a timing according to the display timing. A control signal (Window ON signal) for controlling the selection circuit 30 is generated, and the video decoder 18
, The output of the bit shift circuit 28, or the output of the character generation circuit 32. The signal selected by the selection circuit 30 is supplied to the video display device 3 via the video output terminal 34.
6.

FIG. 2 shows an example of a specific circuit configuration of the character generation circuit 32. Here, the system decoder 14
To the control circuit 20 as shown in FIG.
Is displayed on the screen at coordinates (X0, Y0): (X1, Y
The operation will be described by taking as an example a case where supplementary information indicating that the image is arranged in the rectangular area specified in 1) is supplied. It is assumed that the upper left of the screen is the origin (0, 0).

Hsync indicates a horizontal synchronization signal, Vsync indicates a vertical synchronization signal, and P_Clk indicates a pixel clock in video display. The horizontal counter 40 is cleared by the horizontal synchronization signal Hsync, and counts the horizontal position on the screen according to the pixel clock P_Clk. Count the vertical position. The output of the horizontal counter 40 indicates the horizontal coordinate X, and the output of the vertical counter 42 indicates the vertical coordinate Y.

The window comparator 44 determines the current display position from (X0, Y) in FIG. 4 based on the Window data from the control circuit 20 and the outputs (X, Y) of the counters 40,42.
0): It is determined whether or not to enter the area of (X1, Y1), that is, the character display area. The determination result is supplied to the address counter 46 and the selection circuit 30 as a Window ON signal.

The address counter 46 is reset by a V_Sync signal (or a frame synchronization signal), and the output of the window comparator 44 (Window ON).
Signal) as a counter enable signal, and the held value is incremented. The value held by the address counter 46 is
This is applied to the character data memory 48 as a read address. The character pattern data of the character string to be displayed is written in the character data memory 48 from the control circuit 20 in advance, and the data at the address specified by the address counter 46 is output to the selection circuit 30 as a Char ON signal.

FIG. 3 shows a schematic configuration of the window comparator 44. Latch circuits 50-1, 50-2, 50-3, 50
-4 respectively follow the load instruction, and X0,
X1, Y0, and Y1 are fetched. The comparison circuit 52-1 compares the count value H_count of the horizontal counter 40 with the held value X0 of the latch circuit 50-1, and if H_count is equal to X
If it is larger than 0, the output is set to H (high). The comparison circuit 52-2 calculates the count value H_cou of the horizontal counter 40.
nt and the held value X1 of the latch circuit 50-2 are compared.
When count is smaller than X1, the output is set to H (high). The comparison circuit 52-3 calculates the count value V_count of the vertical counter 42 and the held value Y0 of the latch circuit 50-3.
, And when V_count is larger than Y0, the output is set to H (high). The comparison circuit 52-4 calculates the count value V_count of the vertical counter 42 and the latch circuit 50-
4 and the output is set to H (high) when V_count is smaller than Y1. AND circuit 54
Takes the logical product of the outputs of the comparison circuits 52-1 to 52-4. When the output of the AND circuit 54 is at H level,
ow ON signal.

FIG. 5 shows an example of data stored in the character data memory 48. In the example shown in FIG. 5, it is assumed that one character is composed of 16 × 16 pixels. The (x, y) coordinates in the in-screen display area are displayed at four corners. The address of the memory 48 is incremented in order from (0, 0) at the upper left to lower right. In FIG. 5, a black portion is “1” and a white portion is “0”.

FIG. 6 shows an example of the bit shift circuit 28. The bit shift circuit shown in FIG. 6 is applicable to a luminance signal (Y) and an RGB signal. In the circuit shown in FIG.
It conforms to ITU recommendation 601 and is restricted so as not to generate data of less than 16 as a digital value. If not conforming to the ITU recommendation 601, the bit shift of the bit shift circuit 28 may be simple.

FIG. 7 shows a display example according to this embodiment. In the character display area, the characters are outlined and the background is black. Thus, characters can be displayed in a more legible manner regardless of the image serving as the background of the character display area itself.

The RGB signal is converted from, for example, a YUV signal. In that case, the bit shift may be performed at the stage of the UV signal. FIG. 8 is a schematic block diagram of a bit shift circuit for a UV signal. This circuit is UV
The data from -128 to +127 is converted to 128
This is a circuit that performs a bit shift on a signal to which the value of is added as an offset. Due to the contents of the most significant bit, the output bit (Out
The content of 6) is determined.

In the above embodiment, the signal level of the background around the character is lowered to make the character easier to see. However, the background is colored a little and the coloring is changed over time to obtain the background. The characters can be more easily viewed while allowing the user to confirm the video to some extent. FIG. 9 is a schematic block diagram showing the configuration of the embodiment thus modified. The same components as those in FIG. 1 are denoted by the same reference numerals.

In the embodiment shown in FIG. 9, the functions or operations of the bit shift circuit 70, the control circuit 72, and the character generation circuit 74 are the same as those of the bit shift circuit 28, the control circuit 20, and the character generation circuit 32 shown in FIG. Different from that of The changed part will be described in detail.

The control circuit 72 includes the system decoder circuit 1
4 generates a dot signal (Char ON signal) indicating a character to be displayed on the screen based on the character information and the related information output from the character generation circuit 74, and controls the selection circuit 30 at a timing corresponding to the display timing. A control signal (Window ON signal) is generated to cause the selection circuit 30 to select the output of the video decoder 18, the output of the bit shift circuit 28, or the output of the character generation circuit 32. The control circuit 72 also outputs a color control timing signal C_Cont (for example, in a one-second cycle) for switching the video signal of the character background to the character generation circuit 74 and the bit shift circuit 70.

The bit shift circuit 70 halves the intensity of the video by shifting the video data from the video decoder 18 by one bit. FIG. 10 shows a schematic block diagram of a first example of the bit shift circuit 70, and FIG.
FIG. 9 is a schematic block diagram of a second example of the bit shift circuit 70.

The operation of the bit shift circuit 70 shown in FIG. 10 will be described. 8-bit video signal (from In7 to In0)
And outputs a signal in which each bit is basically shifted by one bit from Out7 to Out0. Selection circuit 80-1
８０80-7 select the A input when the selection control signal is “1”, and select the B input otherwise. Therefore, when the color control signal C_Cont from the control circuit 72 is “1”, the output Out7 is “1” (“0” in FIG. 11). Conversely, when the color control timing signal C_Cont is “0”, Output Out7 is '0'('1' in FIG. 11)
Becomes The color control timing signal C_Cont enables display in which the offset of the color signal is temporally changed with respect to a signal in which the background original video signal is reduced to half the level. Further, in the bit shift circuits shown in FIGS. 10 and 11, the upper limit (239) and the lower limit (16) of the output value are set so that the output has a form close to the ITU recommendation 601.

The bit shift circuit shown in FIG. 6 is used for the G (green) signal, and the bit shift circuit shown in FIG. 10 or 11 is used for the R (red) signal and the B (blue) signal. By using the bit shift circuits shown in FIGS. 10 and 11 in pairs, characters can be effectively viewed easily.

[0030]

As can be easily understood from the above description, according to the present invention, character information can be displayed in a legible manner while the contents of the background video can be confirmed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a first embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of a character generation circuit 32.

FIG. 3 is a schematic configuration block diagram of a window comparator 44.

FIG. 4 is a diagram illustrating the entire display screen and a character display area.

5 shows an example of data stored in a character data memory 48. FIG.

FIG. 6 is a schematic block diagram of a configuration of a bit shift circuit 28;

FIG. 7 is an example of a display screen according to the embodiment shown in FIG. 1;

FIG. 8 is a schematic configuration block diagram of another example of the bit shift path 28;

FIG. 9 is a schematic configuration block diagram of a second embodiment of the present invention.

FIG. 10 is a schematic block diagram of a configuration of a bit shift circuit 70.

11 is a schematic block diagram of another example of the bit shift circuit 70. FIG.

FIG. 12 is a schematic block diagram of a conventional television broadcast receiving apparatus.

FIG. 13 is an example showing a display position of a character to be inserted in a screen.

FIG. 14 is a screen example in which inserted characters are actually displayed.

[Explanation of symbols]

 10: Antenna 12: Tuner 14: System Decoder 16: Audio Decoder 18: Video Decoder 20: Control Circuit 22: Audio Output Terminal 24: Speaker 26: Memory 28: Bit Shift Circuit 30: Selection Circuit 32: Character Generation Circuit 34: Video output terminal 36: Video display device 40: Horizontal counter 42: Vertical counter 44: Window comparator 46: Address counter 48: Character data memory 50-1, 50-2, 50-3, 50-4: Latch circuit 52- 1, 52-2, 52-3, 52-4: comparison circuit 54: AND circuit 70: bit shift circuit 72: control circuit 74: character generation circuit 80-1 to 80-7: selection circuit 110: tuner 112: decoder 114: Display device 116: Speaker

Claims (27)

[Claims] 1. An input unit for inputting text information to be superimposed on video information and a video of the video information, a character generation unit for generating a text video signal according to the text information, and the video from the input unit A video signal processing apparatus comprising: superimposing means for reducing the brightness of information in a display area of the character information and superimposing the character video signal in the display area of the character information. 2. The video signal processing apparatus according to claim 1, wherein the input unit is an extraction unit that extracts the video information and the text information of a predetermined channel from a broadcast signal. 3. The video signal processing device according to claim 2, wherein in the broadcast signal, the character information is multiplexed with a predetermined signal portion of the video information. 4. The superimposing means selects a reducing means for reducing the brightness of the video information from the input means, and selects the video information from the input means except for a display area of the character information. 2. The video signal processing apparatus according to claim 1, further comprising a selection unit that selects a signal in which a character video signal from the character generation unit is superimposed on an output of the reduction unit in a display area of the character information. 5. The video signal processing device according to claim 4, wherein said reduction means comprises a bit shift circuit. 6. The video signal processing apparatus according to claim 1, wherein the superimposing means changes the degree of reduction in brightness of the video information from the input means in a display area of the character information according to time. . 7. The video signal processing apparatus according to claim 6, wherein said superimposing means periodically changes an offset signal given to said video information from said input means. 8. The video signal processing apparatus according to claim 4, wherein the reduction unit changes a degree of reducing brightness of the video information from the input unit in accordance with time. 9. The video signal processing apparatus according to claim 8, wherein the reduction unit periodically changes an offset signal given to the video information from the input unit. 10. A step of inputting video information and text information to be superimposed on the video of the video information, a text generating step of generating a text video signal according to the text information, and the video from the input step A superimposing step of reducing the brightness of the information in the display area of the character information and superimposing the character video signal in the display area of the character information. 11. The video signal processing method according to claim 10, wherein said input step is an extraction step of extracting said video information and said text information of a predetermined channel from a broadcast signal. 12. The video signal processing device according to claim 11, wherein in the broadcast signal, the character information is multiplexed on a predetermined signal portion of the video information. 13. The superimposing step includes: a reducing step of reducing the brightness of the video information from the input step; and selecting the video information from the input step except for a display area of the character information. The video signal processing method according to claim 10, further comprising: selecting a signal in which a character video signal from the character generation step is superimposed on an output of the reduction step in a display area of the character information. 14. The video signal processing method according to claim 13, wherein the reduction step comprises a bit shift. 15. The video signal processing method according to claim 10, wherein in the superimposing step, a degree of reducing the brightness of the video information from the input step in a display area of the character information is changed according to time. . 16. The video signal processing method according to claim 15, wherein the superimposing step periodically changes an offset signal given to the video information from the input step. 17. The video signal processing method according to claim 13, wherein the reducing step changes a degree of reducing the brightness of the video information from the input step according to time. 18. The video signal processing method according to claim 17, wherein the reducing step periodically changes an offset signal given to the video information from the input step. 19. A step of inputting video information and text information to be superimposed on the video of the video information, a text generation step of generating a text video signal according to the text information, and the video from the input step A superimposing step of reducing the brightness of the information in the display area of the character information and superimposing the character video signal in the display area of the character information.
A storage medium that stores software. 20. The storage medium according to claim 19, wherein said input step is an extraction step of extracting said video information and said text information of a predetermined channel from a broadcast signal. 21. The storage medium according to claim 20, wherein, in the broadcast signal, the character information is multiplexed on a predetermined signal portion of the video information. 22. The superimposing step includes: a reduction step of reducing the brightness of the video information from the input step; and selecting the video information from the input step except for a display area of the character information. 20. The storage medium according to claim 19, further comprising: a selection step of selecting a signal in which a character video signal from the character generation step is superimposed on an output of the reduction step in a display area of the character information. 23. The storage medium according to claim 22, wherein said reduction step comprises a bit shift. 24. The storage medium according to claim 19, wherein, in the superimposing step, a degree of reducing the brightness of the video information from the input step in the display area of the character information is changed according to time. 25. The storage medium according to claim 24, wherein said superimposing step periodically changes an offset signal given to said video information from said input step. 26. The storage medium according to claim 22, wherein the reducing step changes a degree of reducing the brightness of the video information from the input step according to time. 27. The storage medium according to claim 26, wherein said reducing step periodically changes an offset signal given to said video information from said input step.