JP2000196458A - Signal conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of a ΔΣmodulation circuit that quantizes an analog signal in a switching amplifier or the like, which conduct high efficiency power amplification by applying pulse drive to a constant voltage switch corresponding to an audio signal from an analog signal source, using an LPF to smooth its output pulse and demodulating the smoothed pulse into an audio signal. SOLUTION: The ΔΣ modulation circuit is provided with two quantizers CMP1, CMP2 that quantize an output of an integration device.adder group 25, and a reference value setting circuit 27 continuously changes the quantization reference values Vref1, Vref2. Thus, in the case of integrating the ΔΣ modulation circuit 21 as an IC, it is not required to high precision matching at voltage division resistors or the like, the design is facilitated and the low cost of the ΔΣmodulation circuit is attained. The conventional binary ΔΣ. modulation can be realized by using the quantization reference values Vref1, Vref2 in common so as to attain a general-purpose integrated circuit in addition to tri-state ΔΣmodulation employing the two quantizers CMP1, CMP2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal conversion circuit which is preferably implemented in relation to an audio signal, and which quantizes the audio signal by using .DELTA..SIGMA. Modulation when amplifying the power of the audio signal. .

[0002]

2. Description of the Related Art FIG. 5 shows a switching amplifier 1 having a .DELTA..SIGMA. Modulation circuit 3 which is a typical prior art signal conversion circuit.
FIG. 2 is a block diagram showing an electrical configuration of the embodiment. An analog input audio signal from the analog signal source 2 is input to the switching amplifier 1, and first, the ΔΣ modulation circuit 3
It is converted into a 1-bit digital signal.

The ΔΣ modulation circuit 3 is provided, for example, in FIG.
As shown in the figure, an integration configured to include a cascade-connected high-order integrator for sequentially integrating the input audio signal, and an adder for mutually adding outputs from the respective integrators. An adder / adder group 4, a quantizer 5 for quantizing an output from the adder of the integrator / adder group 4 into a 1-bit signal,
A delay unit 6 for delaying the 1-bit signal from the quantizer 5 by one sampling clock, a digital / analog converter 7 for digital-to-analog conversion of the 1-bit signal from the delay unit 6, and the analog signal source 2 And an adder 8 for subtracting the audio signal fed back from the digital / analog converter 7 from the input audio signal from the digital / analog converter 7. Thereby, feedback control is realized so that the 1-bit signal from the quantizer 5 corresponds to the input analog audio signal.

The 1-bit signal from the quantizer 5 is supplied to a constant voltage switch 9, and a pulse signal of a predetermined constant voltage corresponding to the generated 1-bit signal is converted into an analog audio signal by a low-pass filter 10. After being demodulated, it is output and sonicated by the speaker 11.

The switching amplifier 1 configured as described above does not use the linear region (unsaturated region) of the semiconductor power amplifying element as in the conventional amplifier, but uses the semiconductor power amplifier used in the constant voltage switch 9. Since the amplification element is used in a non-linear range (saturation range), there is an advantage that power amplification can be performed with extremely high efficiency.

FIG. 6 is an electric circuit diagram of a constant voltage switch 9a which is a specific configuration example of the constant voltage switch 9. As shown in FIG. The constant voltage switch 9a is provided with a series circuit of semiconductor switching elements Q11 and Q12 between a power supply having a constant high potential + E ₀ and a constant low potential −E ₀ . A control input terminal of the semiconductor switching element Q11 is an input terminal P11, a control input terminal of the semiconductor switching element Q12 is an input terminal P12, and a connection point between these semiconductor switching elements Q11 and Q12 is an output terminal P2. The input terminal P13 has the ΔΣ
A 1-bit signal from the quantizer 5 of the modulation circuit 3 is supplied. This 1-bit signal is directly supplied to the input terminal P11, and is supplied to the input terminal P12 after being inverted by the inversion buffer B, and the power is amplified. The output 1-bit signal is output from the output terminal P2 to the low-pass filter 10.

FIG. 7 is a waveform diagram for explaining the operation of the constant voltage switch 9a. In response to the input 1-bit signal from the quantizer 5, the potential of the output signal becomes + E ₀
It is understood that changes between -E ₀ and. Therefore, even when a signal having a relatively small amplitude is output, + E
₀ or outputs large amplitude -E _0, in order to cancel it, so further so that repeated operation of outputting ... large amplitude -E ₀ or + E _0, there is a problem that power efficiency is poor . In order to solve such a problem, a constant voltage switch 9b as shown in FIG. 8 has been proposed.

FIG. 8 is an electric circuit diagram of a constant voltage switch 9b which is another configuration example of the constant voltage switch 9. As shown in FIG. In the constant voltage switch 9b, a series circuit of the semiconductor switching elements Q11 and Q12 and a series circuit of the semiconductor switching elements Q13 and Q14 are provided between the power supply of the high potential + E _{0 and} the power supply of the low potential -E _0. The semiconductor switching elements Q11 and Q11 are arranged in parallel with each other.
The connection point between the switching elements 12 becomes one output terminal P21, and the connection point between the semiconductor switching elements Q13 and Q14 becomes the other output terminal P22. Control input terminals P11,1 of semiconductor switching elements Q11, Q14 arranged on a diagonal line
4 is supplied with a common 1-bit signal. Similarly, the control input terminals P12, P12,
A common 1-bit signal is input to P13.

The operation waveform of the constant voltage switch 9b is shown in FIG.
Indicated by As is clear from FIG. 9, the output terminals P21, P21
Between 22, + 2E ₀ or well voltage -2E ₀ is applied, and a timing of applying zero voltage to between both output terminals P21, P22 is short-circuited. In this way, the period during which the 0 voltage is applied becomes longer at the time of the small signal, and the power efficiency can be further improved as compared with the constant voltage switch 9a.

[0010]

FIG. 10 is a diagram showing a configuration of a quantizer 5a corresponding to the constant voltage switch 9a. As shown in FIG. 10, a single comparator cmp is used for the binary input constant voltage switch 9a, and the input signal vin from the integrator / adder group 4 is converted to a predetermined quantization reference value. It is only necessary to perform level discrimination with vref and apply the obtained binary output vo to the input terminal P13 of the constant voltage switch 9a.

However, in the constant voltage switch 9b, the output has three values as shown in FIG. 9, so that the pair of semiconductor switching elements Q11, 14 and the semiconductor switching elements Q12, Q13 are driven, respectively. As shown by the quantizer 5b in FIG. 11, two comparators cmp1 and cmp2 are required. That is, the first comparator cmp1 discriminates the level of the input signal vin from the integrator / adder group 4 with the first quantization reference value vref1 to create a first control signal vo1 and a second comparison signal vo1. Vessel cm
p2 performs level discrimination with the second quantization reference value vref2 to create a second control output vo2.

Here, the constant voltage switch 9 shown in FIG.
b, the semiconductor switching elements Q11, Q14 and the semiconductor switching elements Q12, Q13 have opposite polarities, and in this case, a pair of control input terminals P11, P
14 and the control input terminals P12 and P13, the control signal vo1 from the comparator cmp1 may be applied to one of the pairs, and the control signal vo2 from the comparator cmp2 may be applied to the other. ~ Q14
Have the same polarity, the input of one of the comparator cmp1 and the comparator cmp2 may have the opposite polarity, or an inverter may be provided on the output side.

Even if the coefficients of the integrators and adders in the integrator / adder group 4 are changed, these quantization reference values vre
If f1 and vref2 are kept constant, there is a problem that the oscillation limit becomes small and the dynamic range becomes narrow. Similarly, when there is a difference between the output levels of the connected analog signal sources 2, the quantization reference value vr
If ef1 and vref2 are kept constant, oscillation occurs when a large signal is input, and the dynamic range becomes narrow when a small signal is input.

Further, on the maker side, separate integrated circuits for ΔΣ modulation are manufactured in a configuration using the constant voltage switch 9a of a low-priced product and a configuration using the constant voltage switch 9b of a high-priced product. Have to do
There is also a problem that the cost increases.

An object of the present invention is to provide a signal conversion circuit adapted to various applications and capable of exhibiting good characteristics in each application.

[0016]

According to a first aspect of the present invention, a signal conversion circuit sequentially integrates an input signal by a high-order integrator,
The added value of each integrator output is quantized by level discrimination with a quantization reference value predetermined by a quantizer, and the quantization result is negatively fed back to an input side to suppress a quantization error with respect to the input signal. The signal conversion circuit includes a plurality of quantization reference values, and includes a reference value setting unit capable of continuously changing at least one of the quantization reference values.

According to the above configuration, when the quantization reference value is created by, for example, dividing the bias voltage by resistance, at least one of the divided resistors is realized by, for example, an electronic regulator, and the reference value is set. The electronic volume changes its resistance value in response to an output from the means, thereby making at least one of the quantization reference values continuously variable.

Therefore, a wide dynamic range and an oscillation limit value can always be obtained in accordance with the change of the coefficient of the integrator or the adder or the level of the input signal. In this way, it is possible to adapt to various applications and exhibit good characteristics in each application.

In the signal conversion circuit according to the present invention, two quantization reference values are set, and the reference value setting means sets the two quantization reference values to the same value. And a ternary Δ based on the two quantization reference values
The output can be switched between a Σ modulation output and a binary ΔΣ modulation output using one quantization reference value.

According to the above configuration, the quantization reference values are set to the same value in the configuration of the two quantizers as shown in FIG. 11, and in this case, the quantizers 1
The operation is similar to that of the quantizer shown by 0 in FIG.
Can operate as a binary output ΔΣ modulation circuit. On the other hand, if the quantization reference values are kept different from each other, ternary Δ を modulation as shown in FIG. 9 can be realized. It is possible to cope with the difference of the constant voltage switch on the side and the like, and the versatility can be improved.

Further, the signal conversion circuit according to the third aspect of the present invention detects the amplitude level of the input signal, and instructs the reference value setting means to set the interval between the quantization reference values when the amplitude level is small. Is further provided, and input detecting means for reducing the interval between the quantization reference values when the amplitude level is large is further provided.

According to the above configuration, if the interval between the quantization reference values becomes small, when considering the multi-bit signal,
This is equivalent to a reduction in the voltage amplitude per bit. The input detection means causes the reference value setting means to reduce the interval between the quantization reference values when the input signal has a small amplitude,
If the amplitude is large, the interval is increased.

Therefore, when a small signal is input, the quantization noise level does not increase, that is, the dynamic range is not narrowed. When a large signal is input, the oscillation limit value is increased, and oscillation can be prevented.

Further, in the signal conversion circuit according to the invention of claim 4, at least one of the coefficients of the integrator and the adder is configured to be variable, and the reference value corresponds to the coefficient. The setting means may further include coefficient setting means for changing at least one of the plurality of quantization reference values.

According to the above arrangement, when the coefficients of the integrator and the adder are changed, the input level to the quantizer changes. Therefore, the coefficient setting means adapts the quantization to the reference value setting means. The quantizer reference value.

Therefore, it is possible to prevent a change in the quantization noise level, that is, a change in the dynamic range and a change in the oscillation limit value, even with respect to the coefficient change.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 4.

FIG. 1 is a block diagram showing an electrical configuration of a switching amplifier 22 having a ΔΣ modulation circuit 21 which is a signal conversion circuit according to an embodiment of the present invention. The switching amplifier 22 uses the constant voltage switch 9b shown in FIG. 8 and derives a ternary ΔΣ modulation output. The ΔΣ modulation circuit 21 corresponds to the constant voltage switch 9b.
Outputs two binary outputs Vo1 and Vo2. Analog signal source 2, low-pass filter 10, and speaker 11
Has the same configuration as the switching amplifier 1 shown in FIG.

When an analog input audio signal from the analog signal source 2 is input to the switching amplifier 22,
The signal is supplied to an adder 24 via an input circuit 23. In the adder 24, the input audio signal from which a feedback signal described later is subtracted is input to an integrator / adder group 25. The integrator / adder group 25 generally includes, for example, a 7th-order integrator and an adder for mutually adding outputs from the respective integrators, which will be described later. The output from the adder group is commonly input to the two binary quantizers CMP1 and CMP2 as the input signal Vin.

The binary quantizers CMP1 and CMP2 are:
Each quantization reference value Vr given from the reference value setting circuit 27
Based on ef1 and Vref2, the input signal Vin is level-discriminated to create the binary outputs Vo1 and Vo2. The binary outputs Vo1 and Vo2 are input to the constant voltage switch 9b, are delayed by one bit period by the delay unit 28, are converted to analog signals by the digital / analog converter 29, and then are output to the adder 24. It is fed back and subtracted from the input audio signal.

In connection with the integrator / adder group 25, a coefficient setting circuit 30 is provided. This coefficient setting circuit 3
0 includes a preset coefficient unit 31 and a switch 32. In the preset coefficient unit 31, a combination of each coefficient of the integrator and the adder in the integrator / adder group 25 is referred to. It is stored in advance as shown by the symbols a, b, and c. Each of the coefficient groups a, b, and c has a switch 3 corresponding to the type of the input audio signal and the ΔΣ modulation characteristic.
By switching 2, the corresponding integrator and adder in the integrator / adder group 25 are selectively set.

The switching state of the switch 32 in the coefficient setting circuit 30 is given to the reference value setting circuit 27 as coefficient selection information. The reference value setting circuit 2
7, amplitude information representing the amplitude level of the input audio signal detected by the input detection circuit 33 is input.

FIG. 2 is a block diagram showing a configuration example of the input detection circuit 33. The input audio signal is input to an amplitude absolute value detection circuit 41, and the absolute value level is sampled. The sampling value from the amplitude absolute value detection circuit 41 is input to a maximum amplitude constant time holding circuit 42, and the peak value of the sampling value is held for a certain time. That is, when a larger sampling value is input while holding the sampling value from the amplitude absolute value detection circuit 41 for the fixed time, the maximum amplitude constant time hold circuit 42 changes the hold value to the larger sampling value. Update and hold for a certain time from that point.

The hold value of the maximum amplitude constant time hold circuit 42 is subjected to a level determination such as the level of the level in the level determination circuit 43, and the amplitude information output circuit 44 responds to the determination result. Then, the amplitude information is output to the reference value setting circuit 27.

FIG. 3 is an electric circuit diagram for explaining the reference value setting circuit 27. The reference value setting circuit 27 is, generally, the a power supply of a high potential + E ₀ side, between the power supply on the low potential -E ₀ side, a series circuit of resistors R1, R2, R3 is configured is interposed I have. In the present invention, the resistor R2 is continuously variable, and is realized by, for example, an electronic regulator.
The resistance value is continuously variable from 0 (that is, both terminals are short-circuited) to a desired resistance value.

FIG. 4 is an electric circuit diagram showing a specific configuration example of the ΔΣ modulation circuit 21. In FIG. 4, FIG.
Are denoted by the same reference numerals. In this ΔΣ modulation circuit 21, two binary outputs Vo
In order to feed back Vo1 and Vo2, the first integrator in the integrator / adder group 25 includes an integrator M11 including an amplifier A11 in response to a feedback signal via the digital / analog converter 29. , And an integrator M12 having an amplifier A12. Correspondingly, the input circuit 23 has an amplifier A01 that inverts and amplifies the audio signal Vi input through the coupling capacitor C.
And an amplifier A02 that inverts and amplifies the inverted output with a gain of 1 and outputs the inverted output.

On the amplifier A11 side, the output from the amplifier A01 of the input circuit 23 is provided via an input resistor R111, and on the amplifier A12 side, the output from the amplifier A02 is provided via an input resistor R121. The feedback signal from the digital / analog converter 29 is
The signals are input to the amplifiers A11 and A12 via input resistors R112 and R122, respectively. Therefore, on the input side of the amplifiers A11 and A12, the input circuit 23
And the feedback signal are added to each other, which also corresponds to the adder 24. Integrator M1
The outputs from M1 and M12 are mutually added by an amplifier A13.

The output from the amplifier A13 is the input resistance R2
1, a second-stage integrator M2 including an amplifier A2
Is input to The output from the integrator M2 is the input resistance R3
1 through a third stage integrator M3 having an amplifier A3.
Is input to A resistor R23 is provided between the integrators M2 and M3.
1, R232, R233 and amplifier A23,
A partial negative feedback loop for zero point control in ΔΣ modulation is formed.

The output from the integrator M3 is the input resistance R41
Is input to a fourth-stage integrator M4 including an amplifier A4, and the output thereof is input to a fifth-stage integrator M5 including an amplifier A5 via an input resistor R51. The resistors 451, R452, and R45 are also provided between the integrators A4 and A5.
3 and an amplifier A45, and a partial negative feedback loop for the zero point control is formed.

The output from the integrator M5 is the input resistance R
61 through a sixth stage integrator M having an amplifier A6
6 and its output is input through an input resistor R71.
The signal is input to a seventh-stage integrator M7 including an amplifier A7. The resistors R671 and R67 are also provided between the integrators M6 and M7.
2, a partial negative feedback loop composed of R673 and amplifier A67 for zero point control is formed.

The outputs from the integrators M1 (M11 and M12 are collectively referred to), M2, M3, M4, M5, M6, and M7 are output from resistors R10, R20, R30, and R4, respectively.
The coefficients are processed through 0, R50, R60, and R70 and are added to each other. The adder is configured to include a negative adder including an amplifier A81, a positive adder including an amplifier A82, and an adder including an amplifier A83 for mutually adding their outputs. . In the example shown in FIG. 4, odd-order integrators M1, M3, 5, M
7 are added by an amplifier A81, and outputs from even-order integrators M2, M4, and M6 are added by an amplifier A82. The output from the amplifier A83 is input to the quantizer CMP as the input signal Vin.

The quantizer CMP has two hysteresis comparators Q1 and Q2 and flip-flops F1 to F1.
F6 or the like, and the hysteresis comparator Q
1 and Q2 are latched at the timing specified by the sampling signal fs, and the constant voltage switch 9b at the subsequent stage is latched.
And an output circuit 40 that outputs a signal in which the switching time interval is adjusted in accordance with the speed limit.

In the switching amplifier 22 configured as described above, the binary quantizer C in the ΔΣ modulation circuit 21
MP1, CMP2 quantization reference values Vref1, Vref
2 can be changed by the reference value setting circuit 27,
In making the ΔΣ modulation circuit 21 by an integrated circuit,
After creation, the reference value setting circuit 27 sets the quantization reference value V
ref1 and Vref2 can be changed, and the resistance R
It is not necessary to perform high-precision alignment of 1 to R3, and it is possible to improve the yield of chips, reduce the design load, and reduce the cost.

For the purpose of reducing the noise level and increasing the oscillation limit value in accordance with the type of the sound source, for example, the input resistor R2 in the integrator / adder group 25 is used.
1, R31, R41, R51, R61, R71, resistors R10, R20, R30, R40, R50, R60, R
When the coefficient value such as 70 is switched by the coefficient setting circuit 30, the reference value setting circuit 27 sets the quantization reference values Vref1 and Vref2 in response to the coefficient selection information. Therefore, the quantization reference values Vref1 and Vref2 can be set according to the level of the input signal Vin or the oscillation limit value that changes according to the coefficient value, and the transmission frequency band of the ΔΣ modulation circuit 21 can be set. Can be set the widest.

Further, the quantization reference value Vref
1 and Vref2 are set by the reference value setting circuit 27 in response to the amplitude information detected by the input detection circuit 33.
When the amplitude is small, the quantization reference value Vref1,
When the interval between Vref2 is set small, the quantization noise is reduced, and when the amplitude is large, the interval between the quantization reference values Vref1 and Vref2 is widened. Can be prevented.

Further, the quantization reference value Vref
1 and Vref2 can be set to the same value by setting the resistance value of the resistor R2 to 0, and the ΔΣ modulation circuit 21 outputs the three-value ΔΣ modulation output shown in FIGS. 8 and 9. And the constant voltage switch 9a for deriving the binary ΔΣ modulation output shown in FIGS. 6 and 7 can be applied to improve the versatility and reduce the cost of the switching amplifier. It can be widely applied from simple products to high-priced products.

In the ΔΣ modulation circuit 21 described above, although the quantizers are provided in two of CMP1 and CMP2, it goes without saying that three or more quantizers may be provided.

[0048]

According to the first aspect of the present invention, a signal conversion circuit comprises:
As described above, in a signal conversion circuit such as a ΔΣ modulation circuit, a plurality of quantization reference values are set, and at least one of them is made continuously variable.

Therefore, it is not necessary to match the quantization reference value with high accuracy, and the cost can be reduced by reducing the design burden and improving the production yield.
A wide dynamic range and an oscillation limit value can always be obtained in accordance with the change of the coefficient of the integrator or the adder in the ΔΣ modulation circuit or the level of the input signal. In this way, it is possible to adapt to various applications and exhibit good characteristics in each application.

The signal conversion circuit according to the second aspect of the present invention sets two quantization reference values and can set them to the same value as described above, And a binary 切換 modulation output with one quantization reference value.

Therefore, by using the integrated circuit of the common ΔΣ modulation circuit, it is possible to cope with the difference of the constant voltage switch and the like on the subsequent stage, and the versatility can be improved.

Further, the signal conversion circuit according to the third aspect of the present invention detects the amplitude level of the input signal, and if the amplitude level is small, reduces the interval between the quantization reference values. When the amplitude level is large, the interval between the quantization reference values is increased.

Therefore, when a small signal is input, the quantization noise level does not increase, that is, the dynamic range is not narrowed. When a large signal is input, the oscillation limit value is increased, and oscillation can be prevented. .

Further, as described above, the signal conversion circuit according to the fourth aspect of the invention converts a plurality of quantized reference values in response to a change in at least one coefficient of the integrator and the adder. At least one of them is changed.

Therefore, it is possible to prevent a change in the quantization noise level, that is, a change in the dynamic range and a change in the oscillation limit value in response to the coefficient change.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a signal conversion circuit Δ according to an embodiment of the present invention;
FIG. 3 is a block diagram illustrating an electrical configuration of a switching amplifier including a modulation circuit.

FIG. 2 is a block diagram illustrating a configuration example of an input detection circuit in the switching amplifier illustrated in FIG.

3 is an electric circuit diagram showing a configuration example of a reference value setting circuit in the switching amplifier shown in FIG.

FIG. 4 is an electric circuit diagram showing a specific configuration example of the ΔΣ modulation circuit shown in FIG. 1;

FIG. 5 is a block diagram illustrating an electrical configuration of a switching amplifier including a ΔΣ modulation circuit, which is a typical conventional signal conversion circuit.

FIG. 6 is an electric circuit diagram showing a configuration example of a constant voltage switch used in a switching amplifier.

FIG. 7 is a waveform chart for explaining the operation of the constant voltage switch shown in FIG.

FIG. 8 is an electric circuit diagram showing another configuration example of the constant voltage switch used in the switching amplifier.

FIG. 9 is a waveform chart for explaining the operation of the constant voltage switch shown in FIG.

FIG. 10 is a diagram illustrating a configuration example of a typical prior art quantizer in a ΔΣ modulation circuit.

FIG. 11 is a diagram illustrating another configuration example of the quantizer in the ΔΣ modulation circuit.

[Explanation of symbols]

 Reference Signs List 2 analog signal sources 9a, 9b constant voltage switch 10 low-pass filter 11 speaker 21 ΔΣ modulation circuit (signal conversion circuit) 22 switching amplifier 23 input circuit 24 adder 25 integrator / adder group 27 reference value setting circuit (reference value setting means) ) 28 delay unit 29 digital / analog converter 30 coefficient setting circuit (coefficient setting means) 31 preset coefficient unit 32 switch 33 input detection circuit (input detection means) 40 output circuit 41 amplitude absolute value detection circuit 42 maximum amplitude constant time hold circuit 43 Level judgment circuit 44 Amplitude information output circuit CMP quantizer CMP1, CMP2 Binary quantizer M11, M12, M2 to M7 Integrator Q11 to Q14 Semiconductor switching element Q1, Q2 Hysteresis comparator R; R1 to R3 Resistance

Claims (4)

[Claims] An input signal is sequentially integrated by a high-order integrator, and an added value of outputs of the respective integrators is quantized by level discrimination with a quantization reference value predetermined by a quantizer.
In a signal conversion circuit configured to negatively feed back the quantization result to an input side and suppress a quantization error with respect to the input signal, a plurality of the quantization reference values are provided, and at least one of the quantization reference values is provided. A signal conversion circuit comprising a reference value setting means capable of continuously changing the value. 2. The two quantization reference values are set, and the reference value setting means can set the two quantization reference values to be equal to each other. Value ΔΣ modulation output and binary Δ with one quantization reference value
2. The signal conversion circuit according to claim 1, wherein the output can be switched to a modulation output. 3. An amplitude level of said input signal is detected, and said reference value setting means decreases an interval between said quantization reference values when said amplitude level is small, and said signal when said amplitude level is large. 2. The apparatus according to claim 1, further comprising input detection means for increasing an interval between quantization reference values.
The signal conversion circuit as described. 4. The apparatus according to claim 1, wherein at least one of the coefficients of the integrator and the adder is configured to be changeable. At least one of the plurality of quantization reference values is provided to the reference value setting means in accordance with the coefficient. 2. The signal conversion circuit according to claim 1, further comprising a coefficient setting means for changing any one of the two.