JP2000195822A - Method to apply copper plating to silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve adhesion of a copper film to microscopic trenches and via holes by a method, wherein in a second stage, a current is interrupted, the thickness of the copper film deposited in the specified range in a first stage is chemically dissolved in a third stage, the current density of a cathod circuit is set lower than the circuit density in the first stage, and a current is made to flow to the copper film until the copper film reaches a prescribed thickness. SOLUTION: In a second stage, a current is interrupted. This time t2 is assumed to be the time equivalent to the time to take for chemically dissolving 5 to 80% of the thickness of a copper film deposited on the surface of a silicon wafer in a first stage. The copper film excessively deposited on the parts of the apertures of trenches and via holes in the first stage is preferentially dissolved. In a third stage, the current density of a cathode current I2 to be applied a plating is set lower than the current density of that in the first stage, and the time t3 is set to a time equivalent to the time it takes until the thickness of the copper film ultimately reaches a prescribed thickness. In this case, there is the possibility that the apertures are likely to be closed in the second stage, but when the circuit density of the cathod current I2 is set at a current density higher than the circuit density of that in the first stage, the apertures are again closed due to current concentration and voids might remain. Accordingly, there is a need to set the current density here to be lower than the circuit density of the cathode current in the first stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming copper used as a semiconductor wiring material by electro-copper plating, and more particularly to a method for improving copper coverage on fine trenches and via holes and improving uniformity. The present invention relates to a method for copper plating on a silicon wafer that can perform stable plating.

[0002]

2. Description of the Related Art Conventionally, in processing semiconductor wafers, aluminum has been used as a wiring material. However, recently, due to an increase in the degree of integration of wiring, copper has been replaced with copper having higher electrical conductivity than aluminum, and an increase in signal delay time has been prevented. As a method of forming a copper film on a wafer, CV
In addition to dry methods such as D method, evaporation method, sputtering method,
Electroplating from aqueous solutions has been used. Electro-copper plating has better throwing power for fine trenches and via holes compared to sputtering etc.,
Nevertheless, if the aspect ratio exceeds 3, the turning becomes insufficient, and voids may occur in the trenches and via holes.

In electrolytic copper plating, in order to improve the electrical conductivity of the surface of a silicon wafer to be plated,
It is necessary to form a copper thin film called a seed layer, and this film thickness is usually 10 to 100 nm. This copper seed layer is currently formed by sputtering, but has a poor uniformity in film thickness, and very little precipitates particularly on the side walls and bottoms in minute trenches and via holes. Various attempts have been made to increase this film thickness, but it is quite difficult, and it is generally said that the ratio of the deposited film thickness of copper at the hole bottom to the surface is 10% or less.

As described above, since the seed layer has a non-uniform film thickness, when immersed in a strongly acidic copper sulfate plating solution, the copper in the thin film portion disappears due to chemical dissolution, and the copper disappears. No electrolytic copper plating is deposited on the portion. Then, since the portion becomes a void, the rotation of the electrolytic copper plating becomes incomplete. Another problem is that copper is more likely to be deposited at the mouth than at the inside of the trench or via hole due to the current distribution. These mouth parts close faster and voids are formed inside.
As described above, there are several problems in depositing copper used as a semiconductor wiring material by electrolytic copper plating, and there is a problem that these must be overcome.

[0005]

SUMMARY OF THE INVENTION The present invention basically reexamines the process of electro-copper plating on a silicon wafer having a copper seed layer thin film attached thereto, and examines the surroundings of minute trenches and via holes in electro-copper plating. The purpose is to improve.

[0006]

Means for Solving the Problems To solve the above-mentioned problems, the present inventors have conducted a study. As a result, by improving the setting of current and time in electroplating, it is possible to improve the fine trenches and via holes. It was found that the rotation could be achieved effectively and with good reproducibility. The present invention is based on this finding, and is based on this finding. 1. A method for electrolytic copper plating on a silicon wafer provided with a copper seed layer thin film, wherein a current and a time applied during the plating process are a. As a first step, the cathode current is limited to the critical current density of 30 to
100%, which is less than the time required for copper deposition corresponding to a thickness of 75% of the smallest hole diameter or groove width on the wafer; b. As a second step, the current is interrupted and the time is set to a. A time corresponding to 5 to 80% of the thickness of the copper deposited in step c) being chemically dissolved; c. As a third step, the cathodic current is increased by the a. And plating the silicon wafer in the above three stages, wherein the current density is equal to or less than the current density in the stage, and the current is passed for a period of time until the copper film thickness finally reaches a predetermined value. 3. The method for plating copper on a silicon wafer according to the above 1, wherein the silicon wafer is continuously rotated therein. The step of chemically dissolving the copper deposited on the silicon wafer at the stage of, characterized in that in order to adjust the dissolution rate, a metal that is electrochemically more noble than copper is brought into contact with the silicon wafer. 3. The copper plating method for a silicon wafer according to 1 or 2.

[0007]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, as shown in FIG. 1, setting of current and time is changed in three stages. FIG. 1 is a schematic diagram of current / time setting in the copper electroplating of the present invention.
In the figure, the vertical axis represents the cathode current density, and the horizontal axis represents time.
Horizontal line at the bottom of Figure 1 shows the critical current density I _L. As a first step, the cathode current I ₁ is reduced to the limit current density I _L
30 to 100% of the time, the time t ₁ is less than the time required for the corresponding copper deposition of a thickness of 75% of the smallest hole diameter or groove width on the wafer. This is because when the current density is low, that is, when the deposition rate of copper is low, the copper in the seed layer disappears due to chemical dissolution at the bottom of the trench or via hole or in the vicinity of the bottom faster than the copper is deposited. In order to avoid this, it is necessary to increase the current density sufficiently and perform rapid plating. However, the current density is limited current density I
If it is higher than _L , the copper deposition becomes dendritic, which is not suitable for complete filling in trenches and via holes.

[0008] The time is at least equal to the film thickness at which the deposited copper film does not disappear at the bottom of the hole or in the vicinity thereof due to chemical dissolution when the current is stopped.
In addition, the time is set so that the thickness of the deposited copper does not become too large in the mouth portion of the trench or the via hole, so that the bottom portion is not closed before the bottom portion is filled in a subsequent operation. Since the copper plating film grows from the sidewalls on both sides of the trench or the via hole, the above-mentioned “minimum hole diameter or 75% of the groove width” means that the undeposited portion of the hole groove is 2%.
It means that it is 5%. Therefore, the deposited film thickness is の of 75%, that is, 37.5% of the “minimum hole diameter or groove width”.

As a second step, the current is interrupted. This time t ₂ is 5 to 80 times the thickness of the copper deposited on the surface in the first stage.
% Is the time corresponding to the chemical dissolution. In the copper deposition in the first stage, the current density is higher at these openings than at the bottoms of trenches and via holes,
As a result, the thickness of copper is greater at the mouth than at the bottom. If the plating is continued as it is, the mouth is closed before depositing in the trench or the via hole, and a void remains. The chemical dissolution of copper occurs at a higher rate on the surface than inside the trench or via hole because the diffusion rate of ionic species involved in the dissolution of copper is higher on the surface.
This is convenient for adjusting the film thickness, and this is used to preferentially dissolve the excessively precipitated copper in the opening of the trench or the via hole in the first step. However, if this time is too long, copper dissolves excessively and part or all disappears, and if it is too short, the above-mentioned effects cannot be obtained.
In the chemical dissolution of copper, the dissolution rate can be adjusted by bringing a metal, which is electrochemically more noble than copper, into contact with the silicon wafer for a required time. The contact of the noble metal can be performed continuously or intermittently for a certain period of time.

As a third step, the cathode current I _{2 for} plating is equal to or lower than the current density of the first step, and the time t ₃ is set until a predetermined copper film thickness is finally reached. This is the second
At the stage, the possibility of the mouth closing before depositing inside the trench or via hole is reduced by chemically dissolving the copper at the mouth of the trench or via hole,
If the current density is higher than in the first stage, the mouth may be closed again due to current concentration and voids may remain. Therefore, the current density here must be lower than the first stage. This is because copper ions are less likely to be supplied in the hole than in the surface, and in order to enhance the deposition property in the hole, it is better to lower the current density and reduce the deposition rate to perform plating gradually. . As a result, copper is completely buried even in the trench or via hole.

Although the electrolytic copper plating solution used in the present invention is not particularly limited, a copper sulfate plating solution is most preferable. This is because the components of the solution are simple, the wastewater treatment is easy, and in the field of semiconductor manufacturing, it does not contain alkali metal ions, which are a source of contamination. The method of the present invention has an advantage that the setting of conditions is easy to promote the speed. Other electrolytic copper plating solutions include a pyrophosphoric acid bath, an EDTA bath, and the like. These also form a complex with copper, so that chemical dissolution can be performed similarly at a low speed. In addition to the above, increasing the dissolved oxygen concentration by blowing air or the like is effective in increasing the chemical dissolution rate.

The following components are suitable as components of the copper sulfate plating solution. Copper sulfate: 0.1-100 g / L as copper (preferably 1
硫酸 50 g / L) Sulfuric acid: 0.1-500 g / L (preferably 1
0 to 300 g / L) In addition, as an additive, for example, polyethylene glycol, polypropylene glycol, quaternary ammonium salt,
Surfactants such as gelatin can be used. These are effective in increasing the polarization in the electrochemical reaction of electroplating, making the size of the copper crystal deposited by plating uniform, and improving the uniformity of the film thickness depending on the location of the deposited film. Also, brighteners can be used. Suitable brighteners include, for example, CC-1220 (manufactured by Japan Energy).

Prior to performing the electrolytic copper plating process of the present invention, trenches and via holes for embedding copper wiring are formed on the surface of a semiconductor wafer as is well known, and copper diffuses into silicon on the surface. Ti, T to prevent
A barrier metal selected from a, Ni, or the like can be formed by a known method such as vapor deposition, sputtering, or a CVD method.
Although this film thickness varies depending on the manufacturing conditions, it is generally 0.1 μm.
It is about 001 to 0.1 μm. In addition, a thin layer of copper is also deposited on the barrier metal layer by vapor deposition, sputtering,
It is attached by a known method such as a CVD method. This is because the barrier metal layer generally has a large electric resistance, and the difference in current density between the periphery of the contact provided at the peripheral portion of the wafer and the central portion in the electroplating becomes large. It is to be given. The thickness is suitably 0.001 to 0.1 μm. However, this film thickness is determined by manufacturing conditions, and is not limited to this range.

The present invention can be carried out using known industrial equipment. FIG. 2 shows a test apparatus used for performing tests of the example and the comparative example, which is structurally similar to an industrial apparatus. In general, an industrial apparatus is designed so that a silicon wafer can be set on a rotating electrode in the same size, and the size (shape, size) of a tank, an anode and the like is naturally increased accordingly. A semiconductor wafer 1 as a material to be plated and an anode 2 are placed in an electroplating tank 3 so as to face each other. In FIG. 2, the semiconductor wafer 1 and the anode 2 are arranged horizontally with respect to the electroplating solution level 4, but they may be arranged vertically. The semiconductor wafer 1 needs to be sealed so that the surface to be plated is left, and the back surface is not touched by the electroplating solution. The contact for power supply is provided near the edge of the semiconductor wafer 1. Reference numeral 6 denotes a rotating electrode that holds and rotates the semiconductor wafer 1, and reference numeral 7 denotes a rectifier. As the anode 2, a phosphorus-containing copper anode (phosphorus content: 0.04 to 0.06%) or an insoluble anode is used. Pt, Pt-plated Ti
Is appropriate. A commercially available dimensionally stable electrode (DSA) can also be used. In the case of using a phosphorous copper anode, the replenishment of the plated copper is automatically performed by dissolving the anode. However, since some sludge is generated when the anode is dissolved, it is necessary to put the anode in an anode bag made of polypropylene fiber or the like. When an insoluble anode is used, the concentration of copper in the solution is reduced by plating, and it is necessary to supply a copper sulfate solution to maintain the concentration of copper.

The plating conditions in the present invention are as follows. Current density: 0.1 to 100 A / dm ² (preferably 0.1 to 100 A / dm ² )
5-5 A / dm ² ) Liquid temperature: 10-80 ° C (preferably 15-30 °)
C) The current density, the solution temperature and the solution flow rate (relative speed between the plating surface and the solution bulk) in electroplating have a mutually dependent relationship, and within the above range, the surface of the semiconductor wafer to be plated is By applying an appropriate flow rate of the liquid, a desired deposition rate and copper precipitation (crystal state) can be obtained. As a method of giving the liquid flow velocity, a method of rotating the wafer to be plated as shown in FIG. 2 is suitable. In the present invention, the rotation of the wafer means to promote the supply of copper ions to the surface to be plated and to promote the chemical dissolution of copper. That is, these factors can be controlled by setting the rotation speed. As the rotation speed increases, both the supply rate of copper ions and the chemical dissolution rate of copper increase. In the present invention, the wafer as the object to be plated is continuously rotated during the above-described series of plating operations in the first to third stages. This stabilizes the supply of copper ions in the wafer surface and the rate of chemical dissolution of copper.

Further, as described above, in the present invention, in order to adjust the chemical dissolution rate of copper, the copper surface on the silicon wafer, which is the material to be plated, is electrochemically more noble than copper. Contact and separation of metal. When a noble metal is brought into contact with the copper surface, so-called battery reaction causes copper to become an anode and the noble metal to become a cathode, thereby accelerating the dissolution rate of copper. Therefore, the dissolution rate of copper is high at the time of contact, and the dissolution rate returns to its original state when the copper is released. Thus, in the second stage of the plating process of the present invention, the time for interrupting the current by making contact with the noble metal can be shortened, and as a result, the time required for total embedding can be reduced. Also in the third stage, precious metal contact can be made to adjust the net copper deposition rate. In the first stage, an increase in the chemical solubility of copper is undesirable because it leads to partial disappearance of the seed layer and consequently voids. The noble metal used in this method is chemically stable to the plating solution,
It may be more electrochemically noble than copper, platinum, gold,
Iridium and the like are suitable.

In the present invention, a normal acid immersion or the like is used as a pretreatment for applying electrolytic copper plating to a semiconductor wafer. Dilute sulfuric acid is suitable as the acid, and its concentration is suitably 0.1 to 50% (preferably 0.5 to 10%). The acid immersion as the pretreatment is not essential, and need not be performed. The final electrolytic copper plating film thickness by the method of the present invention is performed for the purpose of filling trenches on the surface of the semiconductor wafer and forming wiring by flattening by chemical mechanical polishing (CMP) which is a subsequent step. Just enough. Generally, it is 0.5 to 1.5 μm.

[0018]

Examples and comparative examples are described below based on examples and comparative examples. This embodiment is merely an example, and the present invention is not limited to this example. That is, the present invention is limited only by the claims, and includes various modifications other than the examples included in the present invention. An embedding test of a trench formed in a wafer by electrolytic copper plating was performed. The width of the trench of the wafer used for the test is 0.25 μm, and the depth is 1.0 μm (the aspect ratio is 4.0). The wafer was formed by sputtering 0.05 μm of Ta as a barrier layer, and 0.05 μm of copper as a seed layer thereon. In addition, the film thickness of copper is a target value of the surface. The composition of the electrolytic copper plating solution used is as follows. Copper sulfate: 8 g / L as copper Sulfuric acid: 180 g / L Chlorine: 70 ppm Additive (CC-1220: manufactured by Japan Energy): 1 m
L / L

This sample was electroplated under the following conditions. The plating conditions were changed by changing the values of the factors shown in FIG. The liquid temperature is 25 ° C. The copper deposition rate is 0.22 μm per minute at 1 A / dm ² . As a result of electrochemical measurement using the same liquid, the limiting current density of this liquid was 100 rpm and 2 rpm.
At 00 rpm, 3.0 A / dm ² and 4.2 A, respectively.
/ Dm ² . The chemical dissolution rate of the copper coating is 1 revolution.
0.01 μm at 00 rpm and 200 rpm, respectively.
/ Min and 0.02 μm / min. When the platinum wire was brought into contact with the copper surface at a rotation speed of 100 rpm, the chemical dissolution rate of the copper coating was estimated to be 0.06 μm / min.

Table 1 shows the test results. In Table 1, in Comparative Examples 1 and 12, the current density exceeded the range of the present invention, and voids occurred. Comparative Example 2-4 does not exist the time t ₂ of the second stage of interrupting the current. That is, there is no step of dissolving the copper deposited at the opening of the trench or the via hole, and voids are generated in each case. In Comparative Examples 5 and 10, the plating time in the first stage was excessive and voids were generated. In Comparative Examples 6 and 9, the current density in the first stage was insufficient and voids were generated. Comparative Example 7, 8, 11 and the second stage of the time t ₂ is in excess of interrupting the current, the coating of the copper is lost, it is considered that voids are generated. Especially Comparative Example 8
Is void inside the hole. Similarly, in Comparative Example 9, the current density was insufficient and voids were generated. In Comparative Example 13, platinum serving as a noble metal was brought into contact with the wafer to promote the chemical dissolution of copper. However, the excess amount resulted in voids in all the holes. In contrast to these comparative examples, no voids were formed in any of Examples 1 to 7 within the scope of the present invention, and complete embedding in a delicate trench was achieved, confirming the effectiveness of the present invention.

[0021]

[Table 1]

[0022]

According to the method of electroplating copper on a silicon wafer provided with a copper seed layer thin film, by improving the setting of current and time in electroplating, plating defects such as voids can be minimized. It is possible to achieve effective and reproducible turning around trenches and via holes.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of current / time setting in electrolytic copper plating of the present invention.

FIG. 2 is a schematic explanatory view of a rotary electrode plating apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer 2 Anode 3 Plating tank 4 Plating solution level 5 Contact 6 Rotating electrode 7 Rectifier

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4K024 AA09 AB01 BA15 BB12 CA07 CA16 CB08 GA16 4M104 BB04 BB05 BB14 BB17 DD34 DD37 DD43 DD52 FF17 HH13

Claims (3)

[Claims] 1. A method for electroplating copper on a silicon wafer provided with a copper seed layer thin film, comprising the steps of: a. As a first step, the cathode current is limited to the critical current density of 30 to
100%, which is less than the time required for copper deposition corresponding to a thickness of 75% of the smallest hole diameter or groove width on the wafer; b. As a second step, the current is interrupted and the time is set to a. A time corresponding to 5 to 80% of the thickness of the copper deposited in step c) being chemically dissolved; c. As a third step, the cathodic current is increased by the a. Plating at a current density of not more than the current stage, and energizing for a time until the copper film thickness finally reaches a predetermined thickness. 2. The method according to claim 1, wherein the silicon wafer is continuously rotated during the plating operation. 3. The b. The step of chemically dissolving copper deposited on the silicon wafer at the step of: contacting the silicon wafer with a metal that is electrochemically more noble than copper in order to adjust the dissolution rate. Item 1 or 2
The copper plating method for a silicon wafer as described in the above.