JP2000195411A - Field emission electron source device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high density and stable operation required for high definition and high reliability operation having beam focusing action allowing high definition. SOLUTION: A field emission type electron source device is provided with a field emission electron source part including a lead electrode 7, formed on a p-type silicon substrate 1 via an insulating film 6, having an opening part at a portion corresponding to a cathode forming region and a cathode part 5 formed at a part corresponding to the opening part and N-channel field effect transistor part 2-4 formed on the substrate 1. The field emission electron source part is formed at drain regions 3, 4 of the transistor part. A field emission current from the field emission electron source part is controlled by control voltage applied to a gate electrode 8. The drain regions include two kind of wells whose impurity concentration are different from each other. A well 4 whose the impurity concentration is lower than another is formed at an end part of the drain region contacting with a channel region of the transistor part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cold cathode electron source which is expected to be applied to an electron beam pumped laser, a flat display device, an ultra-high-speed micro vacuum device, and the like. The present invention relates to a field emission type electron source for semiconductor application which can realize a voltage and a method of manufacturing the same.

[0002]

2. Description of the Related Art The development of vacuum microelectronics technology has been actively pursued since the development of microfabrication technology for semiconductors has made it possible to form minute cold cathode structures.
The resulting micro-cold cathode structure is expected to have a flat-type electron emission characteristic and a high current density, and thus is expected to be particularly used as an electron source for a next-generation flat display. In addition, since the operating temperature is wider than that of a liquid crystal display system such as a TFT-LCD or the like, practical use as an in-vehicle environment-resistant display is desired.

In order to use these electron sources for flat display applications, it is necessary to satisfy required specifications such as a reduction in operating voltage, stabilization of electron emission characteristics and long life characteristics. In particular, stabilization of the electron emission characteristics is a problem directly related to the basic performance of the display as luminance, and is positioned as an important technical problem.

To solve this problem, a method of inserting a resistance layer inside the electron source, a method of incorporating a constant current circuit, and the like have been proposed.

A first conventional example will be described below with reference to Japanese Patent Application Laid-Open No.
The configuration of the field emission cold cathode device described in Japanese Patent No. 7957 will be described with reference to FIGS. 8 (a) and 8 (b).
This first conventional example uses the principle that the amount of emitter electron current emitted from a field emission cathode device is made constant using the constant current characteristics of a field effect transistor (FET). FIG.
FIG. 2A is a cross-sectional view of a part of a silicon substrate on which one field emission cathode element and one FET are formed, and FIG.
FIG. 2 is a circuit configuration diagram showing an electrical equivalent circuit of a portion including a field emission cathode element.

In FIGS. 8 (a) and 8 (b), 810
Is a field effect transistor (FET), 801 is a p-type silicon substrate, 802 is a first n-type layer serving as a source of the FET 810, 803 is a conical emitter of a field emission cathode device,
804 ′ is a portion of the insulating layer (SiO ₂ layer) 804 that functions as a gate insulating layer of the field emission cathode device,
Is a gate layer of a field emission cathode device, 806 is a FET 810
A second n-type layer 807 serving as a drain of the FET 810
808 is the gate electrode of the FET 810, 8
09 is an anode of the field emission cathode element, 811 is a source resistance, 812 is a gate voltage source (voltage value Vg), 813 is an anode voltage source (voltage value Va), and 814 is a gate-source control voltage source (voltage value Vgs). is there.

As shown in FIG. 8B, the field emission cathode device comprises a triode having an anode (A) 809, a gate (G) 805, and an emitter (E) 803. The emitter (E) 803 The drain-source path of the FET 810 and the source resistor 811 are connected in series between the ground and the ground.

In this triode, the anode (A) 80
9 is an anode voltage source 81 for generating an anode voltage Va.
3 and the gate (G) 805 is connected to a gate voltage source 812 that generates a fixed gate voltage Vg. F
In the ET 810, the gate 808 is connected to a gate-source control voltage source 814 that generates a variable gate-source control voltage Vgs.

In the field emission cathode element used in this field emission cathode device, a predetermined anode voltage Va is applied to the anode 809, a predetermined gate voltage Vg is applied to the gate 805, and a gate 808 of the FET 810 has a required value. When the source-to-source voltage Vgs is applied, the emitter 803
Is emitted from the emitter 803 without heating. In this case, the amount of emitter electron current emission of the field emission cathode device is not controlled by the fixed gate voltage Vg applied to the gate 805, but is changed by the variable gate applied to the gate 808 of the FET 810 connected to the emitter 803. By the source-to-source control voltage Vgs,
Controlled. That is, the FET 810 has its gate 808
By operating the gate-source control voltage Vgs applied to the gate electrode appropriately, the device operates in the constant current region.

As described above, the amount of electron current emitted from the emitter in the form of electric field is determined by the characteristics of the FET connected in series to the emitter and having the function of supplying emitted electrons. Therefore, by optimally designing the FET, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular, by performing the field emission in the saturation operation region of the FET, the emitter is released from the cause of instability of the emitter itself. As a result, an extremely stable and precisely controlled field emission electron flow rate can be obtained.

As a specification required for the cold cathode, for display applications, particularly high definition is also an important factor.
In general, in the case of a microchip type cold cathode structure, electrons emitted from an emitter have a predetermined divergence angle, which may hinder high-definition display.
As one of means for suppressing the spread of the electron orbit, a configuration using a focusing electrode has been proposed. FIG. 9 shows, as a second conventional example, an example of the configuration of such an FED disclosed in Japanese Patent Application Laid-Open No. H10-74473.

In this FED, a second gate electrode (converging electrode) is formed for each emitter, and a negative potential is applied to this gate electrode relative to the first gate electrode (drawing gate electrode). This causes the electrons emitted from the emitter to converge.

That is, in FIG. 9, reference numeral 91 denotes an insulating layer. An insulating layer 93 is further provided on the gate electrode (lead electrode) 92, and a second gate electrode (converging electrode) having a circular opening thereon is provided. ) 94 is provided. In this conventional example, a second gate electrode (converging electrode) 94 is provided so as to surround each emitter 95. By setting the potential of the second gate electrode (converging electrode) 94 to be lower than that of the first gate electrode (extraction gate electrode) 92, electrons emitted from the emitter receive a lens effect of a converging effect, and The trajectory of the beam is converged.

[0014]

However, the field emission type cathode device of the first conventional example can control the field emission electron flow rate stably for a short period of time, but depending on the operating conditions, the field emission type cathode device for a long period of time. Stability cannot be ensured.

The second conventional field emission type display device has a function of converging an electron beam.
It has the disadvantage that the amount of electrons emitted from the emitter is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its objects the following objects: (1) To obtain a field emission type electron source structure realizing a highly reliable operation required for a next-generation display. (2) to obtain a field emission type electron source structure which realizes a high density and stable operation for achieving higher definition; and (3) a field emission type having a beam converging function capable of achieving higher definition. Obtaining an electron source structure.

[0017]

According to an aspect of the present invention, there is provided an apparatus provided with a drawer formed on a p-type silicon substrate through an insulating film and having an opening at a position corresponding to a cathode forming region. A field emission electron source including an electrode, a cathode formed on the p-type silicon substrate at a position corresponding to the opening of the extraction electrode, and a field emission electron source corresponding to the field emission electron source. an n-channel field effect transistor portion formed on a p-type silicon substrate, wherein the field emission electron source portion is formed in a drain region of the field effect transistor portion, and a gate electrode of the field effect transistor portion A field emission type electron source device in which a field emission current from the field emission electron source section is controlled by an applied control voltage, wherein the drain region has at least two kinds of impurities having different impurity concentrations. A well having a low impurity concentration among the at least two types of wells is formed at an end of the drain region which is in contact with a channel region of the field effect transistor portion, thereby achieving the above object. Achieved.

For example, the drain region may include at least two types of n-type impurity elements having different thermal diffusion rates in a silicon substrate as the impurity elements.

In one embodiment, in the drain region,
As the impurity element, a phosphorus element having a high thermal diffusion rate in a silicon substrate and an arsenic element having a low thermal diffusion rate in a silicon substrate are included.

According to another aspect of the present invention, there is provided a device provided with an extraction electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region; A cathode portion formed on the mold silicon substrate at a position corresponding to the opening of the extraction electrode,
And an n-channel field-effect transistor section formed on the p-type silicon substrate corresponding to the field-emission electron source section. A field emission electron source device in which a field emission electron source section is formed, and a field emission current from the field emission electron source section is controlled by a control voltage applied to a gate electrode of the field effect transistor section. The gate electrode of the field effect transistor portion has a shape including at least two types of portions having different gate widths, and a part of the gate electrode is arranged so as to cover an end of the drain region. Thus, the above-mentioned object is achieved.

A device provided according to still another aspect of the present invention is a lead electrode formed on a p-type silicon substrate via a first insulating film and having an opening at a position corresponding to a cathode formation region. A field emission electron source section including: a cathode section formed on the p-type silicon substrate at a position corresponding to the opening of the extraction electrode; An n-channel field effect transistor portion formed on a silicon substrate, wherein the field emission electron source portion is formed in a drain region of the field effect transistor portion and applied to a gate electrode of the field effect transistor portion. A field emission current from the field emission electron source section is controlled by a control voltage to be applied, wherein the gate electrode of the field effect transistor and the p
A gate insulating film formed between the first insulating film formed between the lead electrode and the p-type silicon substrate; and a gate insulating film formed between the gate insulating film and the p-type silicon substrate. It has a configuration buried by the first insulating film, whereby the above-mentioned object is achieved.

The gate insulating film may be composed of a silicon thermal oxide film formed in a sharpening thermal oxidation process for sharpening the tip of the cathode portion of the field emission electron source.

According to another aspect of the present invention, there is provided an apparatus provided with an extraction electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region; a field emission electron source portion including a cathode portion formed on the p-type silicon substrate at a position corresponding to the opening of the extraction electrode; and the p-type silicon substrate corresponding to the field emission electron source portion. An n-channel field effect transistor portion formed thereon, wherein the field emission electron source portion is formed in a drain region of the field effect transistor portion, and a control applied to a gate electrode of the field effect transistor portion A field emission type electron source device in which a field emission current from the field emission electron source unit is controlled by a voltage, wherein the field emission type electron source device is formed of the same material as the gate electrode of the field effect transistor unit. Further comprise a shield electrode disposed so as to cover the area not covered by the gate electrode within the channel region of the field effect transistor unit, by its, the preceding objects are achieved.

[0024] Preferably, the shield electrode is provided with the p
It is maintained at the same potential as the silicon substrate, and has a function of blocking the influence of an external electric field not caused by the gate electrode on the channel region.

According to another aspect of the present invention, there is provided an apparatus provided with a lead electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode forming region. a field emission electron source portion including a cathode portion formed on the p-type silicon substrate at a position corresponding to the opening of the extraction electrode; and the p-type silicon substrate corresponding to the field emission electron source portion. An n-channel field effect transistor portion formed thereon, wherein the field emission electron source portion is formed in a drain region of the field effect transistor portion, and a control applied to a gate electrode of the field effect transistor portion A field emission type electron source device in which a field emission current from the field emission electron source section is controlled by a voltage, wherein the drain region of the field effect transistor section includes the field effect transistor. The gate electrode of the field-effect transistor unit is arranged inside the source region of the unit so as to be surrounded by the source region, and the gate electrode of the field-emission electron source unit is symmetrically planar with respect to the cathode unit. And thereby achieves the objectives set forth above.

For example, the drain region comprises a p-type conductive layer.

An outer peripheral portion of the drain region which is in contact with the channel region of the field effect transistor portion;
The inner peripheral portion of the source region may have a circular shape formed on a concentric circumference.

At least a part of the gate electrode formed between the source region and the drain region is
It may have an arc-shaped symmetrical shape.

For example, Vg <between a first voltage Vex applied to the extraction electrode of the field emission electron source and a second voltage Vg applied to the gate electrode of the field effect transistor. There is a relationship Vex.

According to the present invention, the drain end where the high electric field intensity is concentrated is formed of a well with a low impurity concentration. As a result, the extreme electric field concentration can be alleviated, and the reliability of device operation is improved. Can be done.

By using at least two or more types of n-type impurity elements having different thermal diffusion rates in the silicon substrate as impurity elements in the drain region, two or more types of n-type wells utilizing the difference in thermal diffusion rates can be used. , Can be easily formed.

If a phosphorus element having a high thermal diffusion rate and an arsenic element having a low thermal diffusion rate are used as the impurity elements, an n-well having a low impurity concentration and an n + well having a high impurity concentration can be easily formed. it can.

Further, according to the present invention, in the field emission type electron source device, since a part of the channel gate electrode covers the drain end region, the drain current flowing from the source to the drain is diffused in the drain end region. As a result, the current density can be reduced.

Further, according to the present invention, in the field emission type electron source device, a thick insulating film for an extraction electrode requiring high voltage application and a thin insulating film for low voltage driving are required. The insulating film for a field effect transistor can be functionally separated. Further, by adopting a structure in which the gate insulating film is embedded with the insulating film, a multilayer wiring can be formed, and a wiring for driving the matrix can be easily formed.

If the gate insulating film is formed of a silicon thermal oxide film formed in the step of sharpening the thermal oxidation of the cathode of the field emission electron source, it is possible to use a precisely controlled high-quality thermal oxide film. , High reliability,
The control of the FET can be performed with high accuracy.

Further, according to the present invention, in the field emission type electron source device, the influence of the external electric field can be suppressed by covering the channel region of the field effect transistor portion with the shield electrode. Further, the wiring process can be simplified by using the same material as the gate electrode.

By adding a structure in which the shield electrode is maintained at the same potential as the p-type silicon substrate and has a function of blocking the influence of an electric field from an external electric field other than the gate electrode, the shield electrode has the same potential as the p-type silicon substrate. Since the electric field is maintained at the electric potential, the function of shielding from an external electric field can be more reliably exhibited.

Further, according to the present invention, in the field emission type electron source device, the arrangement of the electrodes such as the gate electrode can be designed symmetrically in a plane centering on the drain, thereby facilitating the electron focusing operation.

Further, according to the present invention, the step of introducing impurities by ion implantation into the drain region can be simplified, manufacturing costs can be reduced, and at the same time, the occurrence of variations in cathode shape due to ion implantation into the cathode can be suppressed.

Further, the outer peripheral portion of the drain and the inner peripheral portion of the source in contact with the channel region of the field effect transistor portion
With the configuration having a circular shape formed on each concentric circle, carrier injection from the source region to the drain region is made uniform, and good transistor characteristics can be obtained.

At least a part of the gate electrode formed between the source region and the drain region for controlling the channel region has a symmetrical arc shape. And the convergence operation can be performed more uniformly.

Further, Vg <Vg <1 between the first voltage (Vex) applied to the extraction electrode of the field emission electron source and the second voltage (Vg) applied to the gate electrode of the field effect transistor. With the configuration having the relationship of Vex, the electron convergence operation can be performed more reliably.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of a specific embodiment of the present invention, the following describes the results of a study by the present inventor on the problems of a conventional field emission electron source device. The problems with the prior art described below are as follows.
This has not been recognized in the art.

First, problems of the first conventional example will be described.

In the configuration shown in FIG. 8A, the gate 8 is controlled with the gate-source control voltage Vgs appropriately applied to the gate 808, that is, with the channel gate of the FET opened.
When the gate voltage Vg is applied to the electric field 05, electric field emission is generated from the tip of the emitter of the field emission cathode element at a certain voltage or more, and the field emission electrons flow from the tip of the emitter toward the anode 809. At this time, since the channel resistance of the FET is sufficiently high, the drain potential increases according to the flow rate of the field emission electrons.

This drain potential mainly depends on the product of the channel resistance, which is a design parameter of the FET, and the field emission electron flow rate, which is an operating condition. Field emission electron flow is FE
The brightness is set according to the required brightness of the D panel, but is usually set to about 1 μA per pixel. Furthermore, it has been experimentally confirmed that the drain potential rises to several volts or more when a small element size of a micron level is assumed using a normal FET having a power supply voltage of about 3.5 V. Further, in order to design the operating voltage of the FET lower, it is necessary to further design the channel resistance, and in order to increase the luminance, it is necessary to increase the flow rate of the field emission electrons. It is considered that the drain potential becomes higher.

According to the study by the present inventors, it has been confirmed that the rise of the drain potential as described above causes some problems in the operation of the field emission type electron source device. One of them is the hot electron phenomenon.

Under the condition that the potential between the source and the drain exceeds the band gap energy of silicon, 1.1 eV, FE
When T is operated for a long time, a phenomenon occurs in which electrons accelerated by the electric field between the source and the drain are injected into the gate insulating film interface near the drain. The injected electrons stay in the vicinity of the gate insulating film to cause a function of canceling a gate voltage, or form an interface state at an interface of the gate insulating film to generate a leak current through the gate insulating film, and the like. Causes the deterioration of the FET performance.

Further, the present inventors have found that an impact ionization phenomenon is a factor that causes a change in the characteristics of the FET.

That is, when the source / drain potential becomes extremely high at 10 V or more with the application of a voltage to the extraction electrode, electrons accelerated at a high speed have a large kinetic energy during the mean free path. When electrons having such a large kinetic energy are scattered, a pair of hole electrons is generated. Carriers generated by this generate new carriers one after another,
A so-called avalanche multiplication phenomenon occurs, causing an extremely large current change (increase). This, in the end,
It is also expected that this will lead to the destruction of the FET element.

These FEs generated by hot electrons
Deterioration of T characteristics, fluctuations in FET characteristics due to impact ionization, device destruction, and the like are major obstacles to long-term reliability operation of the device, and are serious problems particularly in promoting low-voltage operation and high integration of the device.

On the other hand, there is a phenomenon in which the FET characteristics change due to the influence of a high external electric field near the FET element.

In order to generate electric field emission from the tip of the emitter of the field emission cathode element, it is usually necessary to apply a gate voltage Vg of several tens V or more to the gate. Here, when a field emission cathode device and a corresponding FET device are integrated at a high density in order to realize a high-definition display, an electric field from a high gate voltage is generated due to the close proximity of the gate and the channel portion of the FET. , Is expected to affect the channel portion of the FET. In this case, the above-described external electric field apparently lowers the channel resistance and causes a phenomenon that the field emission electron flow rate, which was originally controlled stably by the source-gate voltage Vsg of the FET, increases. The higher the gate voltage Vg, the lower the source-gate voltage Vsg, and the higher the integration density of the device, the greater the risk of being affected by an external electric field. The problem of an increase in the field emission electron flow rate due to the external electric field is also a factor that hinders stable emission current control, and is a major obstacle in practical application.

Next, problems of the second conventional example will be described.

When a negative potential with respect to the first gate electrode 92 is applied to the second gate electrode 94, the negative potential becomes
It acts not only on the electrons emitted from the emitter but also on the electric field at the tip of the emitter. In the case where the opening diameter of the extraction electrode is about 1 μm, it is necessary to apply a potential of about 60 V to the first gate electrode 92 in order to obtain sufficient field emission.

In order to enhance the effect of the convergence of the electron beam, it is necessary to apply a relatively low negative potential to the second gate electrode 94. However, experimentally, a voltage of about 10 V is applied. Sufficient convergence has been demonstrated. However, it has been confirmed by experiments by the present inventors that under the convergence condition, the amount of electrons simultaneously emitted from the emitter is reduced to a fraction.

As described above, in the structure of the second conventional example, the potential applied to the second gate electrode 94 has an effect of canceling the electric field intensity at the tip end of the emitter generated by the first gate electrode 92. As a result, the electric field intensity is weakened, and the electron emission amount is reduced. In this conventional configuration,
There is a trade-off relationship between the convergence effect and the amount of electron emission, confirming that there is an essential problem that sufficient convergence cannot be achieved while maintaining a sufficient amount of electron emission. Was done.

Hereinafter, some specific embodiments of the present invention achieved in consideration of the above-described results of the study on the prior art will be described with reference to the accompanying drawings.

(First Embodiment) Hereinafter, the structure of a field emission type electron source device according to a first embodiment of the present invention will be described.
This will be described with reference to FIGS. 1 (a) and 1 (b). FIG.
1A and 1B are a cross-sectional view and a plan view, respectively, of a field emission type electron source device according to the present embodiment.
(A) shows a cross-sectional structure taken along line II of (b).

In the structure of the present embodiment, 1 is a p-type silicon substrate, 2 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET), and 3 is a drain region of the FET. A second n-type semiconductor conductive portion having a high impurity concentration, a third n-type semiconductor conductive portion having a low impurity concentration serving as a drain region of the FET, and a tower-shaped field emission electron source having a circular cross section. An operating cathode 6 is an insulating layer made of a silicon oxide film functioning as a gate insulating film of a field emission type electron source and FET, 7
Is an extraction electrode for operating as a field emission electron source, 8 is a gate electrode for controlling the channel region of the FET, and 9 is a source electrode for the FET.

As shown in FIGS. 1A and 1B, in the field emission type electron source device of the present embodiment, a part of one main surface of the p-type silicon substrate 1 becomes a source of the FET. A first n-type semiconductor conductive portion 2 and a second
Are formed at a certain distance from each other, and a third n-type semiconductor conductive part having a low impurity concentration is located at a position surrounding the periphery of the second n-type semiconductor conductive part 3. The part 4 is selectively formed.

At this time, as the n-type impurity element for forming the second n-type semiconductor conductive part 3, phosphorus having a high thermal diffusion rate in the silicon substrate is used, and the third n-type semiconductor conductive part 4 is used.
When arsenic having a low thermal diffusion rate in a silicon substrate is used as an n-type impurity element for forming a semiconductor layer, the well structures having different impurity concentrations described above are formed simply and accurately in a self-aligned manner. be able to. This utilizes the principle that the impurity profile changes due to the difference in the thermal diffusion rate in the step of performing a heat treatment after optimally implanting ion implantation of two or more different elements using the same mask. That is, an element having a high thermal diffusion rate (such as phosphorus) is redistributed deeper and more widely than an impurity profile at the beginning of implantation, as compared with an element having a low thermal diffusion rate (such as arsenic).

Second n-type semiconductor conductive portion 3 serving as a drain
Is formed with a tower-shaped cathode 5 having a circular cross section. The tip of the tower-shaped cathode 5 made of silicon has a tip microstructure on the order of nanometers formed by a sharpening process using thermal oxidation. A conductive lead electrode 7 is formed near the cathode 5 via an insulating film 6 made of a silicon oxide film having a circular opening. First n-type semiconductor conductive part 2 serving as a source, second n-type semiconductor conductive part 3 serving as a drain, and third n-type semiconductor conductive part 3
A gate electrode 8 for the FET is formed on the insulating film 6 in a channel region of the FET located between the mold semiconductor conductive portion 4 and the FET. Further, a source electrode 9 is formed on the source n-type semiconductor conductive portion 2 via a contact window.

Hereinafter, the operation of the field emission type electron source device according to the present embodiment having the above configuration will be described.

The p-type silicon substrate 1 and the first n-type semiconductor conductive portion 2 serving as a source region are grounded, and a positive voltage Vex is applied to the extraction electrode 7. Furthermore, when a predetermined voltage Vg is applied to the gate electrode 8 of the FET, the channel region below the gate electrode 8 is opened, and the conditions for injecting electron carriers from the source to the drain are established.
Under this condition, a positive voltage Vex is applied to the extraction electrode 7. In a field emission electron source having a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers, electrons start to be field-emitted from the tip of the cathode 5 by applying a voltage of usually several tens of volts. The emitted electrons are
(A) and (b) proceed while being accelerated toward an anode plate that is arranged opposite to the p-type silicon substrate 1 not shown.

In this case, the amount of the electron current emitted from the cathode 5 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 7, but is applied to the gate electrode 8 of the FET connected to the cathode 5. It is controlled by the applied variable gate-source control voltage Vg. That is, FET
Operates in a constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 8. As described above, the amount of electron flow radiation emitted from the cathode 5 in the electric field is determined by the characteristics of the FET connected in series to the emitter and having a function of supplying emitted electrons. Therefore, by optimally designing the FET, the operating conditions of the FET and the field emission electron flow rate can be designed in advance. In particular, FE
By performing field emission in the saturation operation region of T, extremely stable and precisely controlled field emission electron flow can be obtained without being affected by the instability factor of the emitter itself.

Here, the function of the third n-type semiconductor conductive portion 4 will be described in detail.

The feature of the drain structure of the present embodiment is that a plurality of drain well structures having two or more impurity concentrations (so-called twin well structures) are employed. The field-emitted electron flow is basically supplied from the source of the FET, but the channel region between the source and the drain has a high resistance. To rise. Experiments have confirmed that in the case of an FET formed by a submicron process and operating at a power supply voltage of about 3.5 volts, assuming a channel current of about 1 microamp, the drain potential reaches several volts or more. The electrons injected from the source are accelerated and injected into the drain by the electric field in the channel generated by the drain potential.

However, the channel electric field is not generated uniformly in the channel region, but concentrates near the drain on the surface of the silicon substrate. As a result, the electrons traveling in the channel become high-energy electrons (hot electrons) under the influence of the high electric field intensity particularly near the drain. The hot electrons have higher energy as the electric field intensity near the drain increases, and may cause various problems such as an increase in a threshold voltage for ON / OFF control of the FET and a decrease in drain current. There is.

On the other hand, by arranging the third n-type semiconductor conductive portion 4 at the drain end as described in this embodiment, it is possible to suppress the deterioration of the FET performance due to the hot electrons described above.

Usually, since the drain has a high impurity concentration, the pn junction at the end of the drain is close to an abrupt junction (steep junction). However, as described in the present embodiment, the n-type semiconductor conductive portion 3 of the drain having a high impurity concentration is used.
, The pn junction at the drain end becomes a gentle junction, and as a result, the electric field concentration at the drain end can be reduced. With this effect, it is possible to eliminate a factor that causes the performance degradation of the FET due to hot electrons, and it is possible to guarantee a very stable and stable device operation for a long period of time, so that the device reliability can be significantly improved.

In the description of the present embodiment, an example in which the shape of the cathode 5 is a tower shape has been described, but the same effect can be obtained with a conventional conical cathode shape. In addition, the cathode 5
In this example, a p-type silicon substrate is formed by processing a p-type silicon substrate, but a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, diamond-like carbon, or the like) is used. The same effect can be obtained by using ()).

(Second Embodiment) Hereinafter, the structure of a field emission type electron source device according to a second embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG.
2A and 2B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
(A) shows a cross-sectional structure taken along line II of (b).

In the structure of the present embodiment, 1 is a p-type silicon substrate, 2 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET), and 3 is a drain region of the FET. A second n-type semiconductor conductive portion having a high impurity concentration, a third n-type semiconductor conductive portion having a low impurity concentration serving as a drain region of the FET, and a tower-shaped field emission electron source having a circular cross section. An operating cathode 6 is an insulating layer made of a silicon oxide film functioning as a gate insulating film of a field emission type electron source and FET, 7
Is an extraction electrode for operating as a field emission electron source, 8T is a T-shaped gate electrode for controlling the channel region of the FET, and 9 is a source electrode for the FET.

As shown in FIGS. 2A and 2B, in the field emission type electron source device according to the present embodiment, a part of one main surface of the p-type silicon substrate 1 becomes a source of the FET. An n-type semiconductor conductive portion 2 serving as a drain and an n-type semiconductor conductive portion 3 serving as a drain are formed. Further, an n-type semiconductor conductive portion 4 having a low impurity concentration is selectively located at a position surrounding the periphery of the n-type semiconductor conductive portion 3. Is formed.

On the surface of the n-type semiconductor conductive portion 3 serving as a drain, a tower-shaped cathode 5 having a circular cross section is formed. At the tip of the tower-shaped cathode 5 made of silicon, a tip microstructure on the order of nanometers is formed by a sharpening process utilizing thermal oxidation. A conductive lead electrode 7 is formed near the cathode 5 via an insulating film 6 made of a silicon oxide film having a circular opening. In the channel region of the FET located between the source n-type semiconductor conductive part 2 and the drain n-type semiconductor conductive part 3 and the n-type semiconductor conductive part 4, a gate electrode 8T for the FET is formed on the insulating film 6. Is formed. This gate electrode 8T
Is different from a conventional gate electrode structure having a single width.
It has a plurality of types of gate widths (so-called T-shaped gate structure). Part of the gate electrode 8T is disposed so as to cover the surface of the n-type semiconductor conductive portion 4 having a low impurity concentration, which is located in the channel region of the FET and located at the drain end. Furthermore, on the n-type semiconductor conductive part 2 of the source,
Source electrode 9 is formed via a contact window.

The operation of the field emission type electron source device according to the present embodiment having the above-described configuration will be described below.

The p-type silicon substrate 1 and the source n-type semiconductor conductive portion 2 are grounded, and a positive voltage V
ex. Further, when a predetermined voltage Vg is applied to the gate electrode 8T of the FET, the channel region below the gate electrode 8T is in an open state, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, when a positive voltage Vex is applied to the extraction electrode 7, in a field emission electron source having a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers, a voltage of usually several tens of volts is applied. Electrons begin to be field-emitted from the tip of the cathode 5. The emitted electrons travel while being accelerated toward an anode plate arranged opposite to the p-type silicon substrate 1 not shown in FIG.

In this case, the amount of electron current emitted from the cathode 7 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 7, but is applied to the gate electrode 8 T of the FET connected to the cathode 5. It is controlled by the applied variable gate-source control voltage Vg. That is, FET
Operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 8T. The amount of electron flow emitted from the cathode 5 in the field emission is determined by the characteristics of an FET connected in series to the emitter and having a function of supplying emitted electrons. Therefore, by optimally designing the FET, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular,
By performing the field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result without being affected by the instability factor of the emitter itself.

Here, the function of the gate electrode 8T having two or more different gate widths and arranged so as to cover the drain end region will be described in detail.

The field-emitted electron flow is basically supplied from the source of the FET. Since the channel region between the source and the drain has a high resistance, the drain potential increases in accordance with the amount of electron current emission, that is, the amount of channel current.
Experiments have confirmed that in the case of an FET formed by a submicron process and operating at a power supply voltage of about 3.5 volts, assuming a channel current of about 1 microamp, the drain potential reaches several volts or more. The electrons injected from the source are accelerated by the electric field in the channel generated by the drain potential and injected into the drain.

However, the channel electric field is not generated uniformly in the channel region, but concentrates near the drain on the surface of the silicon substrate. As a result, the electrons traveling in the channel become high-energy electrons (hot electrons) under the influence of the high electric field intensity particularly near the drain. The hot electrons have higher energy as the electric field intensity near the drain increases, and may cause various problems such as an increase in a threshold voltage for ON / OFF control of the FET and a decrease in drain current. There is.

On the other hand, by arranging the gate electrode 8T (so-called T-shaped gate structure) described in the present embodiment so as to cover the drain end, the above-mentioned hot electron phenomenon can be suppressed.

As shown in FIG. 2B, the gate electrode 8T
If one end is disposed so as to cover the n-type semiconductor conductive portion 4 in the drain end region, the electrons injected from the source of the FET travel along the channel formed in the lower region of the gate electrode 8T. The current path is expanded in the n-type conductive region. As a result, in the drain end region of the gate electrode 8T, the drain current density is greatly reduced as compared with other regions. The hot electron phenomenon depends on the drain current density as well as the electric field strength, and as a result, has the effect of greatly reducing the performance degradation of the FET due to the hot electrons.

Further, the gate electrode structure having a plurality of widths (so-called T-shaped gate structure) described in the present embodiment is also effective in terms of design flexibility.

The amount of drain current flowing through the channel of the FET is determined depending on the parameter (W / L) of the width (W) and length (L) of the gate electrode. Since the width of the drain is inevitably determined by the degree of integration and arrangement of the entire device, it is often difficult to freely design the width (W) of the gate electrode. However, by adopting the T-shaped gate structure described in the present embodiment, after arranging a part of the gate so as to cover the drain end region, the remaining gate part has elements of width (W) and (L). The dimensions can be freely set, and the degree of freedom in device design is improved.

With this effect, it is possible to eliminate a factor that causes deterioration of the performance of the FET due to hot electrons while securing the degree of freedom in element design, and it is possible to assure extremely stable and stable device operation for a long period of time. Properties can be significantly improved.

In the description of the present embodiment, an example in which the shape of the cathode 5 is a tower shape has been described. However, a similar effect can be obtained with a conventional conical cathode shape. In addition, the cathode 5
In this example, a p-type silicon substrate is formed by processing a p-type silicon substrate, but a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, diamond-like carbon, or the like) is used. The same effect can be obtained by using ()).

(Third Embodiment) Hereinafter, the structure of a field emission type electron source device according to a third embodiment of the present invention will be described.
This will be described with reference to FIG. FIG. 3 is a cross-sectional view of the field emission type electron source device according to the present embodiment.

In the structure of the present embodiment, 31 is a p-type silicon substrate, 32 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET), and 33 is a drain region of the FET. A second n-type semiconductor conductive portion having a high impurity concentration, a third n-type semiconductor conductive portion having a low impurity concentration serving as a drain region of an FET, and a tower-shaped field emission type electron source having a circular cross section. An operating cathode 36 is a lower insulating layer made of a silicon oxide film functioning as a gate insulating film of the FET, 37
Is an upper insulating layer made of a silicon oxide film functioning as a field emission electron source extraction electrode, 38 is an extraction electrode for operating as a field emission electron source, and 39 is FE.
A gate electrode for controlling the channel region of T, and a source electrode 40 for the FET.

As shown in FIG. 3, in the field emission type electron source device according to the present embodiment, the n-type semiconductor conductive portion 32 serving as the source of the FET is formed on a part of one main surface of the p-type silicon substrate 31. An n-type semiconductor conductive portion 33 serving as a drain is formed, and an n-type semiconductor conductive portion 34 having a low impurity concentration is selectively formed at a position surrounding the periphery of the n-type semiconductor conductive portion 33.

On the surface of the n-type semiconductor conductive portion 33 serving as a drain, a tower-shaped cathode 35 having a circular cross section is formed. The tip of the tower-shaped cathode 35 made of silicon has a tip microstructure on the order of nanometers formed by a sharpening process utilizing thermal oxidation. A conductive lead electrode 38 is formed near the cathode 35 via a lower insulating film 36 and an upper insulating film 37 made of a silicon oxide film having a circular opening. Source n
-Type semiconductor conductive part 32 and drain n-type semiconductor conductive part 33
In the channel region of the FET located between the n-type semiconductor conductive portion 34 and the n-type semiconductor conductive portion 34, a gate electrode 39 for the FET having a configuration embedded on the lower insulating film 36 and embedded in the upper insulating film 37 is formed. ing. The lower insulating film 36 is formed of the cathode 3
The thermal oxide film formed by the sharpening process of No. 5 is used.
Further, a source electrode 40 is formed on the source n-type semiconductor conductive portion 32 via a contact window.

Hereinafter, the operation of the field emission type electron source device according to the present embodiment having the above configuration will be described.

The p-type silicon substrate 31 and the first n-type semiconductor conductive portion 32 are grounded, and a positive voltage Vex is applied to the extraction electrode 38. Furthermore, when a predetermined voltage Vg is applied to the gate electrode 39 of the FET, the channel region below the gate electrode 39 is opened, and the conditions for injecting electron carriers from the source to the drain are established. The lower insulating film 36 is desirably of good quality and thin conditions in order to reduce the threshold voltage of the FET.

Under these conditions, a positive voltage Vex is applied to the extraction electrode 38. In a field emission electron source in which a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers are formed, a voltage of usually several tens of volts is applied.
Electrons begin to be field-emitted from the tip of the cathode 35. The emitted electrons proceed while being accelerated toward an anode plate which is not shown in FIG. 3 and is opposed to the p-type silicon substrate 31.

In this case, the amount of the electron current emitted from the cathode 35 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 38, but is applied to the gate electrode 39 of the FET connected to the cathode 35. It is controlled by the applied variable gate-source control voltage Vg. That is,
The FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 39. As described above, the amount of electron flow radiation emitted from the cathode 35 in the electric field is determined by the characteristics of the FET connected in series to the emitter and having the function of supplying the emitted electrons. Therefore, by optimally designing the FET, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular, the field emission in the saturation operation region of the FET is not affected by the instability factor of the emitter itself, and as a result,
An extremely stable and precisely controlled field emission electron flow can be obtained.

Here, the lower insulating film 36 and the upper insulating film 37
The function of the gate electrode 39 having the structure embedded by the above will be described in detail.

The lower insulating film 36 of this embodiment is mainly made of FE
Functions as a gate insulating film for T. FET ON / O
The threshold voltage at the time of performing FF strongly depends on the thickness of the gate insulating film. In order to operate at a lower voltage, a thin and high quality insulating film is required. On the other hand, for the extraction electrode 38 for the field emission electron source, a laminated film of the lower insulating film 36 and the upper insulating film 37 is used. In order to apply a high voltage of several tens of volts to the extraction electrode 38, a thick insulating film is required in consideration of the withstand voltage. Further, by applying a voltage to the extraction electrode 38, the O.D.
When performing N / OFF control, it is advantageous to design the insulating film to be thicker in terms of operation speed and power consumption.

Therefore, if the gate having the structure described in this embodiment is adopted, the gate insulating film for the FET and the insulating film for the field emission electron source can be designed independently, and the high performance of the device can be achieved. It is easy to plan.

Further, the gate electrode 39 is formed on the upper insulating film 37.
, A multilayer wiring structure generally used in LSI can be easily obtained. By using the multi-layer wiring, it is possible to easily realize a matrix driving wiring structure in the x and y directions that is impossible with a single-layer wiring.

In the description of the present embodiment, an example in which the shape of the cathode 35 is a tower shape has been described. However, a similar effect can be obtained with a conventional conical cathode shape. Further, as the material of the cathode 35, an example in which a p-type silicon substrate is formed by processing is used, but a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, or The same effect can be obtained by using diamond-like carbon or the like.

(Fourth Embodiment) Hereinafter, the structure of a field emission type electron source device according to a fourth embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG.
4A and 4B are a cross-sectional view and a plan view, respectively, of the field emission electron source device according to the present embodiment.
(A) shows a cross-sectional structure taken along line II of (b).

In the structure of the present embodiment, 41 is a p-type silicon substrate, 42 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET), and 43 is a drain region of the FET. A second n-type semiconductor conductive portion having a high impurity concentration; 44, a third n-type semiconductor conductive portion having a low impurity concentration serving as a drain region of the FET; and 45, a tower-shaped field emission electron source having a circular cross section. The operating cathode 46 is a lower insulating layer made of a silicon oxide film functioning as a gate insulating film of the FET.
Is an upper insulating layer made of a silicon oxide film functioning as a field emission electron source extraction electrode, 48 is an extraction electrode for operating as a field emission electron source, 49 is FE
A gate electrode for controlling the channel region of T; 50, a shield electrode from an external electric field in the channel region of the FET;
151 is a source electrode for FET.

As shown in FIGS. 4A and 4B, in the field emission type electron source device according to the present embodiment, a part of one main surface of the p-type silicon substrate 41 becomes a source of the FET. An n-type semiconductor conductive part 43 and an n-type semiconductor conductive part 43 serving as a drain are formed.
An n-type semiconductor conductive portion 44 having a low impurity concentration is selectively formed at a position surrounding the periphery of the semiconductor device 3. On the surface of the n-type semiconductor conductive portion 43 serving as a drain, a tower-shaped cathode 45 having a circular cross section is formed. The tip of the tower-shaped cathode 45 made of silicon has a tip microstructure on the order of nanometers formed by a sharpening process utilizing thermal oxidation. A conductive lead electrode 48 is formed adjacent to the cathode 45 via a lower insulating film 46 and an upper insulating film 47 made of a silicon oxide film having a circular opening. Source n-type semiconductor conductive part 42, drain n-type semiconductor conductive part 43 and n-type semiconductor conductive part 44
An FET gate electrode 49 having a configuration embedded on the lower insulating film 46 and buried in the upper insulating film 47 is formed in the channel region of the FET located therebetween. Further, in the channel region of the FET, a region where the gate electrode 49 for the FET is not formed is covered.
A shield electrode 50 made of the same material as the gate electrode 49 is provided. As the lower insulating film 46, a thermal oxide film formed by a sharpening process of the cathode 45 is used. Further, a source electrode 151 is formed on the source n-type semiconductor conductive portion 42 via a contact window.

The operation of the field emission type electron source device according to the present embodiment having the above configuration will be described below.

The p-type silicon substrate 41, the source n-type semiconductor conductive portion 42 and the shield electrode 50 are grounded, and a positive voltage Vex is applied to the extraction electrode 48. Further, F
When a predetermined voltage Vg is applied to the gate electrode 49 of ET,
The channel region below the gate electrode 49 is opened, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, a positive voltage Vex is applied to the extraction electrode 48. In a field emission electron source in which a gate opening diameter on the order of submicron and a cathode tip on the order of nanometers are formed, electrons start to be field-emitted from the tip of the cathode 45 by applying a voltage of usually several tens of volts. The emitted electrons are supplied to a p-type silicon substrate 41 (not shown).
It proceeds while being accelerated toward the anode plate arranged opposite to the anode plate.

In this case, the amount of the electron current emitted from the cathode 45 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 48, but to the gate electrode 49 of the FET connected to the cathode 45. It is controlled by the applied variable gate-source control voltage Vg. That is,
The FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to its gate electrode 49. As described above, the amount of the electron current radiated from the cathode 45 in the electric field is supplied to the FE which is connected in series to the emitter and has a function of supplying emitted electrons.
It will be determined by the characteristics of T. Therefore, FE
By optimally designing T, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular, by radiating electric field in the saturation operation region of the FET, without being affected by the instability factor of the emitter itself,
As a result, a very stable and precisely controlled field emission electron flow can be obtained.

Here, the function of the shield electrode 50 will be described in detail.

When the above-mentioned field emission type electron source is operated in a predetermined vacuum atmosphere, electrons field-emitted from the cathode 45 collide with residual gas molecules in the vacuum atmosphere to ionize them. This ionization strongly depends on the degree of vacuum to be operated, the type and concentration of residual molecules, the intensity of an external electric field for accelerating electrons, the density of electrons emitted by an electric field (emission current amount), and the like. Among the generated ions, positively charged ions (positive ions) receive an electric field in the direction opposite to the electrons, are guided toward the substrate, and are irradiated on the silicon substrate 41. In the element structure described in the present embodiment, the outermost surface is covered with the upper insulating film 47. When the cations are continuously irradiated on the upper insulating film 47 at a certain density or higher,
Positive charge is gradually charged on the upper insulating film 47, and a positive charge voltage is generated.

If the FET does not have the shield electrode 50, the following problem occurs.

When the charge voltage generated above the channel region of the FET due to the ion irradiation z exceeds the operating voltage of the FET, a malfunction occurs. In addition to the normally controlled drain current, an additional drain current due to the charge voltage flows, thereby impairing the current control characteristics of the FET.

On the other hand, as described in this embodiment, by covering the channel region with the shield electrode 50 connected to the substrate and the conductive potential, even if a charge voltage is generated, the electric field to the channel region can be reduced. Since the influence can be prevented by the shield effect, a change in the characteristics of the FET can be prevented.

It is considered that an actual panel requires an emission operation in a low vacuum atmosphere of about 10 ⁻⁶ Torr, so that the influence of the above-described ion irradiation is expected to increase. Even in such a case, a change in the characteristics of the FET can be prevented by employing the shield electrode, and a stable emission operation can be performed over a long period of time, so that the device reliability can be significantly improved.

In the description of the present embodiment, an example in which the shape of the cathode 45 is a tower shape has been described. However, the same effect can be obtained with a conventional conical cathode shape. Further, as the material of the cathode 45, an example in which a p-type silicon substrate is formed by processing is used, but a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, or The same effect can be obtained by using diamond-like carbon or the like.

(Fifth Embodiment) Hereinafter, the structure of a field emission type electron source device according to a fifth embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG.
5A and 5B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
(A) shows a cross-sectional structure taken along line II of (b).

In the structure of this embodiment, reference numeral 51 denotes a p-type silicon substrate; 52, a first n-type semiconductor conductive portion serving as a source region of an element operating as a field-effect transistor (FET); 53, a drain region of the FET; A second n-type semiconductor conductive part 54 having a high impurity concentration;
Reference numeral 5 denotes a first insulating layer mainly made of a silicon oxide film functioning as a gate insulating film of the FET, and reference numeral 56 denotes a second insulating layer mainly made of a silicon oxide film mainly functioning as an extraction electrode insulating film of a field emission electron source. A layer 57 is a gate electrode for controlling a channel region for the FET, 58 is a source electrode for the FET, and 59 is a lead electrode for the cathode.

As shown in FIGS. 5A and 5B,
In the field emission electron source device according to the present embodiment, a first n-type semiconductor conductive portion 52 serving as a source of the FET and a second n-type semiconductor conductive portion 52 serving as a drain are formed on a part of one main surface of the p-type silicon substrate 51. A semiconductor conductive part 53 is formed, and the second n-type semiconductor conductive part 53 is formed of a first n-type semiconductor conductive part 52.
Takes a configuration that is arranged inside so as to surround the periphery.

Further, at least part of the surface of the channel region of the FET located between the first n-type semiconductor conductive part 52 serving as the source and the second n-type semiconductor conductive part 53 serving as the drain is provided with A gate electrode 57 having a structure embedded between the first insulating layer 55 and the second insulating layer 56 is formed. Further, a source electrode 58 is formed on the first n-type semiconductor conductive portion 52 via a contact window.

Second n-type semiconductor conductive portion 5 serving as a drain
On the surface of No. 3, a tower-shaped cathode 54 having a circular cross section is formed. Tower-shaped cathode 5 made of silicon
At the tip of No. 4, a tip microstructure on the order of nanometers is formed by a sharpening process utilizing thermal oxidation. Further, an extraction electrode 59 having a constant opening diameter and applying an electric field for electron emission is provided around the cathode 54.
Are formed on the second insulating layer 56.

The operation of the field emission electron source device according to the present embodiment having the above configuration will be described below.

A p-type silicon substrate 51 and a first n-type semiconductor conductive portion 52 serving as a source region are grounded, and a positive voltage Vex is applied to an extraction electrode 59. Further, when a predetermined voltage Vg is applied to the gate electrode 57 of the FET, the channel region below the gate electrode 57 is opened,
The conditions for injecting electron carriers from the source to the drain are set. Under this condition, a positive voltage Vex is applied to the extraction electrode 59. The application conditions of Vex and Vg at this time are set so as to satisfy the relationship of Vg <Vex. In a field emission electron source having a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers, electrons begin to be field-emitted from the tip of the cathode 54 by applying a voltage of usually several tens of volts. The emitted electrons travel while being accelerated toward an anode plate, which is opposed to a p-type silicon substrate 51 (not shown).

In this case, the amount of the electron current emitted from the cathode 54 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 59, but is applied to the gate electrode 57 of the FET connected to the cathode 54. It is controlled by the applied variable gate-source control voltage Vg. That is,
The FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 57. As described above, the amount of electron flow radiation emitted from the cathode 54 in the electric field is determined by the FE having the function of supplying the emitted electrons connected in series to the emitter.
It will be determined by the characteristics of T. Therefore, FE
By optimally designing T, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular, by radiating electric field in the saturation operation region of the FET, without being affected by the instability factor of the emitter itself,
As a result, a very stable and precisely controlled field emission electron flow can be obtained.

Here, the arrangement of the source and the drain, which is a feature of this embodiment, will be described.

A feature of the drain structure of this embodiment is that it has an island structure whose outer peripheral portion is surrounded by a source region and a channel region. Further, gate electrodes for controlling the operation of the FET are symmetrically arranged around the cathode of the field emission electron source. By employing this arrangement, carriers can be uniformly injected from the source region to the drain region.

In the drain having the normal structure, carriers are injected from a part of the boundary in contact with the channel region. In this case, the injected carriers diffuse in the drain and reach the cathode of the field emission electron source. Therefore, it is expected that the carrier concentration varies depending on the position of the drain. On the other hand, in the configuration of the present embodiment described above, such a problem does not occur.

In the above description, the configuration in which one cathode is formed in the drain has been described. However, when the cathode is used as an FED pixel, a multi-emitter configuration in which several hundreds of cathodes are formed in the drain per pixel is usually used. Used. If the density of carriers in the drain is different, it is expected that the amount of electrons emitted from the cathode varies depending on the position of the cathode.However, in the present invention, the gate is arranged symmetrically with respect to the drain on which the cathode is formed. Since carriers are injected uniformly and symmetrically through the electrodes, variations in electron emission in the drain are also suppressed.

Further, the extraction electrode of the present invention is effective not only for controlling the amount of emitted electrons but also for controlling the beam trajectory of emitted electrons.

By setting the relationship between the voltage Vg applied to the gate electrode of the FET and the extraction voltage Vex for operating the cathode in advance under an optimal condition of Vg <Vex, the emitted electrons can be reduced. Under the influence of the electric field of Vg in a vacuum, a convergence effect is exhibited. This is because an electric potential of Vg set lower than Vex generates an electric field which has a converging effect on electrons emitted from the cathode and traveling toward the opposite anode. In particular, since a converged electric field from the gate electrode symmetrically arranged with respect to the cathode is generated symmetrically with respect to the electron trajectory, it has a good lens action which has not been achieved in the related art.

Further, the gate electrode 57 having a convergence effect is provided.
Is formed as a wiring buried between the first insulating layer 55 and the second insulating layer 56, and is formed at a position below the extraction electrode 59. With this relative arrangement, even when a voltage lower than Vex is applied to Vg, the influence of the gate electrode 57 is not affected by the cathode 54.
Less than.

In the conventional structure, the electron emission amount is reduced together with the convergence function. However, the structure of the present invention can have a sufficient convergence function while maintaining the electron emission amount.

As described above, in the configuration of the present embodiment, it is possible to suppress variations in electron emission in the drain and to achieve a beam convergence effect by symmetrically arranged gate electrodes.
Since a very high-density emitter operation with extremely small beam spread can be guaranteed, it can be expected as a good field emission electron source suitable for high definition display.

In the description of this embodiment, an example in which the shape of the cathode 54 is a tower shape has been described. However, the same effect can be obtained with a conventional conical cathode shape. Further, as an example of the material of the cathode 54, an example in which a p-type silicon substrate is formed by processing is used, but a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, or The same effect can be obtained by using diamond-like carbon.

(Sixth Embodiment) Hereinafter, the structure of a field emission type electron source device according to a sixth embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG.
6A and 6B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
(A) shows a cross-sectional structure taken along line II of (b).

In the structure of the present embodiment, 61 is a p-type silicon substrate, 62 is an n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET), and 63 is a tower-shaped electric field having a circular cross section. A cathode that operates as an emission electron source, 64 is a first insulating layer made of a silicon oxide film that mainly functions as a gate insulating film of an FET, and 65 mainly functions as an extraction electrode insulating film of a field emission electron source. A second insulating layer made of a silicon oxide film, 66 is a gate electrode for controlling the channel region for the FET, 67 is a source electrode for the FET, and 68 is a lead electrode for the cathode.

As shown in FIGS. 6A and 6B, in the field emission type electron source device of the present embodiment, a part of one main surface of the p-type silicon substrate 61 is provided with a second source serving as an FET. A field emission electron source section including one n-type semiconductor conductive section 62, a cathode 63, and an extraction electrode 68 is formed, and the field emission electron source section is internally surrounded by the n-type semiconductor conductive section 62. Take the configuration arranged in.

The n-type semiconductor conductive portion 62 serving as a source
A first insulating layer 6 is provided on at least a part of the surface of the channel region of the FET located between the
A gate electrode 66 for controlling a current through the gate electrode 4 is formed as a wiring embedded between the first insulating layer 64 and the second insulating layer 65 in a symmetrical arrangement with respect to the cathode 63. I have. Further, on the n-type semiconductor conductive portion 62 of the source,
A source electrode 67 is formed via a contact window.

On the surface of the silicon substrate 61 which is to be a drain region inside the n-type semiconductor conductive portion 62 of the source,
A tower-shaped cathode 63 having a circular cross section is formed. The tip of the tower-shaped cathode 63 made of silicon has a tip microstructure on the order of nanometers formed by a sharpening process using thermal oxidation. Further, a lead electrode 68 having a constant opening diameter and applying an electric field for electron emission is formed on the second insulating layer 65 around the cathode 63.

Hereinafter, the operation of the field emission electron source device according to the present embodiment having the above configuration will be described.

A p-type silicon substrate 61 and an n-type semiconductor conductive portion 62 serving as a source region are grounded, and a lead electrode 6 is connected.
8, a positive voltage Vex is applied. Further, when a predetermined voltage Vg is applied to the gate electrode 66 of the FET, the gate electrode 6
The channel region below 6 is opened, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, a positive voltage Vex is applied to the extraction electrode 68.
Is applied. The application condition of Vex and Vg at this time is Vg
<Set to satisfy the relationship of Vex. By applying a positive voltage to the extraction electrode, a depletion layer is formed in the surface layer of the p-type silicon substrate under the extraction electrode. Under a sufficiently high Vg voltage condition, an n-type inversion layer is formed on the surface of the depletion layer, and functions as a conductive layer for electron carriers. As a result, electrons injected from the channel region are guided toward the emitter through the formed n-type inversion layer. As a result, even if the n-type semiconductor conductive portion is not formed in the drain, substantially the same transistor operation can be performed by applying a constant voltage to Vex.

In a field emission electron source in which a gate opening diameter on the order of a submicron and a cathode tip on the order of nanometers are formed, electrons are usually emitted from the tip of the cathode 63 by applying a voltage of several tens of volts. start. The emitted electrons travel while being accelerated toward an anode plate that is arranged opposite to a p-type silicon substrate 61 (not shown).

In this case, the amount of the electron current emitted from the cathode 63 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 68 but is applied to the gate electrode 66 of the FET connected to the cathode 63. It is controlled by the applied variable gate-source control voltage Vg. That is,
The FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to its gate electrode 66. As described above, the amount of the electron current emitted from the cathode 63 in the electric field is determined by the FE having the function of supplying the emitted electrons connected in series to the emitter.
It is determined by the characteristics of T. Therefore, by optimally designing the FET, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result without being affected by the instability factor of the emitter itself.

Here, the arrangement of the source and the drain, which is a feature of the present embodiment, will be described.

The features of the field emission electron source of this embodiment are as follows.
It has an island structure in which the outer peripheral portion is surrounded by the source region and the channel region. Further, gate electrodes for controlling the operation of the FET are symmetrically arranged around the cathode of the field emission electron source. By adopting this arrangement, n generated from the source region below the extraction electrode
Carriers can be evenly injected into the mold inversion layer region. In the drain having the normal structure, carriers are injected from a part of the boundary in contact with the channel region. In this case, the injected carriers diffuse in the drain and reach the cathode of the field emission electron source. Therefore, it is expected that the carrier concentration varies depending on the position of the drain. On the other hand, in the configuration of the present embodiment described above, such a problem does not occur.

In the above description, a configuration in which one cathode is formed in the n-type inversion layer region functioning as a drain has been described. However, when the cathode is used as an FED pixel, several hundred cathodes per pixel are usually used. Is used.

When the carrier density in the drain is different, it is expected that the amount of electrons emitted from the cathode varies depending on the position of the cathode. However, in the present invention, the amount of electrons emitted from the cathode is different from that of the n-type inversion layer region where the cathode is formed. Carriers are injected uniformly and symmetrically through the symmetrically arranged gate electrodes, so that variations in electron emission in the n-type inversion layer region are suppressed.

Further, the extraction electrode of the present invention is effective not only for controlling the amount of emitted electrons but also for controlling the beam trajectory of emitted electrons. That is, the voltage Vg applied to the gate electrode of the FET and the extraction voltage Vex for operating the cathode.
Is set in advance under the optimal condition of Vg <Vex, the emitted electrons exhibit a convergence effect under the influence of the electric field of Vg in a vacuum. This is because an electric potential of Vg set lower than Vex generates an electric field which has a converging effect on electrons emitted from the cathode and traveling toward the opposite anode. Since the converged electric field from the gate electrode symmetrically arranged with respect to the cathode is generated symmetrically with respect to the electron trajectory, it has a good lens action which has not been achieved in the related art.

The gate electrode 66 having a convergence function is also provided.
Is formed as a wiring buried between the first insulating layer 64 and the second insulating layer 65, and is formed at a position below the extraction electrode 68. Due to this relative arrangement, even when a voltage lower than Vex is applied to Vg, the gate electrode 66 does not affect the cathode 63. In the conventional structure, the electron emission amount is reduced together with the convergence function. However, in the configuration of the present invention, it is possible to have a sufficient convergence function while maintaining the electron emission amount.

As described above, in the present embodiment, it is possible to suppress the variation in electron emission in the n-type inversion layer region functioning as the drain, and to expect the beam convergence effect of the symmetrically arranged gate electrodes. In addition, a high-density emitter operation with a small beam spread can be guaranteed. Accordingly, it can be expected as a good field emission electron source suitable for high definition display.

In the description of the present embodiment, an example in which the shape of the cathode 63 is a tower shape has been described, but the same effect can be obtained with a conventional conical cathode shape. In addition, as the material of the cathode 63, an example in which a p-type silicon substrate is formed by processing is used. However, a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, or The same effect can be obtained by using diamond-like carbon.

(Seventh Embodiment) Hereinafter, the structure of a field emission type electron source device according to a seventh embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG.
7A and 7B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
(A) shows a cross-sectional structure taken along line II of (b).

In the structure of the present embodiment, 71 is a p-type silicon substrate, 72 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET), and 73 is a drain region of the FET. A second n-type semiconductor conductive portion 74 having a high impurity concentration; a cathode 74 operating as a tower-shaped field emission electron source having a circular cross section;
Reference numeral 5 denotes a first insulating layer mainly composed of a silicon oxide film functioning as a gate insulating film of the FET. 76 is a second insulating layer made of a silicon oxide film mainly functioning as an insulating film for an extraction electrode of a field emission electron source, 77 is a gate electrode for controlling a channel region for an FET, and 78 is an FET
A source electrode 79 is a lead electrode for a cathode.

As shown in FIGS. 7A and 7B, in the field emission type electron source device of this embodiment, a part of one main surface of the p-type silicon substrate 71 becomes a source of the FET. A first n-type semiconductor conductive part 72 and a second n-type semiconductor conductive part 73 serving as a drain are formed, and a second n-type semiconductor conductive part 73 is formed.
The type semiconductor conductive portion 73 has a configuration arranged inside so as to be surrounded by the first n-type semiconductor conductive portion 72.

First n-type semiconductor conductive portion 72 serving as a source
N-type semiconductor conductive portion 7 serving as the inner peripheral shape and drain of
3 has a circular shape formed concentrically, and the channel region of the FET is located between the source region and the drain region and has a ring shape. Further, a ring-shaped gate electrode 77 buried between the first insulating layer 75 and the second insulating layer 76 is formed so as to cover the ring-shaped channel.

On the n-type semiconductor conductive portion 72 of the source,
A source electrode 78 is formed via a contact window.

Second n-type semiconductor conductive portion 7 serving as a drain
On the surface of No. 3, a tower-shaped cathode 74 having a circular cross section is formed. Tower-shaped cathode 7 made of silicon
At the tip of No. 4, a tip microstructure on the order of nanometers is formed by a sharpening process utilizing thermal oxidation. Further, a constant opening diameter is provided around the cathode 74,
Extraction electrode 7 for applying an electric field for electron emission
9 is formed on the second insulating layer 76.

The operation of the field emission electron source device according to the present embodiment having the above configuration will be described below.

The p-type silicon substrate 71 and the first n-type semiconductor conductive portion 72 serving as a source region are grounded, and a positive voltage Vex is applied to the extraction electrode 79. Further, when a predetermined voltage Vg is applied to the gate electrode 77 of the FET, the channel region below the gate electrode 77 is opened,
The conditions for injecting electron carriers from the source to the drain are set. Under this condition, a positive voltage Vex is applied to the extraction electrode 79. The application conditions of Vex and Vg at this time are set so as to satisfy the relationship of Vg <Vex. In a field emission electron source in which a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers are formed, electrons start to be field-emitted from the tip of the cathode 74 by applying a voltage of usually several tens of volts. The emitted electrons are represented by p (not shown).
It proceeds while being accelerated toward the anode plate arranged opposite to the mold silicon substrate 71.

In this case, the amount of electron current emitted from the cathode 74 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 79, but is applied to the gate electrode 77 of the FET connected to the cathode 74. It is controlled by the applied variable gate-source control voltage Vg. That is,
The FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to its gate electrode 77. As described above, the amount of electron flow radiation emitted from the cathode 74 in the electric field is determined by the FE having the function of supplying the emitted electrons connected in series to the emitter.
It will be determined by the characteristics of T. Therefore, FE
By optimally designing T, it becomes possible to design the operating conditions of the FET and the field emission electron flow rate in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result without being affected by the instability factor of the emitter itself.

Here, a ring-shaped gate electrode configuration which is a feature of the present embodiment will be described.

A feature of the drain structure of this embodiment is that it has an island structure whose outer peripheral portion is surrounded by a source region and a channel region. Gate electrodes for controlling the operation of the FET are symmetrically arranged in a ring around the cathode of the field emission electron source. By employing this arrangement, carriers can be uniformly injected from the source region to the drain region.

In the drain having the normal structure, carriers are injected from a part of the boundary in contact with the channel region. In this case, the injected carriers diffuse in the drain and reach the cathode of the field emission electron source. Therefore, it is expected that the carrier concentration varies depending on the position of the drain.

In the structure of this embodiment, a structure in which one cathode is formed in the drain has been described. However, when the structure is used as a pixel for FED, a multi-layer structure in which several hundreds of cathodes are formed in the drain per pixel is usually used. An emitter configuration is used. If the density of carriers in the drain is different, it is expected that the amount of electrons emitted from the cathode varies depending on the position of the cathode.However, in the present invention, the gate is arranged symmetrically with respect to the drain on which the cathode is formed. Since carriers are injected uniformly and symmetrically through the electrodes, variations in electron emission in the drain are also suppressed.

Further, the extraction electrode of the present invention is effective not only for controlling the amount of emitted electrons but also for controlling the beam trajectory of emitted electrons. That is, the voltage Vg applied to the gate electrode of the FET and the extraction voltage Ve for operating the cathode.
By setting the relationship of x in advance under an optimal condition of Vg <Vex, the emitted electrons exhibit a convergence effect under the influence of the electric field of Vg in a vacuum. This is because an electric potential of Vg set lower than Vex generates an electric field which has a converging effect on electrons emitted from the cathode and traveling toward the opposite anode. Since a converged electric field from the gate electrode arranged symmetrically with respect to the cathode in a ring shape is generated completely symmetrically with respect to the electron trajectory, it has a good lens action which has not been achieved in the prior art.

Further, the gate electrode 77 having a convergence function is provided.
Are formed as wiring embedded between the first insulating layer 75 and the second insulating layer 76, and the extraction electrode 79
It is formed at a lower layer position. With this relative arrangement, even when a voltage relatively lower than Vex is applied to Vg, the influence of the gate electrode 77 does not affect the cathode 7.
Less than four. In the conventional structure, the electron emission amount is reduced together with the convergence function. However, in the configuration of the present invention, it is possible to have a sufficient convergence function while maintaining the electron emission amount.

As described above, according to the present embodiment, it is possible to suppress a variation in electron emission in the drain and complete a beam convergence effect by the symmetrically arranged ring-shaped gate electrodes. High-density emitter operation with small beam spread can be guaranteed. Therefore, the obtained configuration can be expected as a good field emission electron source suitable for high definition display.

In the description of the present embodiment, an example in which the shape of the cathode 74 is a tower shape has been described. However, a similar effect can be obtained with a conventional conical cathode shape. Further, as the material of the cathode 74, an example in which a p-type silicon substrate is formed by processing is used, but a conventional metal material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (diamond, graphite, or The same effect can be obtained by using diamond-like carbon.

The features of the present invention in each of the embodiments described above can be appropriately combined and applied to the actual configuration of the field emission type electron source device.

[0168]

As described above, according to the field emission type electron source device of the present invention, since the drain end of the FET is formed of a well having a low impurity concentration, the electric field concentration near the drain during the operation of the FET can be reduced. It can be significantly reduced.
As a result, there is an advantage that performance degradation of the FET caused by hot electrons or the like can be prevented, and the reliability of device operation can be significantly improved.

Further, there is an advantage that a plurality of well structures having different impurity concentrations can be easily realized by utilizing the difference in the thermal diffusion rate of the impurity element.

Further, if a phosphorus element having a high thermal diffusion rate and an arsenic element having a low thermal diffusion rate used in a semiconductor process are used as an impurity element, there is a merit that an impurity profile having excellent controllability can be formed.

Further, if a part of the channel gate of the FET is arranged so as to cover the drain end region, the drain current density can be reduced, and as a result, there is an advantage that the performance of the FET is prevented from being deteriorated due to hot electrons.

Further, since the transistor gate insulating film for the FET can be set thin and the insulating film for the field emission electron source can be set thick, there is an advantage that the device performance can be improved. Further, since the channel gate electrode is configured to be embedded in the insulating film, a multilayer wiring can be easily formed, which is suitable for matrix driving wiring.

Further, if a silicon thermal oxide film is used as the gate insulating film, it is possible to perform FET control with excellent controllability and high reliability.

When the channel region of the FET is covered with a shield electrode except for the channel gate region, the influence of an external electric field due to ion charge during electron emission can be prevented.

Further, if the potential of the shield electrode is kept the same as the substrate potential, the effect of shielding from an external electric field is further enhanced.

If the gate electrode arrangement for controlling the FET is designed symmetrically with respect to the drain, the electron injection from the source to the drain can be made uniform, and the uniformity of electron emission can be improved. At the same time, by using a gate electrode located below the extraction electrode, the beam trajectory can be converged without reducing the amount of field emission.

Further, by using the inversion layer formed by the extraction electrode, the same function as that of the n-type semiconductor conductive layer can be provided, and the process can be simplified.

Furthermore, if the inner peripheral portion of the source and the outer peripheral portion of the drain are formed concentrically, carrier injection from the source to the drain is uniform, and good transistor characteristics can be obtained.

If the gate electrode of the FET is formed in a ring shape symmetrically with respect to the drain, the electron orbit convergence operation can be performed more reliably.

Between the voltage Vg applied to the gate electrode and the voltage Vex applied to the extraction electrode, Vg <Vex
With this relationship, a negative electric field effect can be generated on electrons emitted from the cathode, and the convergence of the electron orbit can be performed more reliably.

[Brief description of the drawings]

1 (a) and 1 (b) respectively show a first embodiment of the present invention.
3A and 3B are a cross-sectional view and a plan view schematically showing a configuration of a field emission type electron source device according to the embodiment, and FIG. 4A shows a cross-sectional structure taken along line II of FIG.

FIGS. 2 (a) and (b) respectively show a second embodiment of the present invention.
3A and 3B are a cross-sectional view and a plan view schematically showing a configuration of a field emission type electron source device according to the embodiment, and FIG.

FIG. 3 is a cross-sectional view schematically illustrating a configuration of a field emission electron source device according to a third embodiment of the present invention.

FIGS. 4 (a) and (b) respectively show a fourth embodiment of the present invention.
3A and 3B are a cross-sectional view and a plan view schematically showing a configuration of a field emission type electron source device according to the embodiment, and FIG.

FIGS. 5 (a) and (b) respectively show a fifth embodiment of the present invention.
3A and 3B are a cross-sectional view and a plan view schematically showing a configuration of a field emission type electron source device according to the embodiment, and FIG. 4A shows a cross-sectional structure taken along line II of FIG.

FIGS. 6 (a) and (b) respectively show a sixth embodiment of the present invention.
3A and 3B are a cross-sectional view and a plan view schematically showing a configuration of a field emission type electron source device according to the embodiment, and FIG.

FIGS. 7 (a) and (b) respectively show a seventh embodiment of the present invention.
3A and 3B are a cross-sectional view and a plan view schematically showing a configuration of a field emission type electron source device according to the embodiment, and FIG. 4A shows a cross-sectional structure taken along line II of FIG.

FIG. 8A is a cross-sectional view schematically showing a configuration of a conventional field emission electron source device, and FIG.
FIG. 3 is an equivalent circuit diagram of the configuration of FIG.

FIG. 9 is a cross-sectional view schematically showing a configuration of a conventional field emission electron source device.

[Explanation of symbols]

1 p-type silicon substrate 2 first n-type semiconductor conductive portion 3 serving as a source region of the FET 3 second high impurity concentration serving as a drain region of the FET
N-type semiconductor conductive part 4 having a low impurity concentration to be a drain region of the third FET
N-type semiconductor conductive part 5 cathode 6 insulating layer 7 lead electrode 8 gate electrode 8T T-shaped gate electrode 9 source electrode 31 p-type silicon substrate 32 first n-type semiconductor conductive part 33 to be a source region of FET 33 drain of FET A second n-type semiconductor conductive part having a high impurity concentration serving as a region 34 a third n-type semiconductor conductive part having a low impurity concentration serving as a drain region of a FET 35 a cathode 36 a lower insulating layer 37 an upper insulating layer 38 a lead electrode 39 a gate electrode Reference Signs List 40 Source electrode 41 P-type silicon substrate 42 First n-type semiconductor conductive portion 43 serving as a source region of FET 43 Second n-type semiconductor conductive portion having a high impurity concentration serving as a drain region of FET 44 Impurity serving as a drain region of FET Low concentration third n-type semiconductor conductive part 45 Cathode 46 Lower insulating layer 47 Upper insulating layer 48 Leader electrode Reference Signs List 49 gate electrode 50 shield electrode 151 source electrode 51 p-type silicon substrate 52 first n-type semiconductor conductive portion 53 serving as a source region of FET 53 second n-type semiconductor conductive portion having a high impurity concentration serving as a drain region of FET 54 cathode 55 first insulating layer 56 second insulating layer 57 gate electrode 58 source electrode 59 lead electrode 61 p-type silicon substrate 62 n-type semiconductor conductive portion serving as FET source region 63 cathode 64 first insulating layer 65 second Insulating layer 66 Gate electrode 67 Source electrode 68 Extraction electrode 71 P-type silicon substrate 72 First n-type semiconductor conductive portion 73 serving as a source region of FET 73 Second n-type semiconductor conductive portion having a high impurity concentration serving as a drain region of FET 74 cathode 75 first insulating layer 76 second insulating layer 77 gate electrode 78 source electrode 79 Outgoing electrode 91 Insulating layer 92 Gate electrode (lead electrode) 93 Insulating layer 94 Second gate electrode (focusing electrode) 95 Emitter 801 P-type silicon substrate 802 First n-type layer serving as FET source 803 Field emission cathode element Conical emitter 804 Insulating layer (SiO ₂ layer) 804 ′ Portion of insulating layer functioning as gate insulating layer of field emission cathode device 805 Gate layer of field emission cathode device 806 Second n-type layer serving as drain of FET 807 Source electrode of FET 808 Gate electrode of FET 809 Anode of field emission cathode device 810 Field effect transistor (FET) 811 Source resistance 812 Gate voltage source (voltage value Vg) 813 Anode voltage source (voltage value Va) 814 Gate-source control voltage Source (voltage value Vgs)

Claims (13)

[Claims] A lead electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region; A field emission electron source including a cathode formed at a position corresponding to the opening; an n-channel field effect transistor formed on the p-type silicon substrate corresponding to the field emission electron; Wherein the field emission electron source section is formed in a drain region of the field effect transistor section, and an electric field from the field emission electron source section is controlled by a control voltage applied to a gate electrode of the field effect transistor section. A field emission type electron source device in which a radiation current is controlled, wherein the drain region includes at least two types of wells having different impurity concentrations, and an impurity among the at least two types of wells. Low concentration well is formed in an end portion of the drain region in contact with the channel region of the field effect transistor unit, the field emission electron source apparatus. 2. The field emission type electron source device according to claim 1, wherein the drain region contains at least two types of n-type impurity elements having different thermal diffusion rates in a silicon substrate as the impurity elements. . 3. The method according to claim 1, wherein the drain region contains, as impurity elements, a phosphorus element having a high thermal diffusion rate in a silicon substrate and an arsenic element having a low thermal diffusion rate in a silicon substrate. The field emission type electron source device according to the above. 4. An extraction electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region, and A field emission electron source including a cathode formed at a position corresponding to the opening; an n-channel field effect transistor formed on the p-type silicon substrate corresponding to the field emission electron; A field emission electron source portion is formed in a drain region of the field effect transistor portion, and an electric field from the field emission electron source portion is controlled by a control voltage applied to a gate electrode of the field effect transistor portion. A field emission type electron source device in which a radiation current is controlled, wherein the gate electrode of the field effect transistor portion has a shape including at least two types of portions having different gate widths. A field emission type electron source device, wherein a part of a gate electrode is arranged to cover an end of the drain region. 5. A lead electrode formed on a p-type silicon substrate with a first insulating film interposed therebetween and having an opening at a position corresponding to a cathode formation region, and A field emission electron source including a cathode formed at a position corresponding to the opening of the extraction electrode; and an n-channel field effect formed on the p-type silicon substrate corresponding to the field emission electron source. A transistor section, wherein the field emission electron source section is formed in a drain region of the field effect transistor section, and the field emission electron source section is controlled by a control voltage applied to a gate electrode of the field effect transistor section. A field emission type electron source device in which a field emission current from the semiconductor device is controlled, wherein a gate insulating film formed between the gate electrode of the field effect transistor and the p-type silicon substrate comprises A field emission type comprising a thinner film than the first insulating film formed between a pole and the p-type silicon substrate, and having a configuration in which the gate insulating film is embedded by the first insulating film; Electron source device. 6. The silicon oxide film formed in a sharpened thermal oxidation process for sharpening the tip of the cathode portion of the field emission electron source portion, wherein the gate insulating film is formed. A field emission type electron source device according to claim 5. 7. A lead electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region, and a lead electrode of the lead electrode on the p-type silicon substrate and A field emission electron source including a cathode formed at a position corresponding to the opening; an n-channel field effect transistor formed on the p-type silicon substrate corresponding to the field emission electron; A field emission electron source portion is formed in a drain region of the field effect transistor portion, and an electric field from the field emission electron source portion is controlled by a control voltage applied to a gate electrode of the field effect transistor portion. A field emission type electron source device in which a radiation current is controlled, comprising: a channel region of the field effect transistor portion, which is formed of the same material as the gate electrode of the field effect transistor portion. 3. The field emission type electron source device according to claim 1, further comprising a shield electrode disposed so as to cover a region not covered by the gate electrode. 8. The semiconductor device according to claim 7, wherein the shield electrode is maintained at the same potential as the p-type silicon substrate, and has a function of blocking an influence of an external electric field not caused by the gate electrode on the channel region. Field emission type electron source device. 9. A lead electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region, and a lead electrode of the lead electrode on the p-type silicon substrate. A field emission electron source including a cathode formed at a position corresponding to the opening; an n-channel field effect transistor formed on the p-type silicon substrate corresponding to the field emission electron; A field emission electron source portion is formed in a drain region of the field effect transistor portion, and an electric field from the field emission electron source portion is controlled by a control voltage applied to a gate electrode of the field effect transistor portion. A field emission type electron source device in which emission current is controlled, wherein the drain region of the field effect transistor portion is surrounded by the source region inside a source region of the field effect transistor portion. A field-emission electron source device, wherein the gate electrode of the field-effect transistor portion has a configuration symmetrical in plan with respect to the cathode portion of the field-emission electron source portion. 10. The field emission electron source device according to claim 9, wherein said drain region is made of a p-type conductive layer. 11. The drain region, wherein an outer peripheral portion of the field effect transistor portion in contact with the channel region and an inner peripheral portion of the source region have a circular shape formed concentrically. Item 10. A field emission type electron source device according to item 9. 12. The field emission electron source device according to claim 9, wherein at least a part of the gate electrode formed between the source region and the drain region has an arc-shaped symmetric shape. . 13. A first voltage Vex applied to the extraction electrode of the field emission electron source unit and a second voltage Vex applied to the gate electrode of the field effect transistor unit.
10. The field emission type electron source device according to claim 9, wherein a relationship of Vg <Vex exists with respect to g.