JP2000194555A - Arithmetic processor and instruction order control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further improve frequency by judging whether or not a fetched instruction or an instruction stored in an instruction storage means can be executed according to information regarding the use states of registers. SOLUTION: For example, when two pipeline units 6-1 and 6-2 are provided, this dynamic VLIW system is provided with independent Pending Queues 2-1 and 2-2 for slots 1 and 2, respectively, so as to save an instruction fetched from a normal instruction sequence as an execution waiting instruction if it can not be executed immediately. Further, out-of-order is realized by using a table called a score board 4 for managing information regarding the use states of the registers for each register. an atom which is not executed among atoms of a fetched VLIW instruction is saved in the Pending Queues 2-1 and 2-2 until its execution becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit capable of processing instructions in parallel and an instruction sequence control method therefor.

[0002]

2. Description of the Related Art There are a VLIW method in which resources are statically allocated and used at compile time and a superscalar method in which resources are dynamically allocated at execution time. In contrast to the VLIW method of performing static scheduling, a method using a superscalar is a method represented by a high-performance RISC processor.

[0003] Originally, RISC processors have been speeded up by achieving a high execution frequency with a simple configuration. However, since higher performance is required, instructions that can be executed simultaneously by hardware are detected, and those are executed. Has been applied to a plurality of arithmetic units and executed in parallel.

In the superscalar system, even if a certain instruction cannot be executed, another executable instruction is dynamically searched for and executed. Therefore, even if a cache miss occurs, the process proceeds without stopping the entire processor. be able to.

[0005] However, such hardware is complicated, and has become a serious obstacle to further improving the frequency.

[0006] The VLIW system is located on the opposite side of these complicated hardware. In the VLIW method, since a compiler detects instructions that can be executed simultaneously, a mechanism for detecting the instructions at the time of execution is not required. Therefore, hardware at the time of execution is simplified, and a high frequency may be achieved.

In the method of detecting instructions that can be executed simultaneously by the compiler, there are parameters that cannot be completely predicted or realistically unpredictable by the compiler, and it is difficult to maintain a high degree of parallelism. An unpredictable parameter is, for example, an increase in load latency due to a cache miss. A method for dealing with these is to separate the load instruction and the instruction using the loaded value as much as possible. It is known that this is very difficult to apply.

[0008]

As described above, the conventional VLIW system simplifies the hardware by detecting simultaneously executable instructions at compile time (not at run time), and therefore, has a higher frequency. Although it is expected to be realized, there are parameters that cannot be predicted at the time of compiling, so that it is difficult to further increase the parallelism at the instruction level.

On the other hand, in the conventional super scalar method, although processing can be performed without stopping the entire processor by searching for and executing an instruction that can be executed at the time of execution, the hardware becomes very complicated, and It is becoming difficult to improve the frequency.

The present invention has been made in view of the above circumstances, and has as its object to provide an arithmetic processing device with further improved frequency and an instruction sequence control method therefor.

[0011]

According to the present invention, there is provided an arithmetic processing unit for temporarily saving an instruction that has been fetched but cannot be executed so that a subsequent instruction can be executed in advance. A storage unit, a storage unit for storing information on the use state of each register, and a determination as to whether or not the fetched instruction or the instruction stored in the instruction storage unit can be executed based on the information stored in the storage unit. And determination means for performing the determination.

Preferably, the judgment means may include means for judging whether an instruction that has been fetched but cannot be executed is saved in the instruction storage means or the fetch is interrupted.

Preferably, the judging means may include means for judging whether or not an instruction stored in the instruction accumulating means is given an opportunity for execution.

Preferably, in order for the determination means to determine that the fetched instruction is to be input to the instruction storage means, at least when the instruction has a register to which the execution result is to be written, the register can be overwritten. Yes,
Further, the condition that the value of the register referred to by the instruction has not been determined yet may be required.

Preferably, the determination means may determine that the fetch should be interrupted when a register to which the execution result of the fetched instruction is to be written cannot be overwritten.

Preferably, a specific command not to be input to the command storage means in any case may be determined in advance.

Preferably, when determining whether or not the instruction stored in the instruction storage unit is executable, the determining unit overwrites the register to which the execution result is to be written for the instruction to be determined. If it is possible and the value of the register referred to by the instruction is determined, it may be determined that the instruction can be executed.

The present invention comprises a plurality of arithmetic processing units for executing a given instruction and a plurality of registers used for executing the instruction, and stores a plurality of instructions previously associated with the arithmetic processing unit. An arithmetic processing unit capable of simultaneously fetching and processing a plurality of instructions in parallel by an arithmetic processing unit corresponding to each of the corresponding instructions, wherein a plurality of simultaneously fetched instructions which cannot be immediately executed are replaced by a subsequent instruction Instruction storage means provided for each arithmetic unit to temporarily save the data so that it can be executed in advance, and for each register, execution is still performed by a preceding instruction that writes to the register. First information indicating whether or not there is an uncompleted instruction; and second information indicating the number of preceding instructions which have not yet been executed by referring to the register. For each of a plurality of instructions fetched at the same time, based on the type of each instruction, the register used by each instruction, and the corresponding first and second information, Alternatively, it is determined whether the instruction is to be input to the instruction storage means or the fetch is interrupted, and if the instruction determined to be executable immediately is a NOP instruction or an instruction corresponding to a NOP instruction, or not determined to be executable immediately. If there is an instruction in the instruction storage means corresponding to the instruction, the instruction in the instruction storage means is determined based on the register used by the instruction and the corresponding first and second information. Determining means for determining whether or not the processing can be executed immediately.

Preferably, when the fetched instruction is input to a corresponding instruction storage means, first information of a register serving as a destination of the instruction is set among information stored in the storage means, In addition, when incrementing the second information of the register serving as the source of the instruction and extracting the fetched instruction from the corresponding instruction storage means, the information stored in the storage means includes a destination of the instruction, First information updating means for resetting first information of a register and decrementing second information of a register serving as the source of the instruction, and when a load instruction being executed causes a fetch miss Among the information stored in the storage means, first information of a register to which data loaded by the instruction is to be written is set. When the execution of the load instruction in which the fetch error has occurred is completed, first information of a register to which data loaded by the instruction is to be written is reset among information stored in the storage means. Means may be further provided.

Preferably, for each stored instruction, the instruction storage means, when the register serving as the destination of the instruction and the register serving as the first source are the same register, indicating that the register is the same. In the case where the register serving as the destination of the instruction and the register serving as the second source are the same register, a second tag indicating that fact is stored, and the fetched instruction is stored in the corresponding instruction. When inputting to the storage means, the first or second tag is set when applicable, and when the fetched instruction is retrieved from the corresponding instruction storage means, the first or second tag is applied when applicable. Reset tag, 3rd
May be further provided.

Preferably, when determining whether or not the instruction of the instruction storage means can be executed, the determining means determines whether or not the first tag of the instruction is set, and stores the information stored in the storage means. Wherein the first information of a register serving as a second source of the instruction is reset, and
If the second information of the register serving as the destination of the instruction is 0, it is determined that the instruction can be executed;
If the second tag of the instruction is set,
Among the information stored in the storage means, the first information of a register serving as a first source of the instruction is reset, and the second information of a register serving as a destination of the instruction is If it is 0, it may be determined that it can be executed.

Preferably, when determining whether or not the fetched instruction can be executed, the determination unit may determine whether the first information of a register serving as a destination of the fetched instruction is included in the information stored in the storage unit. When set and / or when the second information of the register is not 0, it may be determined that the fetch is interrupted.

Preferably, when determining whether or not the fetched instruction can be executed, the determination means does not cause interruption of the fetch and, among the information stored in the storage means,
When the first information of the register serving as the source of the fetched instruction is set, it may be determined that the instruction should be input to the instruction storage means.

Preferably, when the fetched instruction corresponds to a load instruction, a store instruction or a conditional branch instruction, the determination means determines that the instruction is not input to the instruction storage means in any case. You may do so.

Preferably, when the condition prediction of the currently executed conditional branch instruction fails, the instruction fetched and being executed based on the failed condition prediction and the instruction stored in the instruction storage means. Means for canceling the command may be further provided.

Preferably, the instruction storage means is a FIFO
You may make it comprise a buffer.

Preferably, the instruction is executed by pipeline processing, the determination of the execution is performed in a decode stage (D stage), and the update of the information is performed in a decode stage and a memory stage (M stage). Is also good.

According to the instruction order control method of the present invention, an instruction is fetched to determine whether or not it can be executed. If it is determined that the fetched instruction cannot be executed, the fetch is not interrupted. When it is determined that the instruction is to be stored in the temporary storage unit, and when it is determined that the fetched instruction is to be stored in the instruction storage unit, whether the other instruction stored in the instruction storage unit is executed first is determined. And if it is determined that the other instruction can be executed, it is determined that the instruction is to be executed.

According to the present invention, there are provided a plurality of arithmetic processing units for executing a given instruction, a plurality of registers used for executing the instruction, storage means for storing information on the use status of each register, and fetching. Instruction storage means provided corresponding to each operation unit for saving the instruction in order to enable the preceding execution of a subsequent instruction when the instruction cannot be immediately executed. Fetch multiple instructions associated with at the same time,
An instruction sequence control method for an arithmetic processing unit that processes a plurality of instructions while changing the order of instructions using the instruction storage unit, wherein the plurality of instructions are fetched simultaneously and stored in the storage unit. Based on the received information, for each arithmetic unit, execute the fetched instruction, execute the instruction stored in the instruction storage means,
Determining whether to execute the instruction, determining whether to store the instruction in the instruction storage means when not executing the fetched instruction, and executing the instruction stored in the instruction storage means; or When at least one of storing the fetched instruction in the instruction storage means is determined, the information stored in the storage means is updated, the instruction is fetched from the instruction storage means, and the instruction storage means is stored. Execute the applicable one of the accumulation of instructions into the
Executing the determined command.

It should be noted that the present invention relating to the apparatus is also established as an invention relating to a method, and the present invention relating to a method is also established as an invention relating to an apparatus.

In the present invention, when the preceding instruction cannot be executed immediately, it is temporarily saved, and the subsequent instruction can be executed first, so that the processing can be speeded up.

Further, since the hardware can have a simple configuration, it is possible to expect an effective increase in speed.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

The system shown in this embodiment is located between the super scalar system and the VLIW system, and is called the dynamic VLIW system. The dynamic VLIW method according to the present embodiment basically includes a VLI
Even though the W method is used, a part of the processing is dynamically executed, so that it is possible to dynamically operate to a certain degree even with respect to items that are difficult to predict at the time of the compiler, so that the processing can be performed without stopping the entire processor. In other words, the dynamic VLIW method seeks a new optimum point of hardware and software (compiler) and aims at optimizing performance.

Regarding the hardware complexity in the dynamic VLIW system, since the reorder buffer and the instruction issue portion which have a particularly large impact on the cycle time are omitted from the super scalar system, the hardware is relatively simple. Simple hardware,
Effective speeding up of program execution can be expected.

Hereinafter, the dynamic VLIW of this embodiment will be described.
The method will be described in detail.

First, the dynamic VL according to the present embodiment
An outline of the IW method will be described with reference to FIGS.

In the following, for the sake of simplicity, the individual instructions making up one VLIW instruction are represented by an atom,
A simultaneously fetched unit composed of a plurality of atoms is referred to as a VLIW instruction. The position where each atom constituting the VLIW instruction should enter is called a slot. The actual program has multiple VLIs
It consists of a sequence of W instructions.

FIG. 1 shows an example of one VLIW instruction. This is an example in which one VLIW instruction is composed of three atoms.

In the dynamic VLIW system, registers are not assigned a renaming structure, and are assigned by a compiler. Eliminating register renaming can simplify the hardware. Note that for this,
As a compiler that generates a VLIW instruction sequence, a compiler that allocates registers so that false dependency does not occur is used (a known compiler may be used).

The instruction issuance is the same as that of the conventional VLIW, and a plurality of instructions assigned by the compiler are executed at the same time. However, the difference from the conventional VLIW is that some of the instructions of the VLIW are different. Is not executed (in this case, the fetch is interrupted in the conventional VLIW; that is, out-of-order is not performed).

FIG. 2 shows the dynamic VLI of this embodiment.
FIG. 2 shows a conceptual diagram illustrating the W method. FIG. 2 shows an example in which two pipeline units (6-1 and 6-2) are provided.

In the dynamic VLIW system, generally, when an instruction fetched from a normal instruction sequence cannot be immediately executed, a pending queue (Pending Queue) for saving the instruction as an execution wait.
ue) independently provided for each slot (2-1 and 2-2 in FIG. 2), and a scoreboard (4 in FIG. 2) for managing information on the use status of each register for each register. Out-of-order is realized using a table called ")."

An atom that is not executed among a plurality of atoms of the fetched VLIW instruction is P until the execution becomes executable.
It is stored in the ending Queue. This Pend
The ing Queue is preferably constituted by a FIFO (first-in first-out buffer).

If the Pending Queue is configured with a FIFO, it is executed in order from the first atom stored in the Pending Queue, which is different from the conventional superscalar reorder buffer. In other words, the executable atom is Pendin
In exchange for the performance constraint that there may be cases where execution cannot be performed even though g Queue exists, hardware is greatly simplified to achieve high speed.

Further, the Pending Queue is:
It is preferably provided for each slot in which an individual atom constituting the VLIW instruction is to be inserted. For example, when the format of the VLIW instruction illustrated in FIG. 2 is used, since there are two slots, two Pending Queues are prepared. An atom that is not executed among the fetched VLIW instructions is the Pe corresponding to the slot.
Input to ndingQueue. As described above, the Pending Queue exists for each slot, and the fact that the slot does not span between slots is one of the restrictions that are made to simplify the hardware and increase the speed.

In each cycle / slot, an atom giving an opportunity for execution may be an atom fetched from a normal instruction sequence, or an atom from a Pending Queue when the Pending Queue is not empty. (1) Atom fetched, (2) Pe
Execution takes precedence in the order of the atoms of the nding Queue.

That is, each Pending Queue
Is the VL fetched from the normal instruction sequence.
If the atom in the slot corresponding to the IW instruction cannot be executed (including a fetch cache miss, interruption of fetch), or if the fetched atom is a NOP
If the atom is an atom, it can be executed if the atom of the Pending Queue is executable (in this case, if the atom of the Pending Queue is not executable, the slot becomes an empty slot in the cycle).

The atom given the opportunity to execute, ie, the fetched atom or the Pending in the above case
The determination as to whether the atom at the head of the Queue is executable is made based on the contents of the scoreboard (the usage of registers related to the atom). Basically, the register used by the atom is If the atom cannot be executed, it is determined that the atom cannot be executed (details will be described later, but an atom fetched from a normal instruction sequence and an atom from the Pending Queue have different criteria for determining whether the atom can be executed). Will do).

The scoreboard uses the fetched atom as P
When you put it in the ending queue,
When issuing an atom from g Queue, when a load instruction causes a cache miss, and when the load instruction causing the cache miss is completed, the contents of the corresponding register are updated.

As described above, in the dynamic VLIW method according to the present embodiment, an atom that cannot be executed immediately is temporarily saved in the Pending Queue, and executed once it becomes executable. Has been realized. Also, the determination as to whether or not execution is possible employs a determination based on an original scoreboard.

Even if an atom cannot be executed at the time of fetching, all of the atoms are Pend
Pinging Queue is not considered in the Ping Queue.
There are cases where it is not allowed to enter. That is, Pe
The nding Queue includes an atom determined to be unexecutable at the time of fetching, and a Pending Que.
Insert an atom that satisfies the conditions for eue. Note that these conditions will be described later in detail.

If an atom determined to be unexecutable at the time of fetch cannot be put in the Pending Queue, the fetch is suspended until the atom becomes executable. When the fetch is interrupted (even if interrupted due to one atom), all atoms of the VLIW instruction are not executed as in the conventional VLIW.

Next, an outline of the dynamic VLIW will be described using a simple example in order to show the effects of the dynamic VLIW.

FIG. 3 shows an example of an instruction sequence when two atoms are included in one VLIW instruction as an example of an instruction sequence to be executed.

In the following, each atom is defined as a mnemonic, a destination (dest) register, a first source (src1) register, and a second source (s
rc2) are described in the order of the registers.

As shown in FIG. 3, this instruction sequence is composed of ADD R8, R9, R10 and LD R5, (R3), LDI R18, 1000 and ADD R13, R9, 4, ADD R21, R18, R9 and SUB. R11, R5, R8, LSR R22, R21, 5 and ORI R24, R21, 0xFF, SUBI R25, R24, 5 and NOP, BRZ R11, R0, ROOP_EXT and NOP are fetched one by one in this order. .

The NOP atom may be an instruction that does not actually cause any operation, or may be an instruction that executes ADD or the like but results in no change.

Hereinafter, the instruction sequence illustrated in FIG.
A description will be given of a comparison between the cases where the IW scheme and the dynamic VLIW scheme are executed.

FIG. 4 shows a case where this instruction sequence is executed by the conventional VLIW system, and FIG. 5 shows a case where this instruction sequence is executed by the dynamic VLIW system.

In the examples of FIGS. 4 and 5, the LD (load instruction) which is the atom of the second slot of the first VLIW instruction is 1
It is assumed that a miss occurs in the next cache and the corresponding data exists in the second cache, so that four cycles are required to load it.

As shown in FIG. 4, when this instruction sequence is executed by the conventional VLIW method, in cycle 1,
ADD R8, R9, R10 in the first slot and LD R5, (R3) in the second slot are executed. However, since the LD in the second slot causes a cache miss, the cycle 2 is executed.
In the four cycles of (1) to (5), both the first and second slots are stalled due to an LD miss (the fetch is interrupted during this period). Thereafter, the instructions are sequentially executed. ing.

Next, as shown in FIG. 5, when this instruction sequence is executed by the dynamic VLIW method, first, in cycle 1, ADD R8, R
9, R10 and LD R5, (R3) in the second slot are executed, and the LD causes a cache miss. From the next cycle, an atom using the destination register R5 of this LD cannot be executed until the LD is completed (the status of this register R5 is reflected on the scoreboard).

In cycle 2, since each atom of the VLIW instruction does not use R5, which is the destination register of LD, LDI R18,1000 and ADDI
R13, R9, and 4 are executed.

In cycle 3, ADD of the first slot
R21, R18, and R9 are executed because R5 is not used, but SUB R11, R5, and R8 in the second slot are
Since R5 is referred to as the first source register, it cannot be executed and is input to the Pending Queue. (It can be seen that R5 cannot be used by referring to the scoreboard, indicating that it cannot be executed.)
From the next cycle, an atom using the destination register R11 of SUB (this S
(Excluding UB) cannot be executed until this SUB is completed (the status of this register R11 is also reflected on the scoreboard).

In cycle 4, since neither R5 nor R11 is used, LSR R22, R21, 5 and ORI R2
4, R21, 0xFF is executed.

In cycle 5, since neither R5 nor R11 is used, NOBI is executed with SUBI R25, R24, and 5.

Here, the LD is completed, and from the next cycle, R5 becomes available (the status of this register R5 is also reflected on the scoreboard).

In cycle 6, first, B in the first slot
RZ R11, R0, and ROOP_EX cannot be executed because R11 is the destination. As will be described in detail later, if a register to be used as a destination cannot be used, Pendin
g Do not put in Queue, but wait for execution (suspend fetch). Therefore, this cycle
It becomes an empty slot. Since the fetch is interrupted, the execution of the fetched instruction in the second slot is also suspended.

Here, in the second slot, since the interruption of the fetch has occurred, the atom in the Pending Queue is given an opportunity to execute. Pending Qu
SUB R11, R5, R8 in eue is the LD
Is completed and R5 is available, so it is executable (it can be seen by referring to the scoreboard), and therefore SUB R11, R5
R8 is retrieved from the Pending Queue and executed.

Here, the SUB is completed, and R11 becomes usable from the next cycle (the status of the register R11 is also reflected on the scoreboard).

In cycle 7, BRZ R11, R0, ROOP_EXT waiting for execution in the first slot are
Executable and executed, and in the second slot, the NOP waiting for execution is executed.

As a result, the process is completed in seven cycles.

As described above, in the conventional VLIW system, 1
Although it takes 0 cycles, in the dynamic VLIW method, the execution can be completed in 7 cycles and the speed can be increased by the out-of-order function that another atom can execute during a miss due to the LD atom.

Hereinafter, the present embodiment will be described in more detail.

FIG. 6 shows that in each cycle / each slot, an atom from a normal instruction sequence is executed or Pend
An example of a general procedure for determining whether to execute an atom of ing Queue or not to execute any of them will be described.

First, one VLIW instruction is fetched from a normal instruction sequence (step S1). However, while the fetch is suspended, the fetch in step S1 is not performed.

Next, if an instruction fetch miss occurs, if the fetched atom itself cannot be executed (regardless of whether or not it can be put into the Pending Queue), if the fetch is interrupted (the same VLIW instruction Cannot execute even one of the atoms in this slot and other slots, and Pen
If none of the conditions are satisfied in the ding Queue), if the fetched instruction is a NOP atom, or if none of the conditions is satisfied (steps S2 to S5).
Execute the atom of the slot (step S
6).

If any of the above conditions is satisfied (steps S2 to S5), the Pe of the slot is
If the atom of the nding Queue can be executed (step S7), the atom of the Pending Queue is executed (step S8).

In other cases, if the fetched atom is a NOP atom, this may be executed, and if not, an empty slot (or NOP is executed) (step S9).

FIG. 7 shows a configuration example of the Pending Queue.

The Pending Queue is a FIFO
Where each element consists of a tag and an atom field.

The atom field is a field for storing the atom itself.

The tag field is the two sr
Bit 0 and Bit 1 provided corresponding to c, respectively, and each bit of Bit 0 and Bit 1 contains 1-bit information. The use of this tag will be explained in the following scoreboard description.

FIG. 8 shows a configuration example of the scoreboard. In this example, there are 32 registers R0 to R31.

The scoreboard stores a set of bits (P bits and Pending Count) provided for each register and indicating the state of each register.
As will be described in detail later, whether or not the atom is executable is determined based on the content of the scoreboard.

The rule underlying the scoreboard is that an operation cannot be performed using a register whose value is not prepared as a source. Here, the value is not prepared,
The starting point is when the result of the load instruction is not written in the register, that is, when the load has a cache miss.

The major things that cannot be predicted by the compiler are the results of cache misses and branches. In the dynamic VLIW method, measures are taken against cache misses.

The feasibility of the fetched atom is determined by the scoreboard, and if it is determined that the fetched atom is feasible,
When the execution of the atom becomes impossible, the following 2
There are different types of processing. (I) Load the atom on the Pending Queue. However, if the fetch is interrupted due to an atom in another slot, the atom cannot be loaded on the Pending Queue.

(Ii) Suspend the new fetch until the atom becomes executable. This is an operation corresponding to the stall of the conventional processor. However, in this embodiment, even if a new fetch is interrupted, the Pending Queue
Atom from is executable.

The scoreboard from which the execution of such an atom is determined is updated according to the following rules. (I) When a load instruction is missed, the P bit is set (set) in the dest (destination) register. (Ii) If the P bit is set in the register of at least one src (source) of the atom determined to be unexecutable and does not match the following case (iii), de
Set the P bit in the register of st
Put this atom in the Queue (unless the new fetch should be interrupted). (Iii) When dest matches one of the srcs of the atom determined to be unexecutable, and the P bit of the register of the matching src is 0 and the P bit of the register of the src that does not match is 1 Sets the P bit in the register of dest, and puts this atom in the Pending Queue (unless the new fetch should be interrupted).

In the case of (iii), Pen
The following is recorded in the field of the ding Queue tag. If src1 matches dest, Bit0 is set. • If src2 matches dest, set Bit1.

The P bit of the register and the tag of the atom set as described above indicate that the corresponding atom is Pend.
Reset when fetched from ing Queue. Also, when the load instruction causing the miss is completed, the P bit of the corresponding register is reset.

In the above case (iii),
The processing related to the tag is, for example, add R2, R2, R
It is necessary for the Pending Queue to correctly issue an instruction in which the register serving as the src matches the register serving as the dest as shown in FIG.

For example, in the case of add R2, R2, and R3, by setting the P bit of R2 as dest, the P bit of R2 as src1 is also set. The atom becomes unexecutable until the P bit of R2 is cleared, and the P bit of R2 is not cleared no matter how long it waits.
(cleared when fetched from the Ding Queue), and will continue to stay in the Pending Queue, so referring to the tag, the P bit of R2 as src was set by another atom or set by itself. It is necessary to distinguish between the two.

Next, in the scoreboard, in addition to the P bit, there is a counter which indicates how many instructions refer to this register in the Pending Queue. They are updated with the following update rules: (I) When an atom enters the Pending Queue, the counter of the register that becomes src is incremented. (Ii) When an atom comes out of the Pending Queue, the counter of the register which becomes src is decremented.

This counter is used for Pending Cou.
It is called nt (P count) and exists for each register, and has information for protecting the source of an atom under pending from being overwritten.

Here, when an atom is placed on the Pending Queue, the scoreboard and the Pending Queue are used.
The operation to be performed on each piece of eue information is summarized as follows. -The P bit of the corresponding dest is set. -The P count of the corresponding src is incremented. -Bit0 or Bit1 is set according to the conditions.

In addition, the operations to be performed on the Pending Queue and the information of the scoreboard when issuing an atom from the Pending Queue are summarized as follows. -The P bit of the corresponding dest is reset. -The P count of the corresponding src is decremented. • Bit0 or Bit1 that has been set is reset.

In one cycle, the fetched instruction is put in the Pending Queue, and the
When the instruction from the ding Queue is to be executed, first, the scoreboard and the tag are updated for the instruction extracted from the Pending Queue, and the scoreboard and the tag are updated for the fetched instruction. (So that the later instruction does not affect the execution of the earlier instruction).

Next, the determination of the feasibility will be described.

First, the determination of the executability of the fetched VLIW instruction atom will be described.

The executability of the fetched atom is
Based on the scoreboard, it is determined whether some conditions are met or not. If it is determined that execution is not possible, Pe
One of two types of processing is performed: the processing is put into the nding Queue, or the fetch of a new instruction is interrupted (stopped). Otherwise, it becomes executable.

When the condition for interrupting the fetch is satisfied, the interruption of the fetch occurs preferentially, and when the interruption of the fetch is not interrupted, the Pending Queue is interrupted for the first time.
e.

FIG. 9 shows an example of a procedure for determining the executability of the fetched atom in each cycle / each slot.

First, when any of the following conditions is satisfied (steps S11 to S15), it is determined that the atom cannot be executed, and interruption of the fetch is determined (step S19).

(I) In the scoreboard, the P bit is set in the register that is the dest of the fetched atom. In this case, when the atom is executed, Pendin
Since writing into a register prior to an atom included in g Queue destroys the dependency, the atom cannot be executed, and therefore no new instruction is fetched.

(Ii) The fetched atom is an LD instruction (load instruction) or ST instruction (store instruction), and the P bit is set in the src register which is the address of the LD atom or ST atom in the scoreboard. Yes In this case, do not include in the Pending Queue.
Do not fetch new instructions. (Iii) The fetched atom is a branch instruction, and the P bit is set in a register that becomes a condition of the branch atom in the scoreboard. In this case, the Pending Queue is not included in the Pending Queue.
Do not fetch new instructions.

In this case, however, the Pending Q
uee, a new instruction is fetched, and the execution proceeds speculatively. (Iv) In the scoreboard, d of the fetched atom
The P count of the register to be est is not 0 (1 or more). In this case, since the atom that is trying to read this register is pending, it cannot be overwritten, so that no new instruction is fetched.

(V) Interruption of fetch is determined by an atom of another slot fetched at the same time. Next, if none of the above conditions is satisfied (steps S11 to S15), the atom is It is determined whether it can be executed or put in the Pending Queue.

That is, when the following condition is satisfied (step S16), it is determined that the atom cannot be executed, and it is determined that the atom is to be put in the Pending Queue (step S18).

(Vi) In the scoreboard, at least one P bit among the P bits of the src register of the fetched atom is set. Only when the condition is not satisfied in step S16, the atom is It is determined that execution is possible (step S17).

If the atom determined to be executable (without fetch interruption) is other than the NOP atom,
The atom is executed. If the atom is a NOP atom, the atom of the Pending Queue is given an opportunity to execute.

Next, the possibility of executing an atom from the Pending Queue will be described.

The feasibility of the atom from the Pending Queue is determined based on a scoreboard based on whether or not some conditions are satisfied. It is determined).

FIG. 10 shows an example of a procedure for judging the feasibility of an atom from a pending queue in each cycle / each slot.

First, when the instruction cache is missed, when the fetched atom itself cannot be executed according to the above conditions (i) to (iv) and (vi), the interruption of the fetch in (v) is stopped. In this case (if the atom in another slot cannot be executed according to the above conditions (i) to (iv) and (vi)), the fetched atom is NOP
Instruction (if fetch is not interrupted) or any of the conditions is satisfied (step S
21), the atom of the Pending Queue
An opportunity for execution is given (see FIG. 6).

At this time, the feasibility of the atom from the Pending Queue is determined under the following conditions.

Note that the Pending Queue is set to FI
With the FO configuration, it is only necessary to determine the feasibility of only the first atom of the Pending Queue.

(I) When the P bits of all the src registers of the atom to be determined are reset and the P count of the dest register is 0 (step S22), , The atom is executable (step S26).

(Ii) If a bit is set in the field Bit0 of the tag of the Pending Queue, the P bit of the register src2 of the atom is not set in the scoreboard, and
If the P count of the dest register is 1 (step S23), the atom becomes executable (step S26). (Iii) If a bit is set in the field Bit1 of the Pending Queue tag, the P bit of the register that is src1 of the atom is not set and the P bit of the register that is dest is set in the scoreboard. If the count is 1 (step S24), the atom becomes executable (step S2).
6).

In the above (ii) and (iii), the condition that the P count is 1 instead of 0 as the judgment condition is that execution is possible when a bit is set in the field of the corresponding tag. This is because the case where the src of the atom matches the dest is shown.

(Iii) In other cases, the atom cannot be executed (step S25).

Hereinafter, how the scoreboard and the Pending Queue tag mechanisms set as described above work will be described with reference to some examples. For simplicity of description, FIG. 11 shows only atoms having dependencies. In addition, the dependency may naturally extend over the slots (for example, the result of the FP operation is used in the INT), but the description of the relationship of the slots is omitted (for the sake of explanation,
Other slots do not affect the content of the scoreboard,
The fetch was not interrupted.)

(I) First, using the example of FIG.
Since the register P bit which is the src of the fetched atom is set, the atom is
The case of entering eue will be described.

In this example, in a certain slot, LD
R8, (R5) is executed, and the next ADD R10, R8,
R9 is executed.

FIG. 12 shows the scoreboard and Pe in this case.
The transition of the content of the nding Queue is shown.

In FIG. 12, the scoreboard and the Pendin
The description of 0 is omitted in the tag of g Queue. In the P bit and the Queue tag, 1 indicates a set state, and 0 indicates a reset state. This is the same in FIGS. 13 and 14 which will be referred to later.

In the initial state, the state of the scoreboard is as shown in FIG. 12A, and the state of the Pending Queue is as shown in FIG. 12B.

First, LD R8, (R5) is fetched and is executed because it is determined that the execution is possible with reference to the scoreboard.

Here, assuming that a cache miss has occurred, as shown in FIG.
The P bit of the register R8 to be st is set. P
The ending queue does not change as shown in FIG.

Next, ADD R10, R8, and R9 are fetched. Referring to the scoreboard, since the P bit of R8 serving as src is set, this atom is input to the Pending Queue. (FIG. 12 (f)) As a result, the P bit of the register R10 which is the dest of the atom is set, and the P count of the registers R8 and R9 which become the src (Pending)
u Count) is incremented to 1 (FIG. 12E).

As described above, an atom attempting to use a register that does not contain a value is placed in the Pending Queue.

When the LD instruction is completed, the scoreboard and the Pending Queue are changed to the state shown in FIG.
And (h), and ADD R10, R8, R9 becomes executable. And ADD R10, R8, R9
Is retrieved from the Pending Queue, the scoreboard and the Pending Queue are shown in FIG.
Return to the state of (a) and (b) (provided that there is no other change in the scoreboard and the Pending Queue).

(Ii) Next, using the example of FIG.
The case where the P bit is set to dest and the fetch of a new instruction is stopped will be described.

In this example, SUB R10, R2, and R3 are executed following the two atoms in FIG.

Scoreboard and Pending Queu
The initial state of e is as shown in FIGS.
Assuming that DR R8, (R5) has caused a cache miss, ADD R10, R8, R9 is
Scoreboard and Pendi when it is put into ueue
The initial state of the ng Queue is as shown in FIGS.

Next, SUB R10, R2, and R3 are fetched. When the scoreboard is referred to, the P bit of dest R10 is set. Here, if SUB R10, R2, R3 is executed, the register R10 will be overwritten before it is written yet by ADDR10, R8, R9. Therefore, the fetch is interrupted (score board and Pending Qu
eue does not change).

As described above, an atom to be used as a dest in a register in which the P bit is set is not included in the Pending Queue, and a new fetch is stopped.

It should be noted that the LD instruction is completed and ADD R1
When 0, R8 and R9 are taken out of the Pending Queue, the scoreboard and the Pending Queue
Returns to the state shown in FIGS. 12A and 12B, so that SUB R10, R2, and R3 can be executed at this time.

(Iii) Next, using the example of FIG. 11C, the Pending Cou of the register to be the dest
A case where the fetch of a new instruction is stopped because nt is not 0 will be described.

In this example, SUB R8, R7, and R6 are executed following the two atoms in FIG.

Scoreboard and Pending Queu
The initial state of e is as shown in FIGS.
Assuming that DR R8, (R5) has caused a cache miss, ADD R10, R8, R9 is
Scoreboard and Pendi when it is put into ueue
The initial state of the ng Queue is as shown in FIGS.

Next, SUBs R8, R7, and R6 are fetched. When the scoreboard is referred to, the P count of the dest R8 is not 0. Here, if SUBR
When 8, R7 and R6 are executed, register R8 is still AD
This would be updated before being referenced by DR10, R8, R9. Therefore, the fetch is interrupted (the contents of the scoreboard and the Pending Queue do not change).

As described above, for an atom that attempts to use a register whose P count is not 0 as dest, P
Stop new fetch without entering ending Queue.

It should be noted that the LD instruction is completed and ADD R1
When 0, R8 and R9 are taken out of the Pending Queue, the scoreboard and the Pending Queue
Returns to the state shown in FIGS. 12A and 12B, so that SUB R8, R7, and R6 can be executed at this time.

(Iv) Next, using the example of FIG.
The case where the tag of the Pending Queue is set will be described.

In this example, in a certain slot, LD
R8, (R5) are executed, and the next ADD R6, R6, R
8 is executed.

FIG. 13 shows the scoreboard and Pe in this case.
The transition of the content of the nding Queue is shown.

In the initial state, the state of the scoreboard is as shown in FIG. 13A, and the state of the Pending Queue is as shown in FIG. 13B.

First, LD R8, (R5) is fetched, and is executed because it is determined that it is executable by referring to the scoreboard.

Here, assuming that a cache miss has occurred during the execution of the LD atom, as shown in FIG. 13C, the P
Bit is set. The Pending Queue does not change as shown in FIG.

Next, ADD R6, R6, and R8 are fetched. Referring to the scoreboard, since the P bit of R8, which is src2, is set, this atom is input to the Pending Queue. Then, since the atom's dest and src1 match, 1 is set to Bit0 (FIG. 13 (f)). Also, the P bit of the register R6, which is the dest of the atom, is set, and the P count of the registers R6, R8, which are the src, is incremented to 1 (FIG. 13 (e)).

Since ADD R6, R6, and R8 are waiting for R8 to become valid, they can be executed even if the P bit of register R6 (set for itself) is 1. In this case, since Bit0 is 1, src2
Becomes executable when the P bit of R8 becomes 0.

When the LD instruction is completed, the scoreboard and the Pending Queue are as shown in FIGS. 13 (g) and 13 (h), and ADD R10, R8, R9 can be executed. When the ADD R10, R8, and R9 are extracted from the Pending Queue, the scoreboard and the Pending Queue are displayed as shown in FIG.
It returns to the state of (a) and (b).

FIG. 14 shows the scoreboard and Pendi when the present configuration example and the procedure example are applied to the example of FIG.
The transition of the content of ng Queue will be shown. (A) and (b) are initial states, (c) and (d) are LDs in cycle 1
Are the states when an error occurred, and (e) and (f) are cycle 3 and SUB R11, R5, and R8 are pending.
State when put in Queue, (g) and (h)
Is the state when the LD is completed in cycle 5 (here, SU
B R11, R5, and R8 become executable). In cycle 6, SUB R11, R5, R8
Is extracted from the Pending Queue, and the state at that time is as shown in (a) and (b).

Next, an instruction that is not included in the Pending Queue will be described.

As mentioned earlier, some instructions will suspend new fetches without entering the PendingQueue when they are not executable. Although the outline of the processing has been described in the description of the feasibility, those atoms will be described in more detail here.

First, if the P bit is set in the register indicating the LD and ST addresses, or
When the P bit is set in the register indicating the data of T, the P bit is not included in the Pending Queue.
This is for maintaining the order relation of. For example, if ST is Pe
The LD is executed while in the nding Queue,
If this is the same address as the ST in the Pending Queue, it is impossible to establish a correct relationship. Similarly, if the LD is pending queuing
e, while the next ST is executed and the address is the same, the LD coming out of the Pending Queue
Will read a value different from the original.

When a trap occurs, the LD,
If the ST is in the Pending Queue, a complicated mechanism is required to re-execute it.
D and ST do not accumulate in the Pending Queue.

Other causes of the trap include arithmetic operation instructions. When a trap such as an overflow occurs, the execution of the process is generally terminated and re-execution is not performed. The operation instruction is loaded on the Pending Queue.

Instructions that do not accumulate on the Pending Queue include instructions requiring a plurality of instruction cycles in the Execute, for example, DIV (division).
There are instructions. If the Execute requires a plurality of cycles, if the Pending Queue is loaded, the issuing of the atom from the fetch side must be stopped for a plurality of cycles when exiting the Pending Queue again. To achieve this, the mechanism becomes complicated. Therefore, an atom that requires a plurality of cycles for Execute is stopped from fetching a new instruction without being stacked in the Pending Queue.

However, an instruction requiring a plurality of cycles in Execute is also put in PendingQueue, and Pe
When running out of the nding Queue,
Another method is to stall the execution of other pipes.

Pending Queue with conditional branch
e is not performed because the hardware becomes complicated. When the conditional branch is put in the Pending Queue, the instructions after the conditional branch are speculatively executed regardless of the result of the conditional branch.
This is because if the speculation is wrong, it is necessary to cancel the result, and it is considered that the cost of hardware such as a shadow register often increases. However, if there is a performance improvement corresponding to the increase in hardware cost, the conditional branch is set to Pending Queue.
It is also possible to put it in a box.

Hereinafter, an example of the configuration of a processor to which the dynamic VLIW method is applied will be described.

FIG. 15 shows a schematic configuration example of a processor.

In this example, one pipe (16-1) for FP (floating point operation) and two pipes (16-2, 16-3) for INT (integer operation) are used, for a total of three pipes. It is an example of a processor that has a

As described above, the dynamic VLIW system is based on the conventional VLIW system.
The position of the pipe to be inserted is determined by the position (slot) of each atom constituting the LIW instruction. In the case of the example of FIG. 15, each of the VLIW instructions starts with F
P, INT0 and INT1 are put into the pipes.

Pending Queue (12-1 to 12-1)
12-3) is provided for each pipe. For example, the atom of the slot corresponding to the FP is always Pe of the FP.
It will be input to the nding Queue (12-1).

As described above, the pipe and the Pending Qu
The hardware is simplified by fixing the relation of eue.

The Pending Queue is a FIFO
And when a Pending atom is issued, the Pending Qu
When it is loaded to eue, it is loaded at the end.

When any of the Pending Queues is full, a new fetch is not performed to prevent the Pending Queues from overflowing. As a result, an atom is issued from the Pending Queue, and the Pending Queue is issued.
The length of ue will decrease.

Next, an example of the configuration of a pipeline in the dynamic VLIW system will be described.

When the pipeline is implemented by the dynamic VLIW system, for example, a five-stage pipeline often used in the conventional RISC, that is, F (Fetch; fetch), D (Decode; decode), E (Exec)
ute; execution), M (Memory; W), W (W
writeback; writeback) stage, R
(Register Read; register read) is added to the FDREMW six-stage pipeline. Of course, the six-stage pipeline is merely an example. For example, even if there are a plurality of stages of F, E, and M, the pipeline can be configured based on the same concept.

FIG. 16 is a schematic block diagram showing a case where such a pipeline configuration is applied to the processor shown in FIG. In the figure, 21 is an instruction cache, 22-1 to 22-3 are Pendin of each slot.
g Queue, 23-1 to 23-3 are selectors for each slot, 24 is a scoreboard, 25-1 is a register file for floating-point arithmetic (Register File)
e) and 25-2 are Register Fis for integer arithmetic.
le, 26-1 are floating point arithmetic units, 26-2,
26-3 is an integer operation unit of each slot, and 27 is a data cache. F, D, R, E, M, W
Indicates the relation with the stage on which the block below operates.

The selectors 23-1 to 23-3 are switches for selecting which one of the fetch side and the pending queue side inputs an atom to the R stage. However, there is a case where neither side is selected, and in this case, the NOP atom is to be input to the R stage.

The register file 25-1 is 2Read /
1 Write, 3 ports, register file 25-2
Has a configuration of a total of 6 ports of 4Read / 2Write.

Although FIG. 16 shows an example in which three pipes are provided, the present invention is of course applicable to a processor having four or more pipes. For example, FIG.
May be provided with another floating-point operation unit sharing the register file 25-1 (in this case, the register file 25-1 is 4Read / 2Wri
te total 6 ports).

In the following, a processing example of each stage of the above pipeline will be described.

First, at the F stage, a VLIW instruction is fetched.

Next, in the D stage, it is determined whether or not the fetched atom is executable with reference to the scoreboard. If the fetched atom is executable (without interruption of the fetch), the fetched atom is sent to the R stage. Pending this atom if not executable (without interruption of fetch)
At the end of the Queue or when the fetch is interrupted and the fetched atom is not executed, P
If the first atom of the endingQueue is executable, this atom is sent to the R stage. If neither the fetched atom nor the head of the Pending Queue is executable, NOP is sent to the R stage.

At this stage, the scoreboard and Pe
The nding Queue is updated.

At the R stage, the atom sent from the D stage reads RegisterFile, and the result is sent to the E stage.

In the E stage, an operation is performed on the data sent from the R stage, and the result is sent to the M stage.

In the M stage, data cache access and TLB access are performed when the atom is an atom for performing memory access.

A cache miss is detected at this stage.

In the W stage, the result of the memory access or the operation result passed through the E and M stages is
written to the guest file.

The reason why the determination of the feasibility is made by increasing the number of pipe stages called the D stage is to reduce the number of register ports. This is because increasing the number of ports of the register generally increases the area and often increases the cost.

However, if the number of register ports does not affect the cost, the feasibility is determined in the D stage.
One executable atom is a Register File
Rather than accessing, the D stage and the R stage are combined into one stage, and the fetched atom and Pen
By accessing both the Register File and the scoreboard at the same time for both of the leading atoms of the ding Queue, and changing the executable atoms to be sent to the E stage, the same as in the related art can be achieved.
It can be realized by a pipeline of stages. If the pipeline has five stages, the penalty of the branch is reduced, so that further performance improvement is expected.

Next, the operation at the time of trapping will be described.

A trap is caused by the execution of an atom, and is distinguished from an interrupt because it is generated by interrupting the execution of the atom.

There are traps that can be re-executed and traps that cannot be re-executed. A re-executable trap involves memory access,
There are LB mistakes. Non-reexecutable traps include overflows caused by arithmetic operations.

Since the atom that causes the re-executable trap is an atom that does not accumulate in the Pending Queue as described above, a new VLIW instruction is interrupted when the trap is triggered, and the Pending
If you issue an atom only from Queue, Pendin
When g Queue becomes empty, there are no atoms out of order. Since the trap is caused at the M stage, the atom issued from the fetch side at the same time as the atom causing the trap is canceled before writing the value to the register at the W stage. Also, among the atoms issued from the fetch side at the same time as the atom that caused the trap, those atoms that entered the Pending Queue are canceled. Further, the atom issued from the fetch side at the same time as the atom causing the trap and the atom existing in the pipeline is canceled. The value of PC at this point is stored in a register called EPC. As a result, all atoms issued from the fetch side at the same time as or after the atom that caused the trap are all canceled, and the same atom is not executed twice when re-executed.

Next, the control is transferred to the trap processing routine, the trap processing is performed, and finally the control is transferred to the location indicated by the EPC, whereby the VLIW instruction including the atom causing the trap which was interrupted is re-executed. Will be.

For an atom that cannot be re-executed,
When issued from the nding Queue, it may already be overtaken by another atom. Therefore, when the trap is caused, it cannot be stopped in the same state as that executed in order. That is, since an instruction overtaking an atom that caused a trap cannot be canceled by hardware, there is a possibility that an atom that is executed twice when re-executed from a VLIW instruction that includes the atom that caused a trap may exist. is there.

By the way, in the case of an atom that cannot be re-executed, that is, an overflow of an arithmetic operation atom, the process is generally killed when a trap occurs, so that re-execution is not necessary. No problem.

Since an attempt is made to kill a process, an overflow of an arithmetic operation atom may affect another process from the process in which the overflowing atom originated. For example, it is assumed that an arithmetic operation atom causing an overflow exists in the process PN. This enters PendingQueue for some reason, the next process PM starts up without being issued, and P
If an overflow trap in which the arithmetic operation atom is issued from the Pending Queue during the operation of M occurs, the new process PM is killed.

In order to prevent such an operation, when starting or ending the process, the Pending Query must be executed.
It is necessary to ensure that ue is empty. Generally, starting or terminating a process involves an interrupt operation.
What is necessary is just to have a property of interrupting after the ing Queue becomes empty.

Next, the interrupt processing will be described.

An interrupt process is a process that occurs without execution of a specific atom. In the case of interrupt processing, the problem is that the Pending
The question is when to execute the atom in Queue. If an atom in the Pending Queue is issued in the interrupt processing routine, and an exception processing occurs, the interrupt processing routine becomes complicated. Also, since there are many atoms that may cause exception processing such as overflow of operations, the policy that exception-causing instructions should not be included in the Pending Queue is P
Ending Queue effect will be reduced.

Further, considering the above-described process at the time of starting or terminating the process, it is appropriate to process the interrupt process in the same manner as the trap. For example, Pendin
It is preferable to take a method of causing an interrupt after g Queue is empty.

Next, the execution of the conditional branch atom will be described.

The conditional branch atom is Pending Q
It is an atom that does not accumulate on ueue. If the P bit is set in the condition of the conditional branch, it is not known whether or not the branch will be established. Therefore, the Pending Queue is not loaded and a new fetch is not performed.

In general, in a high-performance processor, when a conditional branch is fetched, the result of the condition operation is predicted by logic for predicting the result. Implements a mechanism to determine When the condition is predicted by this mechanism, the pipeline penalty of the branch is small, and the average branch penalty is small.

When the prediction mechanism of the conditional branch is dynamically applied to the VLIW, the following may be performed.

When the condition prediction is successful, the conventional processing may be performed.

On the other hand, if the condition prediction fails, the satisfaction or failure of the condition is determined in the E stage. Therefore, it is necessary to cancel the fetched atoms from the F stage to the E stage based on the failed prediction. There is. Also, based on failed predictions, Pendi
It is also necessary to cancel atoms stored in ng Queue.

An atom fetched based on a failed prediction needs to be canceled, but Pending
Do not cancel the atom issued from Queue because it must be executed before the conditional branch in program order. In order to distinguish whether the atom is a fetched atom or an atom issued from the Pending Queue, for example, an atom in the pipeline issued from the Pending Queue is tagged with a Q tag. If the prediction of the conditional branch fails, the atom without the Q tag (at the F, D, and R stages) before the E stage in the pipeline is canceled.

On the other hand, based on the failed prediction, Pendi
It is also necessary to cancel atoms stored in ng Queue, which are distinguished, for example, as follows.

If it is found at the E stage that the prediction has failed, the atom supposed to be at the R stage is changed to Pendin
Since the end of g Queue may have been added, it may be necessary to cancel the end of Pending Queue. In order to determine this case, when an atom is stacked on the Pending Queue from the D stage, C
Attach a tag. Atom with C tag is Pend
This indicates that the instruction is loaded on the pipe instead of the instruction loaded on the ing Queue.

When it is found that the prediction has failed at the E stage and the atom at the R stage has a C tag,
If you cancel the end of the ending queue,
It is possible to cancel an atom that has failed to be predicted and has been placed in the Pending Queue.

Here, the processing in the case where the condition prediction has failed will be described with reference to the specific example of FIG.

FIG. 17 shows the state of the pipeline when the BRZ (branch instruction) of the example instruction sequence is predicted to be nottaken and is unexpectedly taken to be taken. In FIG. 17, for simplicity of explanation,
Only one of a plurality of VLIW slots is shown.

FIG. 17A shows an example of an instruction sequence in a certain slot. Atom followed by BRZ, X, Y, and BR
It is assumed that there is Z before Z (the specific contents of each atom of X, Y, and Z are not particularly defined here). (B)
Indicates the state of each stage at a certain timing. (C) is an X at the end of the Pending Queue.
This shows a state where an atom is held.

Now, in the example of FIG. 17, the atom X next to the BRZ atom was not executable, so
ng Queue, instead of Pendin
An atom called Z from g Queue is in the R stage. In this state, if the branch is not predicted, it is necessary to cancel both X and Y from the pipeline.

Since there is an atom with a C tag in the R stage, the atom to come here is Pending Qu.
eue, and Pending Queu
Cancel the end of e. Further, Y cancels from the D stage. On the other hand, since Z has a Q tag even in the R stage, it is known that Z is an atom issued from the Pending Queue, and this is not canceled.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope.

[0218]

According to the present invention, when the preceding instruction cannot be executed immediately, it is temporarily saved and the subsequent instruction can be executed first, so that the processing can be speeded up. .

Further, since the hardware can have a simple configuration, an effective increase in speed can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a VLIW instruction according to an embodiment of the present invention.

FIG. 2 is an exemplary view for explaining a dynamic VLIW method according to the embodiment;

FIG. 3 is a diagram showing an example of an instruction sequence.

FIG. 4 is a diagram for explaining a case where the instruction sequence of FIG. 4 is executed by a conventional VLIW method;

FIG. 5 is an exemplary view for explaining a case where the instruction sequence of FIG. 4 is executed by the dynamic VLIW method according to the embodiment;

FIG. 6 is an exemplary view showing an example of a procedure from fetch to execution according to the embodiment.

FIG. 7 is a diagram illustrating a Pending Queue according to the embodiment;
Figure showing a configuration example of

FIG. 8 is a view showing a configuration example of a scoreboard according to the embodiment;

FIG. 9 is an exemplary flowchart illustrating an example of a procedure for determining the executability of a fetched atom according to the embodiment.

FIG. 10 shows a Pending Queu according to the embodiment.
A flowchart showing an example of a procedure for determining the feasibility of an atom from e.

FIG. 11 is a diagram showing some examples of an instruction sequence.

FIG. 12: Scoreboard and Pending Queue
Diagram showing an example of the transition of the contents of

FIG. 13: Scoreboard and Pending Queue
Figure showing another example of the transition of the contents of

FIG. 14: Scoreboard and Pending Queue
Figure showing still another example of the transition of the contents of

FIG. 15 is a diagram showing a schematic configuration example of a processor according to the embodiment;

FIG. 16 is a diagram showing a schematic configuration example of a processor according to the embodiment;

FIG. 17 is a diagram illustrating execution of a conditional branch atom.

[Explanation of symbols]

2-1, 2-2, 12-1 to 12-3, 22-1 to 22
-3 ... Pending Queue
e) 4, 24 score board 6-1, 6-2 pipeline unit 16-1 to 16-3 pipe 21 instruction cache 23-1 to 23-3 selector 25-1, 25-2 ... Register file (Regist
er File) 26-1 to 26-3: arithmetic unit 27: data cache

Claims (19)

[Claims] An instruction storage means for temporarily saving an instruction that has been fetched but cannot be executed so that a subsequent instruction can be executed in advance, and stores information on the use status of each register. Storage means for determining whether or not the fetched instruction or the instruction stored in the instruction storage means can be executed, based on information stored in the storage means. Arithmetic processing unit. 2. The arithmetic processing according to claim 1, wherein said determining means includes means for determining whether an instruction that has been fetched but cannot be executed is to be saved in said instruction storage means or fetching is interrupted. apparatus. 3. The arithmetic processing according to claim 1, wherein said judging means includes means for judging whether or not an instruction stored in said instruction accumulating means is given an opportunity for execution. apparatus. 4. The method according to claim 1, wherein the determining unit determines that the fetched instruction is to be input to the instruction storing unit. At least when the instruction has a register to which an execution result is to be written, the register can be overwritten. 4. The operation according to claim 1, wherein a condition that a value of a register referred to by the instruction has not been determined has been satisfied. Processing equipment. 5. The method according to claim 1, wherein said determining means determines that the fetch is interrupted when a register to which an execution result of the fetched instruction is to be written cannot be overwritten. An arithmetic processing unit according to any one of the preceding claims. 6. The arithmetic processing apparatus according to claim 1, wherein a specific instruction not to be input to said instruction storage means in any case is determined in advance. 7. The method according to claim 1, wherein the determining means determines whether the instruction stored in the instruction storing means is executable or not, if the instruction to be determined has a register to which the execution result is to be written, the register can be overwritten. 7. The arithmetic processing device according to claim 1, wherein if the value of the register referred to by the instruction is determined, it is determined that the instruction can be executed. 8. A plurality of arithmetic processing units for executing a given instruction and a plurality of registers used for executing the instruction, wherein a plurality of instructions previously associated with the arithmetic processing unit are simultaneously fetched. An arithmetic processing unit capable of processing a plurality of instructions in parallel by an arithmetic processing unit corresponding to each of the corresponding instructions, wherein a plurality of simultaneously fetched instructions which cannot be immediately executed is replaced by a subsequent instruction. An instruction storage means provided for each arithmetic unit for temporarily saving to enable execution, and for each register, completion of execution by a preceding instruction for writing to the register. First information indicating whether or not there is a non-existent instruction, and second information indicating the number of precedent instructions which refer to the register and have not been executed yet. For each of a plurality of instructions fetched at the same time, based on the type of each instruction, the register used by each instruction, and the corresponding first and second information, It is determined whether the instruction is to be input to the storage means or the fetch is interrupted, and the instruction determined to be executable immediately is the NOP instruction or the NOP instruction.
In the case of an instruction corresponding to the instruction, or when it is not determined that the instruction can be executed immediately, if an instruction is present in the instruction storage means corresponding to the instruction, the instruction in the instruction storage means is used by the instruction. An arithmetic processing apparatus comprising: a register; and a determination unit configured to determine whether or not execution is possible immediately based on the corresponding first and second information. 9. When a fetched instruction is input to a corresponding instruction storage means, first information of a register serving as a destination of the instruction among information stored in the storage means is set, and When the second information of the register serving as the source of the instruction is incremented and the fetched instruction is taken out from the corresponding instruction storage means, the information becomes the destination of the instruction among the information stored in the storage means. First information updating means for resetting the first information of the register and decrementing the second information of the register which is the source of the instruction; and when the load instruction being executed causes a fetch miss. ,
From among the information stored in the storage means, the first information of a register to which the data loaded by the instruction is to be written is set. When the execution of the load instruction in which the fetch error has occurred is completed, the first information is stored in the storage means. 9. The arithmetic processing according to claim 8, further comprising: a second information updating unit that resets first information of a register to which the data loaded by the instruction is to be written, among the pieces of information that have been written. apparatus. 10. The instruction storage means according to claim 1, wherein, for each stored instruction, when a register serving as a destination of the instruction and a register serving as a first source are the same register, a first indication indicating this is provided. If the register serving as the destination of the instruction and the register serving as the second source are the same register, a second tag indicating that fact is stored, and the stored instruction corresponding to the fetched instruction is stored. The first or second tag is set when applicable, and the first or second tag is set when the fetched instruction is retrieved from the corresponding instruction storage means. 10. The arithmetic processing device according to claim 9, further comprising a third information updating unit for resetting the information. 11. The method according to claim 1, wherein the determining unit determines whether or not the instruction stored in the instruction storing unit is executable if the first tag of the instruction is set. Wherein the first information of a register serving as a second source of the instruction is reset and the second information of a register serving as a destination of the instruction is 0, and the program can be executed. When the second tag of the instruction is set, the first information of the register serving as the first source of the instruction among the information stored in the storage unit is reset. 11. The arithmetic processing device according to claim 10, wherein if the second information of the register serving as the destination of the instruction is 0, it is determined that the instruction can be executed. 12. The information processing apparatus according to claim 1, wherein when determining whether or not the fetched instruction is executable, the first information of a register serving as a destination of the fetched instruction is set out of information stored in the storage means. 12. The arithmetic processing device according to claim 8, wherein it is determined that fetching is interrupted when the fetch is performed and / or when the second information of the register is not 0. 13. The deciding means does not interrupt the fetching when judging whether or not the fetched instruction can be executed, and becomes a source of the fetched instruction among the information stored in the storage means. 2. The method according to claim 1, wherein when the first information of the register is set, it is determined that the instruction is to be input to the instruction storage unit.
3. The processing device according to 2. 14. When the fetched instruction corresponds to a load instruction, a store instruction or a conditional branch instruction, the determination means determines that the instruction is not input to the instruction storage means in any case. The arithmetic processing device according to any one of claims 8 to 13, wherein: 15. An instruction which is fetched and being executed based on the failed condition prediction when the condition prediction of the currently executed conditional branch instruction fails, and the instruction inputted and stored in the instruction storage means. The arithmetic processing device according to claim 1, further comprising a unit that cancels the operation. 16. An arithmetic processing device according to claim 1, wherein said instruction storage means is constituted by a FIFO buffer. 17. The instruction according to claim 1, wherein said instruction is executed by pipeline processing, said execution is determined in a decode stage, and said information is updated in a decode stage and a memory stage. The arithmetic processing device according to claim 1. 18. An instruction is fetched and its execution is determined. If it is determined that the fetched instruction cannot be executed, if the interruption of the fetch has not occurred, the instruction is stored in the temporary storage means. And if it is determined that the fetched instruction is to be stored in the instruction storage means, it is determined whether or not another instruction stored in the instruction storage means is executable at the earliest. And determining that the instruction is to be executed if it is determined that the instruction can be executed. 19. A plurality of arithmetic processing units for executing a given instruction, a plurality of registers used for executing the instruction, storage means for storing information on the use status of each register, and a fetched instruction Instruction storage means provided corresponding to each arithmetic unit to save the instruction in order to enable the preceding execution of a subsequent instruction when the instruction cannot be immediately executed, and An instruction sequence control method for an arithmetic processing device that fetches a plurality of attached instructions at the same time and processes the plurality of instructions while changing the order of the instructions using the instruction storage means, comprising: Instructions are fetched at the same time, and based on the information stored in the storage unit, the fetched instruction is executed for each arithmetic unit, or the instruction stored in the instruction storage unit is executed. To run, or NO
Determining whether to execute the P instruction, and determining whether to store the instruction in the instruction storage means when the fetched instruction is not to be executed, and executing the instruction stored in the instruction storage means; Alternatively, when it is determined that at least one of storing the fetched instruction in the instruction storage unit is performed, the information stored in the storage unit is updated, the instruction is fetched from the instruction storage unit, and the instruction storage is performed. A method of controlling the order of instructions, wherein the instructions stored in the means are executed, and the determined instructions are executed.