JP2000188702A - Video signal processing circuit for matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To smooth gradation characteristics to improve gradation continuity and to reduce pseudo contour-shaped image quality interference by making plural dither coefficient patterns in which plural dither coefficients are arranged in a matrix shape include positive and negative dither coefficients so as to make the total of dither coefficients zero. SOLUTION: In this video signal processing circuit 100, a dither matrix coefficient generator 11 generates dither patterns (dither coefficient pattern) 1 to m being an n×n dot matrix, a selector 12 selects one of the dither patterns 1 to m, and an addition circuit 13 adds an input video signal to the selected dither pattern to be outputted through a limiter 14. Here, the dither patterns 1 to m are provided with positive dither coefficients and negative dither coefficients so as to make the total of dither coefficients in one dither pattern zero. By doing this, even if a dither coefficient is added to the input video signal, it becomes difficult to be conspicuous as noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit used in a matrix type display device for performing an inverse gamma correction process on an input video signal to return to a linear gradation and display an image. Panel display device (PDP), field emission display device (FED), digital micromirror device (DM
D), electroluminescence display (EL)
The present invention relates to a video signal processing circuit of a matrix type display device capable of improving the gradation characteristics when expressing digitally limited intermediate gradations as in the above.

[0002]

2. Description of the Related Art Among matrix-type display devices for displaying video signals, for example, a PDP that divides one field into a plurality of subfields to display gradations, an FED that displays gradations by PWM modulation, and a DMD. In the display device described above, an image can be expressed only with a digitally limited number of gradations depending on the driving method. In addition, it is necessary to perform inverse gamma correction processing on the video signal to which the gamma characteristic has been applied to return to a linear gradation.

Therefore, in the matrix type display device, when displaying an image with a digitally limited number of tones, the linearity of the tones that is impaired when performing inverse gamma correction to return to linear tones is reduced. In order to achieve smoothness, for example, a multi-gradation process is performed using a dither method.

In the multi-gradation processing by the dither method, a plurality of adjacent pixels (dots) are formed as a set to form a dither matrix, and intermediate gray levels corresponding to the damaged gray levels are individually set in the dither matrix. A general processing method is represented by dither coefficients. For example, if the display device has only 6-bit gradation capability and performs gradation display using the upper 6 bits of 8-bit dot data, a dither matrix of adjacent 2 × 2 dots is formed, and the dither matrix is insufficient in the dither matrix. By superimposing the two-bit noise pattern, a gradation display corresponding to 8 bits is performed by utilizing a visual integration effect.

FIG. 5 shows an example of an overall configuration of a matrix type display device provided with a video signal processing circuit for performing a multi-gradation process using a dither method and an inverse gamma correction circuit. Here, a PDP is used as an example of the matrix display device. In FIG. 5, a video signal is a video signal processing circuit 1
00, the multi-gradation is achieved by the dither method described later in detail, and is input to the inverse gamma correction circuit 200. The inverse gamma correction circuit 200 performs inverse gamma correction on the input video signal and inputs the video signal to the PDP 300. The video signals are R, G, and B signals. Therefore, actually, the video signal processing circuit 100 and the inverse gamma correction circuit 200
G and B signals require three systems.

Here, a general configuration of the video signal processing circuit 100 will be described with reference to FIG. In FIG.
The dither matrix coefficient generator 1 generates a plurality of types (here, m types) of dither coefficient patterns (hereinafter, dither patterns) each of which is a matrix of n × n dots. In addition,
Here, although m is illustrated as 3 or more, m = 2,
That is, two types of dither patterns may be generated. The dither matrix coefficient generator 1 may be constituted by a ROM or may be constituted by software.

[0007] The selector 2 selects one of the m types of dither patterns from the dither matrix coefficient generator 1 and inputs it to the adder 3. For example, a digitally converted video signal is input to the adder 3. The adder 3 adds the input video signal and the dither pattern selected by the selector 2 and inputs the result to the limiter 4. The limiter 4 restricts the bit of the output of the adder 3 and outputs it. Limiter 4
The output video signal is a multi-gradation signal in which the number of gradations is reduced as compared with the original signal, but apparently increased to the same number of gradations as the original signal.

FIG. 7 shows an example of a conventionally used dither pattern. 7 (A) and 7 (B), a, b, c,
The section consisting of four dots indicated by d shows a dither pattern in a matrix of 2 × 2 dots in vertical (row) × horizontal (column). Note that a dot refers to one of the pixels that constitute R, G, and B pixels. This 2 × 2 dot dither pattern is added to the video signal corresponding to the dot data on the panel of the PDP 300 as described later.
For example, the dot data of the odd-numbered rows have dither coefficients a, b,
are added in order from the pixel at the beginning of the row, and the dither coefficients c, d, c, d,... are added to the dot data in the even-numbered rows in order from the pixel at the beginning of the row. More specifically, a, b,
The dither coefficients c and d are added to four adjacent dots of the same color in R, G, and B, respectively.

In the example shown in FIG. 7A, a, b, c, d
A dither pattern with 0, 1, 2, and 3 respectively;
Two types of patterns, i.e., dither patterns in which a, b, c, and d are 3, 2, 1, and 0, are used, and these dither patterns are alternately switched for each field.

In the example shown in FIG. 7B, a, b, c, d
A dither pattern with 0, 1, 2, and 3 respectively;
a, b, c, and d are 2, 0, 3, and 1 respectively, and a, b, c, and d are 3, 2, 1, and 3, respectively.
By using four types of patterns, a dither pattern of 0, and dither patterns of a, b, c, and d of 1, 3, 0, and 2, respectively, these dither patterns are regularly circulated in a field cycle. It is designed to be switched.

FIGS. 8A and 8B show examples of arithmetic processing by the video signal processing circuit 100 shown in FIG. 6 when the dither pattern shown in FIG. 7A is used.
8A and 8B, the input video signal (original signal) is 8 bits, and dot data corresponding to the dither coefficients a, b, c, and d are 9, 17, 3, 5, and 9, respectively. , (A) shows a case where a dither pattern is added, and (B) shows a case where a dither pattern is added.

In FIG. 8A, an adder 3 adds a dither pattern to an 8-bit original signal.
The original signal of 17, 3, 5 becomes data of 9, 18, 5, 8, 8. In this state, the data value exceeds 8 bits, so that the limiter 4 limits the value exceeding the value based on the number of bits of the original signal (so-called overflow), and cuts off the lower 2 bits to 8, 16, 4, 8 6
It is a bit signal. Here, a 6-bit signal is represented by a multiple of four. Therefore, actually, the signal whose lower 2 bits are truncated to 6 bits is 2, 4, 1, 2, or 3.
It is. The 6-bit video signal is a multi-gray-scale signal in which the number of gray levels is increased to 8 bits apparently by adding the dither pattern.

If the PDP 300 has a display capability of 8 bits, it is not necessarily limited to 6 bits. If the limiter 4 restricts only a portion exceeding 8 bits of data, a large number of 10 bits is required. A gradation display can be performed. As described above, when the matrix type display device has only 6-bit gradation capability, multi-gradation display equivalent to 8 bits equivalent to the original signal may be performed by limiting to 6 bits.

In FIG. 8B, an adder 3 adds a dither pattern to an 8-bit original signal,
The original signal of 17, 3, 5 becomes data of 12, 19, 4, and 5. Actually, as it is, the data value is 8
Since the number of bits exceeds the number of bits, the limiter 4 limits the amount (overflow) exceeding the value according to the number of bits of the original signal, and cuts off the lower two bits, thereby reducing the number of bits.
6-bit signal. Here, a 6-bit signal is represented by a multiple of four. Therefore, actually, the signal in which the lower 2 bits are truncated to 6 bits is 3, 4,
1,1. The 6-bit video signal is a multi-gradation signal in which the number of gradations is apparently increased by adding the dither pattern. FIG. 8 (A),
The output video signal shown in (B) is alternately switched for each field.

The same operation is performed in the case of FIG. 7B. In the case of FIG. 7B, the four types of dither patterns are regularly circulated and switched in the field cycle, and thus a more spatially smooth multi-gradation signal is obtained.

Here, the correspondence between the pixel data on the panel of the PDP 300 and the dither coefficient will be described. In FIG. 9, reference numeral 301 denotes a panel of the PDP 300;
Numeral 02 denotes a dot constituting a pixel composed of R, G, and B. As shown in FIG. 9, panel 301 has N rows × M
It is composed of a plurality of dots 302 in a row, and a, b,
The dither coefficients c and d are added corresponding to the dot data applied to each dot 302. Here, for the sake of simplicity, it is shown that the panel 301 is constituted by dots of one color of R, G, and B, but actually, R, G, and B are actually formed.
G and B dots are sequentially arranged in the row direction to form the panel 301.

[0017]

In the matrix type display device described above, the inverse gamma correction circuit 20 is used.
Since the display is returned to a linear gradation by performing the inverse gamma correction processing by 0, the number of gradations at the low luminance level is lost,
Frequently, image quality disturbance due to loss of gradation continuity may be caused. In particular, in the case of the PDP 300, one field is constituted by a plurality of subfields having different weights of the light emission amounts, and gradation is expressed by selecting a plurality of the subfields. Therefore, depending on the selection condition of the subfield, the visual luminance difference with respect to the adjacent gray scale becomes large, and as a result, image quality disturbance of a pseudo contour may occur in a still image and a moving image.

Therefore, in the case of the PDP 300, a multi-gradation process by a dither method is performed to smooth the gradation linearity, and at the same time, to reduce the image disturbance of a pseudo contour. However, in the conventional dither pattern, near a gray scale where the number of subfields to be selected greatly changes, the luminance difference with respect to the adjacent gray scale is further emphasized, and the image quality disturbance of the pseudo contour may be deteriorated. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and it is possible to improve gradation continuity by smoothing gradation characteristics, and to greatly reduce false contour-shaped image disturbance. It is another object of the present invention to provide a video signal processing circuit of a matrix type display device capable of displaying a high quality video without the need to reduce the number of bits.

[0020]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides a dither matrix coefficient generator (11) for generating a plurality of dither coefficient patterns in which a plurality of dither coefficients are arranged in a matrix. ), A selector (12) for selecting one of a plurality of dither coefficient patterns generated by the dither matrix coefficient generator, and an adder () for adding the dither coefficient pattern selected by the selector to an input video signal. 13), the dither coefficient pattern includes both a positive dither coefficient and a negative dither coefficient, and the sum of the dither coefficients is zero. It is another object of the present invention to provide a video signal processing circuit for a matrix type display device.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video signal processing circuit of a matrix type display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a video signal processing circuit of a matrix type display device of the present invention. FIG. 2 is a diagram showing an example of a dither pattern used in a video signal processing circuit of a matrix type display device of the present invention. 3 is a diagram for explaining the arithmetic processing when the dither pattern shown in FIG. 2 is used, and FIG. 4 is a diagram showing another example of the dither pattern used in the video signal processing circuit of the matrix type display device of the present invention. .

The overall configuration of a matrix type display device provided with a video signal processing circuit for performing multi-gradation processing using the dither method and an inverse gamma correction circuit is as described with reference to FIG.
FIG. 5 shows an example of the entire configuration of the matrix type display device, and the present invention is not limited to this configuration. The signal processing using the dither method by the video signal processing circuit 100 and the inverse gamma correction processing by the inverse gamma correction circuit 200 need not be in the order shown in FIG. 5, and the configuration is such that they are performed simultaneously in the same block. Is also good.

The video signal processing circuit 100 according to the present invention has the configuration shown in FIG.
It is configured as shown in FIG. In FIG. 1, the dither matrix coefficient generator 11 generates, as an example, a plurality of types (here, m types) of dither coefficient patterns (hereinafter, dither patterns) which are n × n dot matrices. Here, although m is illustrated as 3 or more, m =
2, ie, two types of dither patterns may be generated. The dither matrix coefficient generator 11
M, or may be configured by software. The present invention is significantly different from the conventional example in the dither pattern generated by the dither matrix coefficient generator 11.

The selector 12 selects one of the m types of dither patterns from the dither matrix coefficient generator 11 and inputs it to the adder 13. For example, a digitally-converted video signal is input to the adder 13.
The input video signal and the dither pattern selected by the selector 12 are added and input to the limiter 14.
The limiter 14 exceeds the value based on the number of bits of the original signal in the output of the adder 13 (so-called overflow,
Underflow) is output. As in the related art, the output bits of the adder 13 (lower bits) may be limited and output according to the gradation capability of the matrix type display device.

FIG. 2 is an example of a dither pattern used in the present invention. In FIGS. 2A and 2B, a, b, c,
The section consisting of four dots indicated by d shows a dither pattern in a matrix of 2 × 2 dots in vertical (row) × horizontal (column). This 2 × 2 dot dither pattern is added to the video signal corresponding to the dot data applied to the dot 302 of the panel 301 in the PDP 300 as described with reference to FIG. For example, dither coefficients a, b, a, b,... Are added in order to the dot data of the odd-numbered rows from the dot at the head of the row, and dither coefficients c, d, c, d,. Are added in order from the dot.

In the example shown in FIG. 2A, a, b, c, d
, And dither patterns with a, b, c and d of 2, -1, 1 and -2, respectively. The pattern is alternately switched, for example, for each field.

In the example shown in FIG. 2B, a, b, c, d
, -2, 1, -1, and 2, respectively, a, b, c, d of -1, -2, 2, 1 and a, b, c, d, respectively 2,
-1, 1, -2 dither patterns and a, b,
Four types of patterns, i.e., dither patterns in which c and d are 1, 2, -2 and -1, respectively, are used, and the dither patterns are switched periodically by, for example, a field cycle.

In the dither pattern used in the present invention, FIG.
Unlike the conventional example shown in FIG. 1, both the positive dither coefficient and the negative dither coefficient are provided so that the sum of the dither coefficients in one dither pattern becomes zero. Further, in this example, as a preferred embodiment, when a matrix composed of an even number of dither coefficients is equally divided into two by the number,
That is, when divided into two sets of dither coefficients such as a, c and b, d or a, b and c, d, the sum of the two sets of dither coefficients is set to 0. I have.

By doing so, even if the dither coefficient is added to the video signal, it becomes less noticeable as noise, and the luminance difference, which is a problem of the conventional example, is further emphasized, and the image quality disturbance in the form of a pseudo contour deteriorates. That doesn't happen. The dither pattern is not limited to the example shown in FIG.
a, b, c, and d are -1, 0, 1, 0, respectively,
0, or 5, 5, -2, -6, 6,-
A plurality of numerical values having different absolute values, such as 2, -3 and -1, may be included. It is preferable, but not limited, that the same number of positive dither coefficients and negative dither coefficients exist in one matrix. The matrix is preferably a square such as n × n dots, but may be a rectangle such as n × m (m （n) dots.

When the matrix of 2 × 2 dots is put together, the sum of the dither coefficients is set to 0, and more preferably, the same number of positive dither coefficients and negative dither coefficients are included. More preferably, the dither coefficients in the diagonal (diagonal) direction have the same absolute value. When an image is displayed on the PDP 300, a matrix of dither coefficients may be appropriately selected so that the gradation characteristics become as smooth as possible and interference is minimized even at the boundary between adjacent matrices.

FIGS. 3A and 3B show examples of arithmetic processing by the video signal processing circuit 100 shown in FIG. 1 when the dither pattern shown in FIG. 2A is used.
In FIGS. 3A and 3B, the input video signal (original signal) is 8 bits, and the dot data corresponding to the dither coefficients a, b, c, and d are 9, 17, 3, and 5, respectively. , (A) shows a case where a dither pattern is added, and (B) shows a case where a dither pattern is added.

In FIG. 3A, an adder 13 adds a dither pattern to an 8-bit original signal,
The original signals of 9, 17, 3, and 5 become data of 7, 18, 2, and 7. Since the data value may exceed 8 bits in this state, the limiter 14 limits only the portion (overflow, underflow) exceeding the 8-bit data. If the PDP 300 has a display capability of only 6 bits, the lower 2 bits may be truncated by the limiter 14 to generate a 6-bit signal of 4, 16, 0, 4. Here, a 6-bit signal is represented by a multiple of four. Therefore, actually, the signals whose lower 2 bits are truncated to be 6 bits are 1, 4, 0, and 1.

In FIG. 3B, a dither pattern is added to the 8-bit original signal by the adder 13.
An original signal of 9, 17, 3, 5 becomes data of 11, 16, 4, and 3. Since the data value may exceed 8 bits in this state, the limiter 14 limits only the portion (overflow, underflow) exceeding the 8-bit data. The output video signals shown in FIGS. 3A and 3B are alternately switched, for example, for each field.

The same operation is performed in the case of FIG. In the case of FIG. 2B, four types of dither patterns are used.
Are switched cyclically in a field cycle, so that a more spatially smooth multi-gradation signal is obtained.

According to the present invention, since the dither pattern in which the sum of the dither coefficients in one dither pattern is zero is added, even if the dither pattern is added to the video signal, the gradation may increase as a whole. In addition, there is no need to reduce the lower bits by the limiter 14 as in the related art. Therefore, the gradation characteristics are smoothly and averagely converted, the visual luminance difference between adjacent gradations is reduced, and the gradation continuity can be improved. Is possible. For this reason, it is possible to significantly reduce the pseudo contour-like image quality disturbance caused by the subfield division.

In this embodiment, the dither pattern is changed every field, but the present invention is not limited to this. The dither pattern may be changed for each frame, the dither pattern may be changed for each adjacent block,
The correspondence between the sections (matrix) and the dots may be changed. That is, the dither pattern is temporally or PDP3
The position on the panel 301 at 00 may be changed.

FIG. 4 is a diagram showing an example of a dither pattern in the case of an odd number in a dither pattern using an n × n dot matrix. Here, n = 3. In FIG. 4, a section composed of nine dots indicated by a to i indicates a dither pattern in a matrix of 3 × 3 dots in vertical (row) × horizontal (column). This 3 × 3 dot dither pattern is similar to that of FIG.
0 is added to the video signal corresponding to the dot data applied to the dot 302 of the panel 301 at 0. For example,
The first row of dot data includes dither coefficients a, b, c, a,
, b, c,... are added in order from the dot at the head of the line, and the dot data in the second line include dither coefficients d, e, f, d, e,
are added in order from the dot at the head of the line, and the dot data on the third line include dither coefficients g, h, i, g, h, i,.
Are added in order from the dot at the beginning of the line. Hereinafter, this is repeated.

In the example shown in FIG. 4, the dither coefficient of e, which is the center of the 3 × 3 dot matrix, is set to 0, and the dither coefficients of a to d and f to i excluding the dither coefficient are made different sequentially. . a to d and f to i are 2, -3, 4, respectively.
-4, -1, 1, -2, 3 dither patterns;
Eight types of dither patterns, which are obtained by shifting the dither patterns a to d and f to i clockwise in the circumferential direction one by one, are used. These dither patterns are used for each field, each frame, and each adjacent block. The switching is performed by regularly circulating. The dither patterns are not shown.

Also in this example, the dither pattern has both a positive dither coefficient and a negative dither coefficient, and the sum of the dither coefficients in one dither pattern (that is, the remaining dither coefficients excluding the center dither coefficient). Is set to 0. Further, in this example, as a preferred embodiment,
The vertical and horizontal centers of a matrix composed of an odd number of coefficients are set to 0, and the remaining even number of coefficients include the same number of positive coefficients and negative coefficients.

In this way, even if the dither coefficient is added to the video signal, it becomes less noticeable as noise, and the luminance difference, which is a problem of the conventional example, is further emphasized, and the image quality disturbance in the form of a pseudo contour deteriorates. That doesn't happen. The dither pattern composed of an odd number of coefficients is not limited to the example shown in FIG. a to d and f to i may include 0. It is preferable, but not limited, that the same number of positive dither coefficients and negative dither coefficients exist in one matrix. The matrix is n × n
It is preferably a square like a dot, but n × m
It may be a rectangle like (m 長方形 n) dots.

When an image is displayed on the PDP 300, a matrix of dither coefficients may be appropriately selected so that the gradation characteristics become as smooth as possible and interference does not occur as much as possible even at the boundary between adjacent matrices.

[0042]

As described above in detail, the video signal processing circuit of the matrix type display device of the present invention includes both a positive dither coefficient and a negative dither coefficient as a dither coefficient pattern, and Since the sum is set to 0, the gradation characteristics are smoothly and averagely converted, the luminance difference in visibility with respect to adjacent gradations is reduced, the continuity of gradations can be improved, and pseudo contours can be improved. Image quality disturbance can be greatly reduced. Further, since it is not necessary to reduce the number of bits, it is possible to display an image with good image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a dither pattern used in the present invention.

FIG. 3 is a diagram for explaining a calculation process when the dither pattern shown in FIG. 2 is used.

FIG. 4 is a diagram showing another example of a dither pattern used in the present invention.

FIG. 5 is a block diagram illustrating an example of the overall configuration of a matrix display device.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a diagram showing an example of a conventionally used dither pattern.

FIG. 8 is a diagram for explaining a calculation process when the dither pattern shown in FIG. 7 is used.

FIG. 9 is a diagram for explaining the correspondence between pixels and dither coefficients in a matrix display device.

[Explanation of symbols]

 11 Dither matrix coefficient generator 12 Selector 13 Adder 14 Limiter

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/34 G09G 3/34 D H04N 9/69 H04N 9/69 F term (Reference) 5C021 PA12 PA62 PA66 PA78 RA02 RB03 XA34 XA35 XB06 YC07 ZA02 5C066 AA03 BA20 CA08 CA17 DD06 EA00 EC02 EC05 EF02 GA04 GB01 HA06 KA08 KD06 KE02 KE04 KE07 KE16 KG01 KM13 KM15 KP05 LA02 5C080 AA05 BB05 DD02 EJ29 FF01

Claims (6)

[Claims] 1. A dither matrix coefficient generator for generating a plurality of dither coefficient patterns in which a plurality of dither coefficients are arranged in a matrix, and one of a plurality of dither coefficient patterns generated by the dither matrix coefficient generator is selected. In a video signal processing circuit of a matrix type display device including a selector and an adder for adding a dither coefficient pattern selected by the selector to an input video signal, the dither coefficient pattern has a positive dither coefficient and a negative dither coefficient. A video signal processing circuit for a matrix type display device, wherein the sum of the dither coefficients is zero. 2. The dither coefficient pattern is composed of an even number of dither coefficients. When dither coefficients constituting the dither coefficient pattern are equally divided into two sets by number, the sum of the two sets of dither coefficients is 2. The video signal processing circuit of a matrix type display device according to claim 1, wherein 0 is set. 3. The video signal processing circuit according to claim 1, wherein said dither coefficient pattern is composed of an odd number of dither coefficients, and a vertical and horizontal center dither coefficient is set to zero. 4. When the remaining dither coefficients in the dither coefficient constituting the dither coefficient pattern, excluding the vertical and horizontal center dither coefficients, are equally divided into two sets by the number, the two
4. The video signal processing circuit according to claim 3, wherein the sum of the dither coefficients of the two sets is zero. 5. The video signal processing circuit of a matrix type display device according to claim 1, wherein said dither coefficient pattern is a square having the same number of vertical and horizontal lines. 6. A video signal processing method according to claim 1, wherein said dither coefficient pattern has the same number of positive dither coefficients and negative dither coefficients. circuit.