JP2000188536A - Reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a reset circuit with less power consumption that stably outputs a reset signal to initialize a circuit at application of power. SOLUTION: The reset circuit consists of an inverter consisting of a P-channel enhancement FET 4 and an N-channel FET 5 and a differentiation circuit consisting of a capacitor 3 and a resistor 2, where an output signal of the differentiation circuit is given to an input stage of the inverter. An absolute value |VTP| of a threshold voltage VTP of the P-channel enhancement FET and a threshold voltage VTN of the N-channel enhancement FET are selected so that the threshold voltage VTN of the N-channel enhancement FET is higher than a value (1st potential-|VTN|). Thus, the reset circuit can generate a reset signal stably at application of power with the circuit configuration of less power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital circuit, and more particularly to a circuit for generating a signal for initializing a circuit after power is turned on.

[0002]

2. Description of the Related Art Conventionally, various types of circuits have been used for this type of circuit. A typical one will be described below with reference to examples.

FIG. 5 shows a typical configuration of a conventional reset circuit. 1 is a terminal connected to the first potential, 2 is a resistor, 3 is a capacitor, 8 is a reset signal output terminal, 9 is an inverter, and a node N1 is an input part of the inverter 9.

[0004] The resistor 2 and the capacitor 3 constitute an integrating circuit. Here, the leakage resistance of the capacitor 3 and the inverter 9
When the input resistance of the node N1 is infinite and a step-like voltage E [V] is applied to the terminal 1 connected to the first potential at time t = 0, the potential Vin of the node N1 is expressed as follows. Is done.

Vin = E · (1−exp (−t / τ)) (1 · 1) where τ is a time constant, and τ = capacitance C of the capacitor
X Resistance value R. Vin increases gradually as τ increases. In the equation (1.1), Vin = 0 [V] at t = 0 [s], and Vin = E [V] at t = ∞ [s]. And Vin is 0
This indicates that the voltage increases exponentially from [V] to E [V]. This is shown in FIG.

Since the reset circuit functions to generate a reset signal until the power supply voltage reaches the final power supply voltage after the power is turned on and becomes sufficiently stable, the value of τ is determined by the rising characteristics of the power supply itself and the electronic device. It is determined in consideration of the capacity between the power supply and the ground potential. The value is the slew rate of a normal digital circuit signal (several [ns] to several tens [n]
s]), which is extremely large, and is determined to be about several tens [ms] to several hundred [ms]. As a result, Vin is a signal that rises very slowly, far from a signal of a normal digital circuit. Care must be taken when receiving such a very slowly changing signal in a digital circuit (such as a gate IC). This is because in a digital circuit, there is a boundary (threshold voltage) for determining an input voltage as a logic level “0” or a logic level “1”. For this reason, depending on the slew rate when the input voltage crosses the threshold voltage, the input voltage crosses the threshold voltage due to minute noise included in the input signal, and the output at the reset output terminal 8 follows the input voltage. This is because the signal may vibrate.

FIG. 10 shows this state. As described above, in the circuit of FIG. 5, a reset signal that vibrates is output, and the timing required for reset may not be satisfied (the H and L periods become unstable).

In order to prevent such inconvenience, the reset circuit usually uses an inverter 9 having Schmitt characteristics. FIG. 11 shows input / output characteristics of an inverter having Schmitt characteristics (hereinafter, referred to as Schmitt inverters). As shown in FIG. 11, the Schmitt inverter has two different threshold voltages when the input voltage rises and when the input voltage falls. If the threshold voltage at the time of rising of the input voltage is Vtrise and the threshold voltage at the time of falling of the input voltage is Vtfall,
Since Vtrise> Vtfall, once the input voltage rises and becomes equal to or higher than Vtrise, the input voltage is determined to be logic level “1”, and the input voltage falls to Vtf
As long as the input voltage does not fall below all, the input voltage is at logic level "0".
Is not determined (in the case of positive logic). Usually Vtris
Since the difference between e and Vtfall is set to several hundred [mV], after the input voltage rises and becomes equal to or higher than Vtrise, the input voltage is determined to be the logic level “1”, and the input voltage is set to be equal to or lower than Vtrise due to minute noise. V
If it does not fall below tfall, the logic level is not determined to be "0". Such a characteristic of the Schmitt inverter is advantageous for the reset circuit because even if the input signal gradually rises, it can be converted into a normal digital signal without impairing the response characteristic. For this reason, the inverter 9 is usually a Schmitt inverter.

However, the Schmitt inverter has a relatively large structure because it has an element for generating a positive feedback in the circuit configuration.

FIG. 7 and FIG. 8 show a portion of the Schmitt inverter that generates positive feedback. FIG. 7 shows the case where the inverter and the resistor are used, and FIG. 8 shows the case where the N-channel enhancement FET and the resistor and the capacitor are used. When the outputs of FIGS. 7 and 8 are further inverted, they become Schmitt inverter outputs.

As a Schmitt inverter, a general-purpose gate IC is also available, but this is one in which six circuits of Schmitt inverters are integrated in a 14-pin DIP or SOP type package. Although only one Schmitt inverter is required to form the reset circuit, using a device integrated for six circuits deteriorates the cost of the product.

Further, 14-pin DIP or SOP type packages are of a large size in view of the trend toward miniaturization of electronic components in recent years, and the use of devices of these packages requires mounting. The area will be squeezed, preventing the product from being downsized.

FIG. 6 shows another reset circuit disclosed in JP-A-5-235727. 1 is a terminal connected to the first potential, R1 and R2 are resistors, C is a capacitor, Q1 and Q2 are MOSFETs, and φR is a terminal for outputting a reset signal. The node N1 is where the gate of Q1 and the gate of Q2 are connected.

In this circuit, the power supply voltage decreases from Vcc1 to Vcc2 at time T1, and thereafter, at time T2, V
The operation at the time of recovery to cc1 will be described with reference to FIG.

In the steady state, the potential of node N1 is (R2 /
(R1 + R2)) · Biased to Vcc1 and C
Is charged and the voltage across it is (R1 / (R1 + R
2)) · Vcc1. When Vcc1 drops to Vcc2, the potential VN1 of the node N1 at that moment becomes Vcc2- (R
1 / (R1 + R2)). Vcc1, which is the threshold voltage VT of the inverter composed of Q1 and Q2.
In the following cases, φR outputs “H”. Thereafter, the potential of the node N1 increases with (R2 / (R1 + R2)) · Vcc2 asymptotically, and the power supply voltage changes from Vcc2 to Vc.
At the moment of recovery to c1, the capacitor C causes the node N1
Is raised. As a result, the potential of the node N1 exceeds the threshold voltage VT of the inverter, so that the signal of the output terminal φR becomes “L”.

However, the reset signal of the reset circuit shown in FIG. 6 is for detecting a change in the power supply, and does not output the reset signal when the power is turned on. This will be described with reference to FIG.

At the moment when the power is turned on, the potential of the node N1 becomes Vcc1 and exceeds the threshold voltage of the inverter, so that the output terminal φR outputs "L". Thereafter, as the capacitor C is gradually charged, the potential of the node N1 decreases, and (R2 / (R1 + R2)). Vc
It converges to c1. However, the potential of the node N1 is Q1
And Q2 does not fall below the threshold value VT of the inverter. For this reason, the potential of the node N1 is always equal to or higher than the threshold voltage of the inverter from the time when the power is turned on until the power becomes stable. Not done.

Immediately after the power is turned on, the power supply to the devices constituting the system is simultaneously started. However, since the voltage of each node in the system changes very far from the steady state until it reaches the steady state, it is necessary for the device that needs to be reset to properly reset inside the device. State cannot be determined. As a result, depending on the case, an abnormal current path may be generated inside the device, or a device that changes its state by writing a command may cause a malfunction such as a transition to an unintended mode.

Further, considering that the reset circuit shown in FIG. 6 is determined by biasing the potential of the node N1 with the resistance ratio of R1 and R2 so as not to be affected by the input resistance of the inverter, The values are all 10
[KΩ] to about 100 [kΩ]. If R1 =
20 [kΩ], R2 = 30 [kΩ] and the power supply voltage is 5
If [V] is set, a current of 100 [μA] always flows through R1 and R2 regardless of whether or not the reset operation is being performed. This current is very large considering that the standby current of recent semiconductor memories in general is several [μA] to several tens [μA]. In particular, it is not advisable for a battery-operated portable device to have a path through which current always flows in a circuit, because it hinders long-term operation.

[0020]

In the above-mentioned conventional reset circuit, since the output of the integrating circuit in the reset circuit changes very slowly, the reset circuit is connected to the integrating circuit by noise depending on its slew rate. There was a risk that the output of the inverter would vibrate and not reset. In addition, depending on the configuration of the reset circuit, a reset signal is not output when the power is turned on, or a path for constantly flowing current is provided, which is disadvantageous in terms of current consumption. Further, since a Schmitt inverter is required, even if this is a general-purpose gate IC, it is disadvantageous in terms of economy and mounting area.

[0021]

According to a first aspect of the present invention, there is provided a reset circuit comprising a P-channel enhancement FET and an N-channel enhancement F based on an output of a differentiating circuit.
It is configured to control ET. That is, the second node of the capacitor is connected to the first node of the resistor, the first node of the capacitor is connected to the first potential, and the second node of the resistor is connected to the second potential. A P-channel enhancement FET having a source connected to the first potential, and an N-channel enhancement FET having a drain connected to a drain and an output terminal of the P-channel FET;
Is connected to the gate of the P-channel enhancement FET and the gate of the N-channel enhancement FET, and is connected to the N-channel enhancement FET.
Has a configuration connected to the second potential, and the absolute value | VTP | of the threshold value of the P-channel enhancement FET and the threshold value VTN of the N-channel enhancement FET are VTN (first Potential of-
VTP│), the threshold value VTP of the P-channel enhancement FET and the threshold value VTN of the N-channel enhancement FET are set.

As a result, a reset circuit solving the above problem can be realized, and a low-level reset signal can be generated stably when the power is turned on.

The reset circuit of the present invention according to claim 2 is
In the first reset circuit, a cathode of a diode is further connected to a first node of the resistor, and an anode of the diode is further connected to a second node of the resistor. It is.

As a result, it is possible to realize a reset circuit that solves the above-mentioned problem, and to stably generate a low-level reset signal even when the power is turned on after the power is turned off.

The reset circuit of the present invention according to claim 3 is
In the first reset circuit, the positional relationship between a resistor and a capacitor is replaced. The P-channel enhancement FE is output by the output of the integrating circuit constituted by these components.
This is a configuration for controlling the T and N channel enhancement FETs. That is, the second node of the resistor is connected to the first node of the capacitor, and the first node of the resistor is connected to the first node.
Is connected to a first potential, a second node of the capacitor is connected to a second potential, and a source is connected to the first potential.
P-channel enhancement F connected to the potential of
ET and the N-channel enhancement FET whose drain is connected to the drain and output terminal of the P-channel FET, the first node of the capacitor being connected to the gate of the P-channel enhancement FET and the N-channel enhancement FET.
Connected to the gate of the channel enhancement FET,
The source of the N-channel enhancement FET has a configuration connected to the second potential, and the absolute value | VT of the threshold value of the P-channel enhancement FET
P│ and the threshold value VTN of the N-channel enhancement FET are such that VTN is higher than (first potential −│VTP│).
Threshold value VTP and the N-channel enhancement F
It is characterized by setting a threshold value VTN of ET.

As a result, a reset circuit that solves the above problem can be realized, and a high-level reset signal can be stably generated when power is turned on.

The reset circuit of the present invention according to claim 4 is
In the third reset circuit, a cathode of a diode is further connected to a first node of the resistor, and an anode of the diode is further connected to a second node of the resistor. It is.

As a result, it is possible to realize a reset circuit that solves the above problem, and to stably generate a high-level reset signal even when the power is turned on again after the power is turned off.

[0029]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a reset circuit according to a first embodiment of the present invention. 1 is a terminal connected to the first potential, 2
Is a resistor, 3 is a capacitor, 4 is a P-channel enhancement FET, 5 is an N-channel enhancement FET,
Reference numeral 6 denotes a node where the gate of the P-channel enhancement FET 4 and the gate of the N-channel enhancement FET 5 are connected, and 8 denotes a reset signal output terminal. The first node of the capacitor 3 and the source of the P-channel enhancement FET 4 are connected and connected to the terminal 1. The second node of the capacitor 3, the first node of the resistor 2, the gate of the P-channel enhancement FET 4 and the gate of the N-channel enhancement FET 5 are connected to form a node 6. The second node of the resistor 2 and the source of the N-channel enhancement FET 5 are both grounded. The drain of the P-channel enhancement FET 4 and the drain of the N-channel enhancement FET 5 are connected to form a reset signal output terminal 8.

Next, the operation will be described with reference to FIGS. The resistor 2 and the capacitor 3 constitute a differentiating circuit, and the node 6 almost reaches the power supply voltage immediately after the power is supplied to the terminal 1 connected to the first potential. As a result, P
The absolute value of the voltage Vgs between the gate and the source of the channel enhancement FET 4 is 0 [V], the voltage Vgs between the gate and the source of the N-channel enhancement FET 5 becomes almost the power supply voltage, and the P-channel enhancement FET
4 is OFF state, N-channel enhancement FET 5
Is turned on. N-channel enhancement FET
When 5 is first turned on, a low level “L” is output from the reset output terminal 8 and becomes a reset signal.

Next, since the potential of the node 6 decreases exponentially, the voltage of the N-channel enhancement FET 5
gs decreases, and the N-channel enhancement FET 5
Is lower than the threshold voltage VTN of the N-channel enhancement FET 5, the N-channel enhancement FET 5 is turned off. At this point, the P-channel enhancement FET 4 is still in the OFF state. Further, since the potential of the node 6 decreases exponentially, Vgs of the P-channel enhancement FET 4
The absolute value of increases. Then, the potential of the node 6 is equal to or less than (power supply voltage − | VTP |), that is, the absolute value of Vgs of the P-channel enhancement FET 4 is equal to the absolute value of the threshold voltage of the P-channel enhancement FET 4 | VTP.
When the value becomes | or more, the P-channel enhancement FET 4 is turned ON, so that a high level “H” is output from the reset output terminal 8. This means that the reset has been released. Thus, the P-channel enhancement FE
By setting the threshold voltages of both the T4 and the N-channel enhancement FET 5 so that VTN> (power supply voltage− | VTP |), the output characteristics can be monotonically adjusted without using a Schmitt inverter. It can be reduced.

The threshold value is set by using a P-type impurity (for example, boron) or an N-type impurity (for example, phosphorus or arsenic).
When ions are implanted into the channel portion of the ET, it can be easily set by a known technique such as changing the implantation amount or changing the gate thickness.

FIG. 2 shows a reset circuit according to a second embodiment of the present invention.

In the second embodiment, a diode 7 is further connected to both ends of the resistor 2 in FIG.
The configuration and function of each unit other than the diode 7 are the same as those in FIG. The cathode of diode 7 is connected to the first node of resistor 2 while the anode of diode 7 is connected to the second node of resistor 2 and is grounded. The diode 7 constitutes a path for rapidly discharging the electric charge charged in the capacitor 3 to the power supply line after the power supply is cut off. The charge accumulated in the capacitor 3 after the power is turned off is discharged to the power line through the resistor 2. However, the time constant τ by the resistor 2 and the capacitor 3 is set to about several tens [ms] to several hundred [ms] for resetting. For this reason, the electric charge of the capacitor 3 is not sufficiently discharged unless a sufficient time equal to or longer than τ is secured after the power is turned off until the power is turned on again. For this reason, the peak of the potential of the node 6 immediately after the power is turned on again does not rise as much as when the initial charge of the capacitor 3 is 0, and as a result, does not exceed the threshold voltage of the N-channel enhancement FET 5 and has a low level. A case where the reset signal is not output may occur. The diode 7 forms a path for rapidly discharging the electric charge of the capacitor 3 after the power is turned off, thereby eliminating this fear and ensuring the operation of the reset circuit.

The reset circuit described in the first and second embodiments is for a case where the initialization of the digital circuit at the time of power-on is performed by a low-level reset signal.

FIG. 3 shows a reset circuit according to a third embodiment of the present invention. 1 is a terminal connected to the first potential, 2 is a resistor, 3 is a capacitor, 4 is a P-channel enhancement FET, and 5 is an N-channel enhancement F
ET and 6 are nodes and P channel enhancement F
ET4 gate and N-channel enhancement FET5
8 denotes a reset signal output terminal. The first node of the resistor 2 and the source of the P-channel enhancement FET 4 are connected and connected to the terminal 1.
The second node of the resistor 2, the first node of the capacitor 3, the gate of the P-channel enhancement FET 4 and the gate of the N-channel enhancement FET 5 are connected to form a node 6. The second node of the capacitor 3 and the source of the N-channel enhancement FET 5 are both grounded. The drain of the P-channel enhancement FET 4 and the drain of the N-channel enhancement FET 5 are connected to form a reset signal output terminal 8. This embodiment has a configuration in which the positions of the resistor and the capacitor of the first embodiment are interchanged.

Next, the operation will be described with reference to FIGS. The resistor 2 and the capacitor 3 form an integrating circuit. Initially, immediately after power is supplied to the terminal 1 connected to the first potential, the node 6 is at the second potential (usually a ground potential). As a result, the absolute value of the voltage Vgs between the gate and the source of the P-channel enhancement FET 4 becomes the power supply voltage, and the N-channel enhancement FET 5
Since the voltage Vgs between the gate and the source becomes 0 [V], the P-channel enhancement FET 4 is turned on, while the N-channel enhancement FET 5 is turned off. P-channel enhancement FET
When 4 is first turned on, a high level “H” is output from the output terminal 8 and becomes a reset signal. Next, since the potential of the node 6 increases exponentially, the absolute value of Vgs of the P-channel enhancement FET 4 decreases,
When the potential of the node 6 becomes equal to or more than (power supply voltage − | VTP |), that is, when the absolute value of Vgs of the P-channel enhancement FET 4 becomes equal to or less than the absolute value | VTP | of the threshold voltage of the P-channel enhancement FET 4, the P-channel enhancement FET 4 It turns off. At this point, the N-channel enhancement FET 5 is still
It remains in the FF state.

Further, since the rise of the potential of the node 6 increases exponentially, Vgs of the N-channel enhancement transistor 5 increases. When Vgs of the N-channel enhancement FET 5 becomes equal to or higher than the threshold voltage VTN of the N-channel enhancement FET 5, the N-channel enhancement FET 5 is turned on, and the second potential 2 is passed to the drain side.
Outputs a low level "L". This releases the reset. As described above, the threshold voltages of both the P-channel enhancement FET 4 and the N-channel enhancement FET 5 are set to VTN> (power supply voltage− | VTP
By setting the threshold value so as to satisfy the relationship of |), the output characteristics can be monotonically increased without using a Schmitt inverter. As in the case of the first embodiment, there is no possibility of causing an unintended vibration in the reset signal.

Next, FIG. 4 shows a reset circuit according to a fourth embodiment of the present invention. In the fourth embodiment, a diode 7 is further connected to both ends of the resistor 2 in FIG. 3, and the configuration and function of each part other than the diode 7 are the same as those in FIG.
Is the same as The cathode of diode 7 is connected to the first node of resistor 2 and to terminal 1, while the anode of diode 7 is connected to the second node of resistor 2. The diode 7 is for forming a path for rapidly discharging the electric charge charged in the capacitor 3 to the power supply line after the power supply is cut off, as in the case of FIG. In FIG. 3 as well, the electric charge of the capacitor 3 is not sufficiently discharged unless a sufficient time longer than the time constant τ is secured after the power is turned off until the power is turned on again. Therefore, the potential of the node 6 immediately after the power is turned on again becomes the second potential.
, The absolute value of Vgs of the P-channel enhancement FET 4 does not exceed the absolute value of the threshold voltage of the P-channel enhancement FET 4, and as a result, a high-level reset signal is not output. Can occur. The diode 7 forms a path for rapidly discharging the electric charge of the capacitor 3 after the power is turned off, as in the case of FIG. 2, thereby eliminating this fear and ensuring the operation of the reset circuit.
As described above, the reset circuits described in the third and fourth embodiments are for the case where the initialization of the digital circuit at the time of power-on is performed by a high-level reset signal.

[0041]

As described in detail above, the threshold value VTP and the N-channel enhancement FE of the P-channel enhancement FET constituting the reset circuit are described.
The threshold value VTN of T is determined by the following equation.
│), and each threshold value is set so that the value of VTN− (power supply voltage−│VTP│) takes an appropriate value (for example, several hundred [mV]). Thus, a stable reset signal can be generated which is resistant to noise and free from unintentional vibration even though the Schmitt inverter is not used.

Further, by inserting a diode in parallel with the resistor constituting the reset circuit, a stable reset signal can be generated even when the power is turned on after the power is turned off.

Then, after a period in which the signals on the system compete with each other immediately after the power is turned on, the reset can be reliably released.

Further, since the circuit does not include a bleeder resistor for bias, there is no path for constantly flowing current.
An extremely low power consumption reset circuit can be configured.

Furthermore, since the configuration does not require a Schmitt inverter, the present reset circuit has advantages in terms of economy and mounting area, particularly when it is configured with individual elements.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a first example of a conventional reset circuit.

FIG. 6 is a circuit diagram showing a second example of a conventional reset circuit.

FIG. 7 shows a first example of a positive feedback generator in a Schmitt inverter.
FIG. 4 is a circuit diagram showing an example of the embodiment.

FIG. 8 shows a second example of the positive feedback generator in the Schmitt inverter.
FIG. 4 is a circuit diagram showing an example of the embodiment.

FIG. 9 is a diagram illustrating output characteristics of an integration circuit at a node N1 in FIG. 5;

FIG. 10 is a diagram illustrating an influence on an output when noise is applied to a node N1 in FIG. 5;

FIG. 11 is a diagram showing input / output characteristics of a Schmitt inverter.

FIG. 12 is a diagram illustrating the operation of FIG. 6;

FIG. 13 is a diagram showing that a reset signal is not output when power is turned on in FIG. 6;

FIG. 14 is a diagram showing the operation of FIGS. 1 and 2;

FIG. 15 is a diagram showing the operation of FIGS. 3 and 4;

[Description of Signs] 1 Terminal connected to first potential 2 Resistor 3 Capacitor 4 P-channel enhancement FET 5 N-channel enhancement FET 6 Node in reset circuit (first node of resistor or capacitor) 7 Diode 8 Reset signal Output terminal 9 Inverter

Claims (4)

[Claims] 1. A reset circuit for generating a reset signal for initializing a circuit at power-on, wherein a second node of a capacitor is connected to a first node of a resistor, and the first node of the capacitor is a first node of the capacitor. A second node of the resistor is connected to a second potential, a source is connected to the first potential, and a drain is a drain of the P-channel FET and an output terminal. And a first node of the resistor is connected to the P-channel FET.
The source of the N-channel enhancement FET is connected to the gate of the N-channel enhancement FET and the gate of the N-channel enhancement FET.
And the absolute value | VTP | of the threshold value of the P-channel enhancement FET.
And a threshold value VTN of the N-channel enhancement FET is set such that VTN is higher than (first potential − | VTP |). 2. The reset of claim 1, wherein a cathode of a diode is further connected to a first node of the resistor, and an anode of the diode is further connected to a second node of the resistor. circuit. 3. A reset circuit for generating a reset signal for initializing a circuit when power is turned on.
Is connected to a first node of a capacitor, a first node of the resistor is connected to a first potential, a second node of the capacitor is connected to a second potential, and a source is connected to the first node. And a N-channel enhancement FET having a drain connected to the drain and output terminal of the P-channel FET, and a first node of the capacitor is connected to the P-channel enhancement FET. A gate connected to the gate of the N-channel enhancement FET, a source of the N-channel enhancement FET connected to the second potential;
Absolute value of threshold value of channel enhancement FET│
VTP | and the threshold value VTN of the N-channel enhancement FET are VTN (first circuit. 4. The reset of claim 3, further comprising a diode cathode connected to a first node of the resistor, and an anode of the diode further connected to a second node of the resistor. circuit.