JP2000188341A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor storage device to detect multilevel data with accuracy by constituting the device to sense changes in lapse of time and to refer to the matrix of thresholds and drain current values. SOLUTION: The memory section of an MROM is provided with a memory cell array 21, a loader coder 22 which controls the word line to which the gate of each memory cell is commonly connected, a column decoder 23 which controls bit lines, and a bias circuit 24 which biases the bit lines. The memory section is electrically connected to a sense amplifier 25. When, for example, four different threshold voltages are to be sensed, three sense amplifiers are required. To the sense amplifier 25, a logic circuit 26 which makes the outputs of three sense amplifiers correspond to two addresses D0 and D1 is electrically connected. Therefore, the difference between the output waveforms of multilevel data cells can be recognized when the rising times and voltage and current values of the output waveforms are monitored with time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having a multi-valued MROM memory cell for detecting a threshold value and a drain current to determine a decimal data value. It relates to the manufacturing method.

[0002]

2. Description of the Related Art Conventionally, in a memory cell array of a general read-only memory (ROM), MOSFETs are arranged in a matrix, the gate of each memory cell is connected to a plurality of word lines in a row direction, and a source and a drain are arranged. Is connected to a plurality of bit lines in a column direction.

In a normal ROM, a 1-bit memory cell is constituted by one transistor, and data of each memory cell is obtained by setting the threshold voltage of the transistor to a high level and a low level. I have. However, since only one bit of data can be stored in one memory cell, there is a disadvantage that the chip size becomes large.

Therefore, a ROM employing a method of storing a plurality of data in one memory cell, that is, a so-called multi-valued memory ROM has been proposed. As a method, a method of setting a plurality of different current values by changing a gate length, a gate width, and a gate oxide film thickness of a transistor of a memory cell, or changing a threshold value to a plurality by changing an ion implantation amount. is there.

[0005]

However, according to the prior art, since only one bit of data can be stored in one memory cell, there is a disadvantage that the chip size becomes large when the capacity is increased. In the case of a multilevel memory cell, the gate length and gate width of the transistor,
There is a method in which a plurality of different current values are set by changing the gate oxide film thickness, or a method in which the threshold voltage is changed to a plurality by changing the ion implantation amount, but the read detection method is difficult.

The present invention has been made in view of such circumstances, and has a configuration in which a change with time is detected and a matrix of a threshold value and a drain current value is referred to.
It is an object of the present invention to provide a semiconductor memory device capable of detecting multi-value data with high accuracy and a method of manufacturing the same.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor substrate, a plurality of first bit lines formed on the semiconductor substrate, and a first bit line formed on the semiconductor substrate. A plurality of first ground lines alternately arranged, and a plurality of memory cells in which memory transistors having drains connected to the first bit lines and sources connected to the first ground lines are arranged in a matrix. A first selection transistor formed on the semiconductor substrate and connected to the first bit line, a second selection transistor formed on the semiconductor substrate and connected to the first ground line, and the memory transistor A plurality of word lines connected to the first gate line and intersecting the first bit line and the first ground line; and the first bit line is connected to the first selection transistor. A second bit line connected at least three through the first ground line is the second
And at least two second ground lines connected via a selection transistor of the memory cell. In the data reading, one of the memory cells is selected, and the drain voltage of the output signal drain voltage from the memory cell is selected. The semiconductor memory device is characterized in that the change is performed by reading a change with time, that is, a voltage drop, and recognizing 10 levels of 10 conditions from a matrix table showing a relationship between an attained threshold value and a voltage drop value.

According to a second aspect of the present invention, there is provided a semiconductor substrate, a plurality of first bit lines formed on the semiconductor substrate, and a plurality of first bit lines formed on the semiconductor substrate and alternately arranged with the first bit lines. A plurality of memory cells in which a memory transistor having a first ground line, a drain connected to the first bit line, and a source connected to the first ground line are arranged in a matrix, and formed on the semiconductor substrate; A first selection transistor connected to the first bit line, a second selection transistor formed on the semiconductor substrate and connected to the first ground line, and a gate connected to the memory transistor; A plurality of word lines intersecting the first bit line and the first ground line, and at least one of the first bit lines via the first selection transistor; A second bit line which is three connections,
In a method of manufacturing a semiconductor memory device having a first ground line and at least two second ground lines connected via the second selection transistor, the first
Implanting ions having a first dose into the channel region of the memory transistor of the semiconductor substrate using the mask described above, and implanting ions having a second dose into the channel region using the second mask The second dose is not implanted, the first dose is implanted, the second dose is implanted, and the first and second doses are implanted. Arbitrarily adopting the case where the ion implantation is performed with an overlapping amount to set any one of the ten types of thresholds.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multi-level MROM memory cell according to one embodiment of the present invention will be described below with reference to the drawings. The materials, numerical values, and the like of the components described in the examples described below are merely examples, and do not limit the present invention.

FIG. 1 shows an equivalent circuit diagram of a multi-level MROM memory cell according to the present invention. 2 is a plan view of a main part of FIG. 1, FIG. 3 is an explanatory view of an X part (memory cell) of FIG. 2, and FIG. 4 is a method of injecting a threshold (V _th ) into the memory cell. FIG.

On the semiconductor substrate 10, a plurality of first bit lines (not shown) and a plurality of first ground lines are alternately arranged. The bit lines and the ground lines are constituted by diffusion layers formed on the surface of the semiconductor substrate 10. A plurality of memory cells (not shown) in which a semiconductor transistor 10 having a drain connected to the first bit line and a source connected to the first ground line are arranged in a matrix on the semiconductor substrate 10. Are formed. The semiconductor substrate 10 further includes a first selection transistor 2 connected to the first bit line, and a first selection transistor 2 connected to the first bit line.
The second selection transistor 3 connected to the ground line is formed.

[0012] The semiconductor substrate 10 includes a plurality of word lines 4 ₁ to 4 _n is the first bit line made of polysilicon, are formed so as to intersect with the first ground line. On the semiconductor substrate 10, three first bit lines are connected via the first selection transistor 2.
1 is formed via an insulating film (not shown). On the semiconductor substrate 10, a second ground line 6 made of Al and having three first ground lines connected through the second selection transistor 3 is formed via an insulating film. Note that reference numerals 7a, 7
Reference characters b, 7c, 7d, and 7e denote bank selection lines made of polycrystalline silicon, respectively.

As shown in FIG. 3, one memory cell is
For example, a source region 11 on a surface of a semiconductor substrate 10 such as Si,
The structure is such that a drain region 12 is formed, and a gate electrode 14 made of polycrystalline silicon is provided on a substrate 10 via a gate oxide film 13 along a channel width direction.

In FIG. 4, reference numerals 15 and 15 indicate wirings made of polycrystalline silicon. Ions for adjusting the threshold value are implanted into one of these wirings 15 using a photoresist 16. At this time, in the conventional type, ions are implanted from the hole for the polysilicon width W as shown in FIG. 5, but in the present invention, as shown in FIG. I do.

More specifically, as shown in FIGS. 8A to 8J, two times of photo and one time of ion implantation are performed in the ion implantation region (more precisely, two times of high level implantation and one time of high level implantation). Times,
By dividing the memory transistor into four levels (including one low-level injection and no low-level injection), the memory transistors can be distinguished into ten conditions and ten value levels. The method of reading data is as follows. One memory cell is selected, the change with time of the output signal drain current Id from this memory cell is read (see FIG. 7),
Recognize 0 condition 10 value level. In FIG. 7,
Vds indicates a source-drain voltage, and Vgs indicates a source-gate voltage.

[0016]

[Table 1]

FIG. 9 is a characteristic diagram showing the relationship between the time t and Vgs of the memory cell, and FIG. 10 is a characteristic diagram showing the relationship between the time t and Vds. FIG. 11 is a characteristic diagram showing a relationship between the time t of the memory cell and the drain current Id, that is, a time change of the output current. 11A to 11J correspond to FIGS. 8A to 8J, respectively. For example, FIG. 11A shows a case where the condition 9 is recognized as “9”.

FIG. 12 shows a circuit configuration for detecting multi-value data of a memory cell according to the present invention. The memory portion of the MROM includes a memory cell array 21, a loader coder 22 for controlling a word line to which a gate of each memory cell is commonly connected, and a column decoder 23 for controlling a bit line.
And a bias circuit 24 for biasing the bit lines. The memory portion is electrically connected to the sense amplifier 25. Here, for example, to sense four different threshold voltages, three sense amplifiers are required. Each amplifier receives three different references, one for each. A logic circuit 26 for making the outputs of the three sense amplifiers correspond to the two addresses D0 and D1 is electrically connected to the sense-up 25.

When multi-value data is detected by the circuit configuration shown in FIG. 12, the detection is performed as follows. That is, by monitoring the rise time of the output waveform, the voltage, and the current value over time, the difference between the output waveforms of the multi-value data cells can be recognized. When detecting multi-valued data, it can be distinguished by a combination of rising and falling voltage changes.

In the MROM multi-valued memory cell of the above embodiment, the transistor is divided into two by injecting through a W / 2 width ion implantation hole as shown in FIG.
As shown in the figure, the ion implantation area is divided into two photo and one ion implantation intensity (exactly four levels including high level implantation twice, high level implantation once, low level implantation once, and none) By doing so, the memory transistors can be distinguished into ten conditions and ten value levels. Then, in the data reading, one memory cell is selected, the temporal change of the output signal drain voltage Vds from this memory cell is read (see FIG. 7), and the attained threshold value and the voltage drop value are shown in Table 1 above. This is performed by recognizing 10 conditions and 10 value levels from the matrix table shown. Therefore, the conventional 1/0 value (binary)
Multivalued data can be detected with higher accuracy than in the case of a storage element.

Further, in the method of manufacturing an MROM multi-valued memory cell according to the above embodiment, ions having a first dose are formed by using a photoresist 16 as a first mask. After the implantation into the region, ions having a second dose are implanted into the channel region using a second mask, and if the ion implantation at the second dose is not performed, the ions at the first dose are implanted. The case where the ion implantation is performed, the case where the ion implantation of the second dose is performed, and the case where the ion implantation is performed by overlapping the first and second doses are arbitrarily adopted, and ten kinds of threshold values are set. By setting either one, multi-valued data can be detected with higher accuracy than in the case of the conventional 1/0 value (binary) storage element, similarly to the above.

[0022]

As described in detail above, according to the present invention, multi-value data can be detected with high accuracy by detecting a change with time and referring to a matrix of threshold values and current drop values. And a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a multi-level MROM memory cell according to one embodiment of the present invention.

FIG. 2 is a plan view of a main part of FIG. 1;

FIG. 3 is an explanatory diagram of a memory cell in an X section in FIG. 2;

FIG. 4 is an explanatory diagram of a case where ions for threshold adjustment are implanted into a specific transistor memory cell constituting the memory cell of FIG. 1;

FIG. 5 is an explanatory diagram showing a state of ion implantation of a conventional memory cell.

FIG. 6 is an explanatory view showing a state of ion implantation of a memory cell of the present invention.

FIG. 7 is an explanatory diagram of a data reading method according to the present invention.

FIG. 8 is an explanatory view of a pattern of threshold value adjusting ion implantation in a memory cell according to the present invention.

FIG. 9 is a characteristic diagram showing a relationship between time and a gate-source voltage according to the present invention.

FIG. 10 is a characteristic diagram showing a relationship between time and a source-drain voltage according to the present invention.

FIG. 11 is a characteristic diagram showing a relationship between time and drain current under each condition according to the present invention.

FIG. 12 is a circuit configuration diagram for detecting multi-level data of the multi-level MROM memory cell of FIG. 1;

[Explanation of symbols]

1 ... memory transistor, 2 ... first selection transistor, 3 ... second selection transistors, 4 _1, 4 _2, 4 ₃ ... word lines, 5 ... second bit line, 6: second ground line, 7a 7b, 7c: bank selection line, 10: semiconductor substrate, 21: memory cell array, 22: loader coder, 23: column decoder, 24: bias circuit, 25: sense amplifier, 26: logic circuit.

Claims (2)

[Claims] 1. A semiconductor substrate, a plurality of first bit lines formed on the semiconductor substrate, and a plurality of first ground lines formed on the semiconductor substrate and alternately arranged with the first bit lines. A plurality of memory cells in which a memory transistor having a drain connected to the first bit line and a source connected to the first ground line is arranged in a matrix; A first selection transistor connected to the first bit line, a second selection transistor formed on the semiconductor substrate and connected to the first ground line, and a first selection transistor connected to a gate of the memory transistor. A plurality of word lines intersecting the first ground line and at least three word lines intersecting the first ground line and the plurality of word lines intersecting the first ground line; 2 bit lines and at least two second ground lines connected to the first ground line via the second selection transistor, and data is read out of one of the memory cells. This is performed by selecting a memory cell, reading the temporal change of the output signal drain voltage from the memory cell, that is, the voltage drop, and recognizing 10 conditions and 10 value levels from a matrix table showing the relationship between the reached threshold and the voltage drop value. A semiconductor memory device characterized by the above-mentioned. 2. A semiconductor substrate, a plurality of first bit lines formed on the semiconductor substrate, and a plurality of first ground lines formed on the semiconductor substrate and alternately arranged with the first bit lines. A plurality of memory cells in which a memory transistor having a drain connected to the first bit line and a source connected to the first ground line is arranged in a matrix; A first selection transistor connected to the first bit line, a second selection transistor formed on the semiconductor substrate and connected to the first ground line, and a first selection transistor connected to a gate of the memory transistor. A plurality of word lines intersecting the first ground line and at least three word lines intersecting the first ground line and the plurality of word lines intersecting the first ground line; A method of manufacturing a semiconductor memory device comprising two bit lines and at least two second ground lines connected to the first ground line via the second selection transistor; Implanting ions having a first dose into a channel region of the memory transistor of the semiconductor substrate using the method, and implanting ions having a second dose into the channel region using a second mask; This second
Is not performed, the first dose is implanted, the second dose is implanted, and the first and second doses are overlapped. Arbitrarily adopting the case where the implantation is performed and setting any one of ten types of thresholds.