JP2000188334A - Semiconductor integrated circuit correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the recurrence of timing violation by making wiring variation delicate when layout correction is performed by making delays improvable by inserting another cell having a high-driving force even when such a high driving-force cell that has the same logic as that a cell to be improved for delay does not exist. SOLUTION: A path 121 which violates a timing restriction is specified by performing delay calculation and timing analysis based on a wiring capacity/ resistance 111 from layout data. Then a cell 122 to be improved is specified out of cells existing on the violating path 121. On the cell 122, cell exchanging is performed for timing improvement based on a prescribed cell library. When the timing violation is not dissolved for the cell 122, a correction circuit 123 is generated by connecting a buffer between the output pins of the cell 122. Then a corrected layout 112 is generated by correcting the layout of the circuit 123. The buffer is arranged adjacently to the cell 122.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for correcting a circuit used in a layout design of a semiconductor device, and more particularly to a method for correcting a violation of a path delay time constraint.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, the influence of the delay due to the parasitic capacitance of the wiring is dominant over the delay of the element itself, so that a timing constraint violation occurs after the layout design process. In order to correct the timing constraint violation, circuit delay information is extracted from the layout data, and the process returns to the logic circuit design process to correct the timing constraint violation. Then, based on the circuit whose timing constraint violation has been corrected, partial layout correction is performed again in the layout design process.

In the case of a standard cell design, generally,
The violation of the timing constraint is corrected by increasing the driving capability of the cell.

In Japanese Patent Application Laid-Open No. Hei 7-31794, in addition to changing the driving capability of a cell, a buffer with a high driving capability is inserted, and the lack of driving capability is compensated for by cell parallelization. At this time,
The delay value after correction is estimated as a fixed wiring load capacity.

[0005]

However, in changing the driving capability of a cell, the delay cannot be improved unless a predetermined cell library has a cell with a high driving capability having the same logic as the cell whose delay is to be improved.

In addition, when a high driving capability buffer is inserted, the wiring route is changed by rewiring depending on the layout in the layout correction, and thus differs from the wiring load capacitance at the time of the timing violation correction. Occurs.

In addition, the area is increased by buffer insertion and cell parallelization, the arrangement variation in rearrangement in layout correction becomes large, and the possibility of reoccurrence of timing violation is increased.

The present invention makes it possible to improve the delay by inserting another high drive capability cell even if there is no high drive capability cell having the same logic as the cell whose delay is to be improved,
An object of the present invention is to prevent a timing violation from recurring by minimizing wiring fluctuations in layout modification.

Further, by reducing the area of the cell for which the delay is to be improved, an increase in the area due to the insertion of a cell having a high driving capability is prevented.

[0010]

According to the present invention, there is provided a circuit repair apparatus for performing a timing analysis based on a wiring capacitance and a resistance from layout data to specify a path violating a predetermined timing constraint. Means for specifying a cell for which delay improvement is to be attempted from cells existing in the violation path, cell replacement means for replacing the delay improvement trial cell with a high-drive capacity cell having the same logic in a predetermined cell library, and the cell replacement means In the case where the timing constraint is not satisfied, a buffer insertion means for inserting a high drive capacity buffer immediately after the delay improvement trial cell to reduce the area of the delay improvement trial cell; and It has a layout correction means arranged adjacent to the improvement trial cell, and corrects a circuit of a timing constraint violation path.

In addition, the circuit repair apparatus of the present invention performs timing analysis based on wiring capacitance and resistance from layout data to specify a path violating a predetermined timing constraint, and Means for identifying a cell for which delay improvement is to be attempted from cells to be improved, cell replacement means for replacing the delay improvement trial cell with a cell having the same logic in a predetermined cell library, and the timing constraint in the cell replacement means. If not, replace the delay improvement trial cell with a small area cell having negative logic of the delay improvement trial cell, and insert an inverter with high driving capability immediately after the negative logic cell; Layout modifying means for arranging the high drive capability buffer adjacent to the delay improvement trial cell, Do the road modifications.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a circuit correction device according to a first embodiment of the present invention.

In FIG. 1, violation path specifying means 101
Performs delay calculation and timing analysis based on the wiring capacitance / resistance 111 from the layout data, and specifies a path 121 that violates a predetermined timing constraint. The correction cell specifying unit 102 specifies a correction cell 122 to be improved from cells existing on the timing violation path 121. The cell exchange means 103 performs cell exchange for timing improvement on the modified cell 122 based on a predetermined cell library, and generates a modified circuit 123. If the timing violation is not resolved by the cell exchange means 103 for the corrected cell 122,
A buffer is inserted into the output pin of the correction cell 122 to generate the correction circuit 123. Layout modification means 105
Performs a layout correction on the correction circuit 123 to generate a corrected layout 112. At this time, the correction circuit 1
If the buffer insertion unit 104 inserts a buffer, the buffer is arranged adjacent to the correction cell 122.

Next, the process of circuit correction will be described with reference to FIGS. 1, 2 and 3. FIG. 2A shows a path 12 having a timing violation specified by the violation path specifying unit 101.
1 is an example. The correction cell specifying means 102 specifies the cell 203 as a correction cell from the timing violation path 121. As a method of specifying a correction cell, there is a method of setting a cell having the largest delay as a correction cell or a method of correcting a cell having a large delay improvement rate.

Next, the cell exchange means 103
3 is replaced with a cell 233 having a higher driving capability than the cell 203 among cells replaceable with the cell 203 from a predetermined cell library. FIG. 2B shows the circuit after cell replacement.

Here, if the timing violation is not resolved by the cell switching means 103, the buffer insertion means 10
4, immediately after the output pin of cell 233, buffer cell 21
Insert 1. FIG. 2C shows the circuit after the buffer is inserted. The buffer cell 211 to be inserted performs delay calculation with the wiring capacitance and resistance of the newly created wiring 221 set to 0 or a predetermined value, has a driving ability to eliminate timing violation, and selects the buffer cell 211 having the minimum area. .

Then, the cell 233 is stored in the cell 23 from a predetermined cell library so that a timing violation does not occur.
The cell 243 having the smallest area among the cells which can be replaced with the cell 3 is replaced. FIG. 2D shows the circuit after cell replacement.

By preparing buffer cells having a large driving capability in the cell library by the buffer inserting means 104, it is possible to eliminate a timing violation due to insufficient driving capability, and prepare a cell having a large driving capability in a logic cell other than the buffer cell. This has the advantage that the cell library can be reduced in size.

In the layout correcting means 105, the inserted buffer cells are arranged adjacent to the corrected cells. FIG.
FIG. 3A shows a layout before correction, and FIG. 3B shows a layout after correction.

The modified cell 301 in FIG. 3A is the cell 203 in FIG. 2A, and the cells 331 and 311 in FIG.
3, 211.

In contrast to the correction cell 331, the buffer cell 31
1 are arranged adjacent to each other. Since the correction cell 331 and the buffer cell 311 are adjacent to each other, the wiring 321 connecting the correction cell 331 and the buffer cell 311 has a short wiring length. Can be reduced. Alternatively, the wiring capacitance of the wiring 321 can be regarded as 0 because the wiring capacitance is extremely small as compared with the input gate capacitance of the buffer cell 311.

Further, the wiring variation due to the wiring correction is also caused by the cell 3
31 and 311, the fluctuation amount can be reduced. Furthermore, by reducing the area of the cell 331, the vacant area of the arrangement increases, so that the arrangement variation due to the arrangement correction can be reduced.

(Embodiment 2) FIG. 4 is a block diagram showing a configuration of a circuit correction device according to a second embodiment of the present invention.

In FIG. 4, an inverter inserting means 404 is used instead of the buffer inserting means 104 in the circuit correction device of the first embodiment shown in FIG. Description of FIG. 4 is omitted.

Next, the inverter insertion means will be described with reference to FIGS. FIG. 5A shows the circuit after the cell exchange means 403 has been completed.

Here, in the case where the timing violation has not been resolved by the cell exchange means 403,
When there is a cell having the negative logic of and having an area smaller than the correction cell 503, the inverter inserting means 404
The correction cell 503 is replaced with a negative logic cell 512, and the cell 5
An inverter cell 511 is inserted immediately after the twelve output pins.

FIG. 6 shows an example of a predetermined cell library. For example, the cell 503 is stored in the library A shown in FIG.
ND3B. AND3B is a 3-input AND and N
AND3A and NAND3B are 3-input NANDs,
It has negative logic for ND3B. Therefore, the cell 503 has the NA
It can be replaced with ND3A or NAND3B.

As in the first embodiment, the wiring capacity and resistance of the newly formed wiring 521 are set to 0 or a predetermined value, and the negative logic cell 512 and the inverter cell having the minimum area within the range satisfying the timing constraint. Select 511.

FIG. 5B shows a circuit after cell replacement and inverter insertion. Here, the cell 243 in FIG.
D3A, cell 211 is BUFC, cell 203 is AND3
B, the cell 503 in FIG.
It is assumed that 2 is NAND 3A and cell 511 is INVC. Area before timing violation correction is AND3B
= 11. The area after correction according to the first embodiment is AND3A + BUFC = 7 + 10 = 17, and the area after correction according to the second embodiment is NAND3A +
INVC = 5 + 8 = 13, and the area in the second embodiment is smaller than that in the first embodiment, and can be suppressed by 18% as compared with that before correction.

In the layout correcting means 405, as in the first embodiment, the cell 512 is located at the position where the cell 503 is arranged.
Are arranged, and the cells 511 are arranged adjacently.

In a CMOS, generally, an inverter having the same driving capability has a smaller area than a buffer. Therefore, when the area of the correction cell is set to a negative logic and the area is reduced, the free space in the layout is increased, and the circuit variation in the layout correction can be further reduced.

[0033]

As described above, the present invention can be applied to a cell library having a small number of cell types having different driving capabilities.
If there are many types of cells having different driving capabilities of the buffer or the inverter, the timing can be improved.

Since the wiring variation in the layout correction is only in the vicinity of the correction cell, the amount of wiring variation can be reduced, and the difference between the predicted wiring capacitance and resistance at the time of delay improvement can be reduced, thereby reducing the number of repetitions. There is an effect that can be.

Further, since the area of the cell targeted for the delay improvement can be reduced, the wiring variation due to the layout variation in the layout correction can be further reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a circuit correction device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a circuit modification example according to the first embodiment of the present invention;

FIG. 3 is a diagram showing a layout modification example according to the first embodiment of the present invention;

FIG. 4 is a configuration diagram of a circuit correction device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a circuit modification example according to the second embodiment of the present invention;

FIG. 6 is a diagram showing an example of a cell library.

[Explanation of symbols]

 101 Violation path identification means 102 Corrected cell identification means 103 Cell exchange means 104 Buffer insertion means 105 Layout modification means 111 Wiring capacitance / resistance 112 Correction layout 121 Timing violation path 122 Correction cell 123 Correction circuit 401 Violation path identification means 402 Correction cell identification means 403 Cell exchange means 404 Inverter insertion means 405 Layout correction means 411 Wiring capacitance / resistance 412 Corrected layout 421 Timing violation path 422 Corrected cell 423 Correction circuit

Claims (6)

[Claims] An apparatus for correcting a timing violation after layout design, comprising: a violating path specifying unit, a corrected cell specifying unit, a cell exchanging unit, a buffer inserting unit, and a layout correcting unit; Performing a timing analysis based on the wiring capacitance from the layout data to specify a path that violates a predetermined timing constraint; and the correction cell specifying unit specifies a cell whose delay is to be improved from cells in the violating path. The cell exchange means performs delay improvement by changing the driving capability of the cell, and the buffer insertion means inserts a buffer immediately after the cell when the cell exchange means cannot correct the timing constraint violation. Wherein the layout modifying means arranges the buffer adjacent to the cell. Correction device. 2. An apparatus for correcting a timing violation after a layout design, comprising: a violating path specifying unit, a corrected cell specifying unit, a cell exchanging unit, an inverter inserting unit, and a layout correcting unit; Performing a timing analysis based on the wiring capacitance from the layout data to specify a path that violates a predetermined timing constraint; and the correction cell specifying unit specifies a cell whose delay is to be improved from cells in the violating path. The cell exchange means performs a delay improvement by changing the driving capability of the cell, and the inverter insertion means sets the cell to a negative logic when the cell exchange means cannot correct the timing constraint violation. Cell, and an inverter is inserted immediately after the cell to improve the delay. The disposed adjacent to the cell, the circuit adjustment device also. 3. The circuit repair apparatus according to claim 1, wherein said buffer inserting means reduces the area of said cell by setting a wiring capacitance between said cell and said buffer to a predetermined value. 4. The circuit repair apparatus according to claim 2, wherein said inverter inserting means reduces the area of said cell by setting a wiring capacitance between said cell and said inverter to a predetermined value. 5. The circuit correction device according to claim 1, wherein said buffer inserting means sets a wiring capacity between said cell and said buffer to zero. 6. The circuit correction device according to claim 2, wherein said inverter inserting means sets a wiring capacitance between said cell and said inverter to zero.