JP2000183654A - Waveform generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveform generator that can generate smooth sweep waveforms. SOLUTION: This waveform generator 1 is provided with a waveform parameter data memory that stores a plurality of sets of waveform parameter data to generate a unit sweep waveform corresponding to a sweep period for a prescribed time length and an address-generating circuit 12 that generates address data DAP to read the waveform parameter data from the waveform parameter data memory for each updated time with a prescribed time length, where a joint waveform of a plurality of unit sweep waveforms corresponding to a plurality of sweep periods can be generated, on the basis of a plurality of the waveform parameter data, sequentially read from the waveform parameter data memory for each update time. In this case, the update time is individually set by each sweep period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generating apparatus for generating various waveforms such as a sine wave and a rectangular wave, and more particularly, to a method of generating waveform parameters such as the frequency, amplitude and offset voltage of a generated waveform over time. The present invention relates to a waveform generation device having a sweep function that changes in response to a change.

[0002]

2. Description of the Related Art In order to inspect characteristics of an ABS sensor, a motor, and the like, a sweep waveform whose frequency, amplitude, and the like sequentially changes in accordance with set waveform parameter data in a set sweep period may be required. As a waveform generating apparatus used at the time of this type of characteristic inspection or the like, a waveform generating apparatus 71 shown in FIG. 6 is conventionally known. The waveform generation device 71 is configured to generate, for example, an analog output signal So having a sweep waveform shown in FIG. Specifically, the waveform generation device 71 includes a CPU
72, a RAM 73 for temporarily storing various data and calculation results of the CPU 72, a reference clock generation unit 74 for generating a 1 μS reference clock SKR, and an address generation circuit for generating address data DA for reading out frequency data Df. 75, a frequency data memory 21 for storing frequency data Df, a DDS 24 for generating a sine wave analog signal SA based on the frequency data Df, and an LP for generating an analog output signal SO by removing unnecessary frequency components.
F31, a connector 18 for outputting an analog output signal So, and a display unit 78 are provided. The address generation circuit 75 includes a programmable counter 76 and an address counter 77.

In the waveform generating apparatus 71, when a sweep sequence, which is the order of generation of a desired sweep waveform, is designated, first, an operation unit (not shown) is operated, whereby a waveform shown in FIG.
The screen 81 for sweep sequence input shown in FIG.
To be displayed. Next, on the sweep sequence input screen 81, a sweep sequence is designated using a mouse. Specifically, first, the update time of the frequency data Df is set in the update time setting display section 82 on the sweep sequence input screen 81. In this case, the update time is the time during which the address data DA is updated by the address generation circuit 75, that is, the frequency data memory 21.
Means the output cycle of the frequency data Df output by Therefore, it is set to a short time to some extent so that the analog output signal SO changes smoothly at a step frequency of a small step. At this time, the update time is set to 1 ms.
It is assumed to be set to

Next, a sweep sequence input screen 8
In the first 0 row at 1, the start frequency of the sweep waveform in the first sweep period T1 (10 MHz in this example)
z), and then, in the second row, the end frequency of the sweep waveform in the first sweep period T1 (the start frequency of the sweep waveform in the second sweep period T2, which is 1 MHz in this example). Next, the operator operates the frequency data D in the first sweep period T1.
The update count and sweep time of f are set in the middle and right columns of the first row, respectively. In this case, the update count is a value (1000 times in this example) obtained by dividing the sweep time (1S) by the preset update time (1 mS).

At this time, the first sweep sequence condition is determined. At this time, the CPU 72 causes the RAM 73 to store the update count data and the update time data in the first sweep period T1. At the same time, the CPU 72
Generates frequency data Df for each update based on the start frequency, the end frequency, and the number of updates, and stores the frequency data Df in the frequency data memory 21. Similarly, a sweep sequence condition for the second sweep period T2 is input. At this time, the CPU 72 also stores the update count data in RA
M73 and frequency data D for each update.
f is generated and stored in the frequency data memory 21. Similarly, the respective sweep sequence conditions for the third sweep period T3 and the fourth sweep period T4 are input. Thus, the update time data and the update count data in the first to fourth sweep sequences are stored in the RAM 7.
3 and the frequency data Df in the first to fourth sweep sequences are stored in the frequency data memory 2.
1 is stored.

When the sweep sequence condition of the fourth sweep period T4 is input, the sweep period and the number of updates of the entire sweep sequence are 8S and 8000, respectively. In this case, the frequency data memory 21 has a storage capacity of 32 Kbytes, and one frequency data Df is composed of 4 bytes.
K data can be stored. Therefore, at this time, the remaining storage capacity of the frequency data memory 21 is exhausted, and further input of the sweep sequence condition is prohibited.

At this time, when the input of the sweep sequence condition is prohibited in a state where the sweep sequence condition for all desired sweep periods is not set, the operator operates so that the frequency data Df falls within 8K data. The update time on the update time setting display unit 82 is changed to a longer time. Next, after clearing the preset sweep sequence conditions, the sweep sequence conditions for all sweep periods are reset.
As a result, the number of updates is reduced, so that sweep sequence conditions for all desired sweep periods can be set.

On the other hand, when the sweep sequence is executed, C
The PU 72 first reads out the update time data DR1 from the RAM 73 and outputs it to the programmable counter 76, and outputs the update count data DRD1 in the first sweep period T1 to the address counter 77. Next, the programmable counter 76 counts the number of inputs of the reference clock SKR, and every time the count value reaches 1000 times (that is, every time it reaches 1 mS), the update clock signal SKR is used.
DR1 is output to the address counter 77. Next, the address counter 77 sequentially outputs the address data DA in synchronization with the update clock signal SDR1. As a result, the frequency data Df stored at the address of the address data DA is sequentially output from the frequency data memory 21, and the DDS 24 generates an analog signal SA having a frequency corresponding to each frequency data Df. As a result, LPF 31
Output an analog output signal So having a sweep waveform.

As a result, as shown in FIG. 5, an analog output signal SO of 10 MHz is output at the start time t0 of the first sweep period T1, and thereafter, the frequency monotonously decreases every update time, and the first sweep is performed. End time t1 of period T1
Outputs an analog output signal So of 1 MHz.
Similarly, in the second sweep period T2 to the fourth sweep period T4, the analog output signal SO having a frequency according to the set sweep sequence condition is output.

[0010]

However, the conventional waveform generator 71 has the following problems. First, in the conventional waveform generation device 71, when the update time is set on the update time setting display unit 82, the update times for all sweep periods are set uniformly at the same time. Problem. That is, the sweep waveform corresponding to a long (for example, 3S) sweep period and the sweep waveform corresponding to a short (for example, 100 mS) sweep period are updated at the same update time. Therefore, a sweep waveform having a short sweep period is represented by frequency data D
As a result of the decrease in the total number of data of f, a rough waveform that does not sweep smoothly is obtained. For this reason, the conventional waveform generation device 7
No. 1 has a problem that the smoothness of the sweep waveform may be reduced depending on the setting conditions of the sweep sequence.

Second, in the conventional waveform generator 71, the total number of frequency data Df is stored in the frequency data memory 21.
It is necessary for the operator to set the sweep sequence conditions while checking the memory so as not to exceed the memory capacity. In this case, in order to completely set all the necessary sweep sequence conditions, prior to setting the sweep sequence conditions, the operator first determines the update time and determines the update time based on the predicted update time. Calculation of the total number of frequency data Df must be performed. For this reason, the conventional waveform generation device 71 has a problem that the setting of the sweep sequence condition is complicated and difficult.

The present invention has been made in view of the above problems, and has as its main object to provide a waveform generating apparatus capable of generating a smooth sweep waveform, in which a sweep sequence condition can be set easily and in a short time. It is a main object to provide a simple waveform generation device.

[0013]

According to a first aspect of the present invention, there is provided a waveform generating apparatus comprising: a plurality of sets of a plurality of sets of waveform parameter data for generating a unit sweep waveform corresponding to a sweep period having a predetermined time length; A waveform parameter data memory that can be stored, and an address generation circuit that generates address data for reading the waveform parameter data from the waveform parameter data memory at every update time of a predetermined time length. Based on a plurality of sequentially read waveform parameter data, a waveform generation device configured to generate a connected waveform of a plurality of unit sweep waveforms respectively corresponding to a plurality of sweep periods, the update time is individually set for each sweep period. It is characterized in that it is configured to be able to be set.

In this waveform generation device, the update time of the address data generated by the address generation circuit, in other words, the update time for reading the waveform parameter data from the waveform parameter data memory is individually set for each sweep period. Is done. Therefore, set the update time of the short sweep sweep period to a short time,
The update time of a long sweep period can be set to a long time. With this setting, the sweep waveform for a short sweep period is
A smooth sweep waveform is obtained, and a sweep waveform for a long sweep period is a sufficiently smooth sweep waveform. In addition, the number of waveform parameter data for a short sweep period does not increase so much, and the number of waveform parameter data for a long sweep period decreases. Therefore, since the total number of waveform parameter data can be reduced, the capacity of the waveform parameter data memory can be reduced. Conversely, if the capacity of the waveform parameter data memory is made the same as that of the frequency data memory 21 in the conventional waveform generation device 71, the total number of storable waveform parameter data can be increased.

According to a second aspect of the present invention, there is provided a waveform generating apparatus according to the first aspect.
In the waveform generating apparatus described above, a sequence memory for storing the number of updates of address data in a sweep period and an update time for each sweep period, and an address memory for updating address data based on the update time stored in the sequence memory A clock signal generation circuit that generates an update clock signal, wherein the address generation circuit generates address data based on the number of updates of the address data and the number of inputs of the update clock signal.

In this waveform generation device, when the sweep sequence condition is set, the sequence memory stores the number of updates of the address data and the update time in the sweep period for each sweep period. On the other hand, when the sweep sequence is executed, the clock signal generation circuit generates an update clock signal for updating address data based on the update time stored in the sequence memory, and the address generation circuit determines the number of updates of the address data and the number of updates. Address data is generated based on the number of input clock signals. Therefore, the execution of the sweep sequence is managed by the sequence data including the number of updates and the update time of the address data stored in the sequence memory, and is processed by hardware. For this reason, the sweep sequence can be processed in an extremely short time as compared with the case of processing using software.

According to a third aspect of the present invention, there is provided a waveform generating apparatus.
In the described waveform generation device, the sequence memory stores the number of repeated generations of the unit sweep waveform, and the address generation circuit stores the address data for the unit sweep waveform in the sequence memory when the unit sweep waveform is repeatedly generated. It is characterized in that it is repeatedly generated according to the number of repeated generations.

In this waveform generation device, the address generation circuit repeatedly generates the sweep waveform in accordance with the number of repetitions of the unit sweep waveform stored in the sequence memory. Therefore, it is not necessary to store waveform parameter data for the same sweep waveform in the waveform parameter data memory redundantly, so that the total number of waveform parameter data can be reduced and the memory space can be effectively used. Becomes

According to a fourth aspect of the present invention, there is provided a waveform generating apparatus according to the first aspect.
3. The waveform generation device according to any one of items 1 to 3, further comprising an update time determination unit that determines an update time according to a predetermined rule when a predetermined time length corresponding to each of the plurality of sweep periods is set. It is characterized by.

In this waveform generator, when the sweep period is set by the operator, the update time is automatically determined according to a predetermined rule. In this case, it is desirable that the update time of the short sweep period be determined to be short, and the update time of the long sweep period be determined to be long. In addition, since the update time is automatically determined, the number of updates can be automatically calculated.
As described above, the update time is automatically determined, and the update count is automatically calculated, thereby avoiding complicated and difficult update time calculation work and update time calculation work.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a waveform generator according to the present invention will be described below with reference to the accompanying drawings.

The waveform generating apparatus 1 has a waveform generating function for generating a standard waveform such as a sine wave or a rectangular wave and an arbitrary waveform, and a sweep sequence function for simultaneously sweeping waveform parameters including the frequency, amplitude and offset voltage of the waveform. It is configured to be feasible. More specifically, as shown in FIG. 1, the waveform generation device 1 includes a CPU 2, a display input unit 3, an operation unit 4, a floppy disk drive 5, an RO
An M6, a RAM 7, a reference clock generator 8, and an output unit 9 are provided.

The CPU 2 corresponds to an update time determination unit in the present invention, determines an update time as described later, and controls each unit according to a waveform generation command and a sweep sequence condition set in the display input unit 3 or the operation unit 4. Controls the operation of each circuit. The display input unit 3 includes, but is not limited to, an LCD panel on which a touch panel is provided, and displays a sweep sequence condition input screen 41 (see FIG. 4) and the like on the LCD panel in a table format. Operation unit 4
Is provided with various switches, a shuttle dial, and the like, and is configured to be capable of various settings relating to waveform generation. The floppy disk drive 5 is configured to be able to write and read various data for generating a waveform to and from a floppy disk. The ROM 6 stores an operation program of the CPU 2. In addition, the RAM 7 temporarily stores the calculation results of the CPU 2, various data for generating a waveform described later, start address data DS and end address data DE of the arbitrary waveform data memory 29, and the like.

As shown in FIG. 1, the output unit 9 includes a programmable counter 11 corresponding to a clock signal generation circuit according to the present invention, an address counter 12 corresponding to an address generation circuit according to the present invention, a waveform generation unit 13, and a sequence circuit 14. And a connector 18 for outputting an analog output signal So, and generates a predetermined waveform in accordance with various data for waveform generation output from the CPU 2. The sequence circuit 14 includes a sequence counter 15, a sequence memory 16, and a loop counter 17.

The programmable counter 11 supplies the address counter 12 with the address data D based on the update time data DR output from the sequence memory 16.
An update clock signal SDR for updating the AP is generated. Specifically, for example, when a sweep sequence condition for sweeping one waveform in a sweep period of 3 seconds is set, when the CPU 2 determines the number of updates to be 1000, the CPU 2 calculates the sweep period of 3 seconds by dividing 1000. Thereby, the update time is specified as 3 mS, and the update time data DR is stored in the sequence memory 16. In this case, each time the number of inputs of the 1 μS reference clock SKR output from the reference clock generator 8 reaches 3000, the programmable counter 11 updates the update clock signal SDR.
Generate The cycle of the update clock signal SDR is
As described later, 1 μS within the range of 1 μS to 65.5 mS
Determined in S increments. Further, in the present specification, the address data DAP refers to the frequency data Df, the amplitude data D
a and address data for reading the offset voltage data DO.

The address counter 12 generates address data DAP by sequentially incrementing the address value in synchronization with the update clock signal SDR output from the programmable counter 11. The waveform generation unit 13
The configuration of the address counter 12 will be described later.
A standard waveform and an arbitrary waveform are generated in accordance with the address data DAP output from.

The sequence circuit 14 controls connection and looping of a plurality of waveforms. The sequence memory 16 in the sequence circuit 14 stores sweep sequence data DSP conditionally set on a sweep sequence input screen 41 displayed on the LCD panel of the display input unit 3, and the sweep sequence data DSP stores the sweep sequence data DSP. Is written by the CPU 2 prior to the execution. The sequence counter 15 outputs the address data DRA in accordance with the carry signal SC output from the loop counter 17, and outputs the update count data D
RD is output to the address counter 12. The loop counter 17 stores the loop data DRP output from the sequence memory 16, counts the number of times the carry signal SC is output from the address counter 12, and sweeps the output signal so that the number of outputs becomes equal to the value of the loop data DRP. Controls the number of repeated sweeps of the same waveform during sequence execution.

In the sequence circuit 14, for example, a sweep time of 3 seconds, an update count of 1000 times and a loop count of 2 are set as the sweep sequence condition 1, and as the sweep sequence condition 2, a sweep time of 5 seconds and an update count of 1000 times. And when the number of loops is set to 1, the CPU 2 first sets the sweep sequence data DSP
Is output, the first sweep sequence data (3 m, 1000, 2) and the second sweep sequence data (5 m, 1000, 1) are stored in the sequence memory 16.
, For example, are sequentially written to addresses 001 and 002. Next, the sequence counter 15 outputs the address data DRA corresponding to the address 001 to the sequence memory 16. As a result, the sequence memory 16 stores the update time data DR (3m
S), the update count data DRD (1000 times) and the loop data DRP (2 times) are stored in the programmable counter 11,
Output to the address counter 12 and the loop counter 17, respectively.

Next, the programmable counter 11
An update clock signal SDR is output to the address counter 12 every 3 ms when the number of input clocks of the reference clock SKR reaches 3000. On the other hand, the address counter 12
The output processing of the address data DAP to the waveform generator 13 is executed. In this processing, the address counter 12
Each time the update clock signal SDR is input, the address data DAP is output to the waveform generator 13 while being incremented. Thereafter, the address counter 12 outputs the carry signal SC to the loop counter 17 and resets the address data DAP to an initial value when the number of input clocks of the update clock signal SDR reaches the number of updates of 1000 times. Thereafter, the address counter 12 restarts the counting operation, and the number of input clocks of the update clock signal SDR becomes 1
When the number of times reaches 000, the carry signal SC is output to the loop counter 17. As a result, the address data DAP
Is performed twice.

On the other hand, when the carry counter SC is output from the address counter 12 a number of times specified by the loop data DRP, the loop counter 17 carries the carry signal SC.
Is output to the sequence counter 15. As a result, the sequence counter 15 increments the address data DRA and outputs it to the sequence memory 16. As a result, the sequence memory 16 stores the update time data DR (5 ms), the update count data DRD (1000 times), and the loop data DRP (1) stored at the next address 002.
Is output to the programmable counter 11, the address counter 12, and the loop counter 17, respectively.
At this time, the output unit 9 sets the sweep sequence condition 1
The output process of the address data DAP to the waveform generating unit 13 is executed only once in the same manner as the sweep sequence of FIG. As a result, the waveform generator 13 of the output unit 9 sequentially generates sweep waveforms according to the set sweep sequence conditions 1 and 2.

As shown in FIG. 2, the waveform generator 13 includes a frequency data memory 21, an amplitude data memory 22, an offset data memory 23, a DDS 24, an LPF 25, and a TT
L conversion circuit 26, level conversion circuit 27, arbitrary waveform address generation circuit 28, arbitrary waveform data memory 29, D / A
Conversion circuit 30, LPF 31, D / A conversion circuits 32, 3
3, a signal switch 34, a multiplier 35, an adder 36, and a buffer amplifier 37.

The frequency data memory 21 has a storage capacity capable of storing, for example, 64K sine wave frequency data Df generated by the DDS 24 at the time of executing a sweep sequence or the like. Specifically, when the sweep sequence condition is set on the sweep sequence input screen 41, the CPU 2 outputs the waveform parameter data DP corresponding to the sweep sequence data DSP, and at that time, the frequency data memory 21 The frequency data Df of the waveform parameter data DP is stored. In addition,
The frequency data Df is, for example, 10 mHz resolution.
The range from mHz to 10 MHz is specified so that it can be specified.

The amplitude data memory 22 stores amplitude data Da of the amplitude value of the generated waveform among the waveform parameter data DP output from the CPU 2. Further, the offset data memory 23 stores the offset voltage data DO regarding the DC offset voltage of the generated waveform among the waveform parameter data DP output from the CPU 2. Note that the frequency data memory 21, the amplitude data memory 22, and the offset data memory 23 correspond to a waveform parameter data memory in the present invention. DDS2
4 generates a sine wave or a sweep waveform WS having a frequency corresponding to the frequency data Df output from the frequency data memory 21 by digital processing. LPF25 is DDS24
Filter the sinusoidal signal generated by. The TTL conversion circuit 26 converts the sine wave output from the LPF 25 into a TTL
By converting the clock into a level, a rectangular clock reference clock signal CK is generated. In addition, the level conversion circuit 27
By level-converting the signal level of the rectangular wave output from the conversion circuit 26, for example, pattern data of a ± 10V rectangular wave is generated.

The arbitrary waveform address generation circuit 28 is provided with a TT
By incrementing the address value in synchronization with the reference clock signal CK output from the L conversion circuit 26,
The address data DA for reading the waveform data DW from the arbitrary waveform data memory 29 is generated. The arbitrary waveform data memory 29 is configured so that the user can freely write the waveform data DW for the arbitrary waveform. For example, when the floppy disk storing the waveform data DW is inserted into the floppy disk drive 5, CP
The waveform data DW transferred by U2 is stored. D
The / A conversion circuit 30 generates an analog signal SA by digital-to-analog conversion of the waveform data DW output from the arbitrary waveform data memory 29. LPF31
Is constituted by a secondary low-pass filter of a variable cutoff frequency type, and functions as a smoothing filter by removing the signal components and noise components of the reference clock signal CK contained in the input analog signal SA. D /
The A conversion circuit 32 outputs to the multiplier 35 an analog voltage signal generated by digital-to-analog conversion of the amplitude data Da output from the amplitude data memory 22, and the D / A conversion circuit 33 outputs the analog voltage signal to the offset data memory 2.
An offset voltage signal generated by performing a digital-to-analog conversion of the offset voltage data DO output from 3 is output to the adder 36.

In the waveform generator 13, for example, when generating the sweep waveform WS, the frequency data memory 21, the amplitude data memory 22 and the offset data memory 23 follow the address data DAP output from the address counter 12. Frequency data Df, amplitude data Da
And offset voltage data DO.
As a result, the DDS 24 generates a sweep waveform WS having a frequency corresponding to the frequency data Df, and the signal switch 3
4 to output a sweep waveform WS to the multiplier 35.
At the same time, the analog voltage signal output from the D / A conversion circuit 32 is output to the multiplier 35, which controls the amplitude value of the sweep waveform WS by multiplying the sweep waveform WS and the analog voltage signal by each other. I do. Also, D
The offset voltage signal output from the A / A conversion circuit 33 is output to the adder 36, and the adder 36 adds the offset voltage signal to the sweep waveform WS output from the multiplier 35 to generate a sweep waveform analog output signal. SO
Generate Next, the buffer amplifier 37 buffers and amplifies the analog output signal So and outputs it to the connector 18.

On the other hand, when generating the arbitrary waveform, the frequency data memory 21 outputs the frequency data Df in accordance with the address data DAP output from the address counter 12, so that the DDS 24 generates a sine wave of a predetermined frequency. . Next, the TTL conversion circuit 26 converts the sine wave to the TTL level to thereby generate the reference clock signal C.
K is generated and output to the arbitrary waveform address generation circuit 28. At the same time, the CPU 2 outputs the start address data DS and the end address data DE to the arbitrary waveform address generation circuit 28, and the arbitrary waveform address generation circuit 28 outputs these input data and the reference clock signal CK. Based on the address data DA, the address data DA is generated and output to the arbitrary waveform data memory 29. As a result, the arbitrary waveform data memory 29 sequentially outputs the waveform data DW corresponding to the address data DA, and the D / A conversion circuit 30
An analog signal SA having an arbitrary waveform is generated by digital-to-analog conversion of the waveform data DW. In this case, the analog signal SA is input to the multiplier 35 via the LPF 31 and the signal switch 34, is multiplied by a constant 1 by the multiplier 35, and the offset voltage signal of value 0 is added by the adder 36. Thereafter, the signal is buffer-amplified by the buffer amplifier 37 and output to the connector 18 as an analog output signal SO.

Next, a method of setting conditions for executing a sweep sequence and the overall operation of the waveform generating apparatus 1 will be described mainly with reference to FIGS. Note that
A process of determining an update time for frequency data Df in a sweep sequence in which only a frequency is swept, and a process of calculating the number of data will be described as a representative.

First, on the sweep sequence input screen 41 shown in FIG. 4, the sweep time (1S) of the first sweep period, the start frequency (10 MHz),
When the end frequency (1 MHz) and the number of loops (two times) are set, the CPU 2 executes the data creation processing shown in FIG. In this process, the CPU 2 determines the update time according to the set time for the sweep time. Specifically, the CPU 2 first sets the sweep time to be less than 1 ms, 1 ms to 6.5536 S, and 6.
It is determined which of these is equal to or greater than 5537S (step 51). Next, when less than 1 ms, the CPU 2
When the update time is determined to be 1 μS (step 52),
The number of frequency data Df is calculated. In this case, C
PU2 obtains the number of data by dividing the sweep time by the update time. Also, the set time is 1 ms to 6 ms.
At the time of 5536S, the CPU 2 sets the set time to 100
The time is determined by dividing by 0 (step 53), and the number of data at that time is calculated. Further, when it is equal to or greater than 6.5537 S, the CPU 2 determines 65536 μS (step 54) and calculates the number of data at that time. Also, CPU
In step 53, when the determined update time is longer than (6.5537 / 2) S, the value 1 is written to the flag corresponding to the 001 line.

In the same manner as described above, after the processing for all the rows (rows 001 to 003 in this example) has been performed, and when the enter button 42 is further operated, the CPU 2 executes the calculation for all the rows. Is completed (step 55), and the total number of frequency data Df becomes 6
It is determined whether it is within 4K data (step 56). In this example, since the data is within 64K data, the CPU 2
This data creation processing is normally terminated (step 57).
Thereafter, the CPU 2 sets the lines 001 to 003 as the first to third sweep sequence conditions, respectively, and sets each of the sweep sequence data DSP (update time,
The number of updates and the number of loops) are transferred to the sequence memory 16 and stored.

On the other hand, if the total number of data exceeds 64K data, it is determined whether or not the number of data in all rows cannot be divided (step 58). In this case, dividing the number of data
This means that the number of data is halved by dividing the determined number of data in each row by the value 2. Lines that can be divided are limited to lines in which the value 1 is not written to the flag in step 53 and lines in which the number of data after division is, for example, 10 or more. As a result, by limiting the rows that can be divided, it is possible to prevent a reduction in the number of data in each sweep period, that is, a reduction in the smoothness of the sweep waveform. When the flag 1 is written in all the rows, the CPU 2 determines that the total number of data exceeds 64K data, displays that fact on the display input unit 3, and terminates the data creation processing in error (step 59).

When it is determined that there is a row that can be divided (step 60), the CPU 2 determines the update time corresponding to the row to be twice as long as the update time, and then adds a half of the preset number of data. (Step 61). Thereafter, the CPU 2 updates the flag (step 6).
2) In this process, the newly determined update time is (6.
5537/2) If the time is longer than S, the value 1 is written to the flag corresponding to the row. Then, CPU
2 determines whether or not the calculation of all the rows for the update time and the number of data has been completed (step 63), and if there is a row that can be divided, steps 60 to 63 are further repeated to execute When it is determined that the calculation has been completed, it is determined again whether or not the total number of data is 64K data (step 56). Thereafter, steps 56 to 6 described above are performed.
By repeating Step 3, the data creation processing is normally terminated (Step 57) or terminated with an error (Step 5).
9) At the time of normal termination, each sweep sequence data DSP (update time, number of updates, number of loops) corresponding to each row is transferred to the sequence memory 16 and stored.

Next, when the data creation process is completed normally and a sweep sequence start switch (not shown) on the operation unit 4 is operated, the CPU 2
To execute a sweep sequence. At this time, the address counter 12 outputs the address data DAP to the waveform generator 13 according to the sweep sequence data DSP stored in the sequence memory 16. As a result, the DDS 24 of the output unit 9 outputs the address data D
A sweep waveform WS is generated according to the frequency data Df output from the frequency data memory 21 according to the AP. Next, the sweep waveform WS is converted to the LPF 25 and the signal switch 3.
4 and to the adder 36 via the multiplier 35, and the adder 36 outputs an analog output signal So having a sweep waveform. Next, the amplifier 37 outputs the analog output signal So.
Is output to the connector 18 after buffer amplification.

The present invention is not limited to the above embodiment. For example, in the embodiment of the present invention, an example has been described in which three groups of update times (steps 52 to 54) are used in the data creation processing. The time length is not limited to the time shown in the embodiment of the present invention, and can be appropriately changed. Further, the division of the number of data is not limited to the division into two, and it is possible to divide by the number of values of 1 or more.

Further, with respect to the configuration of the sequence circuit 14 and the output section 9, a part of the functions can be shared by the CPU 2, or can be configured by a DSP or the like.

[0045]

As described above, according to the waveform generating apparatus of the first aspect, the updating time of the address data generated by the address generating circuit can be set individually for each sweep period. In addition, a sweep waveform that smoothly sweeps in accordance with the set sweep sequence condition (particularly, sweep time) can be generated. Further, since the total number of waveform parameter data can be reduced, the capacity of the waveform parameter data memory can be reduced. As a result, the cost of the apparatus can be reduced, and the capacity of the waveform parameter data memory can be reduced by the conventional waveform generation. When the same as the frequency data memory 21 in the device 71, the total number of storable waveform parameter data can be increased.

According to the second aspect of the present invention, the address generation circuit generates the address data based on the number of updates of the address data stored in the sequence memory and the number of inputs of the update clock signal. Thus, as a result of the sweep sequence being processed in a hardware manner, the sweep sequence can be processed in an extremely short time as compared with a case in which the sweep sequence is processed in a software manner.

Further, according to the third aspect of the present invention, the address data for the unit sweep waveform is repeatedly generated in accordance with the number of repetition generations stored in the sequence memory, thereby providing the same waveform data for the waveform parameter data memory. Since the overlapping storage of the waveform parameter data for the sweep waveform can be prevented, the total number of waveform parameter data can be reduced, and the memory space can be effectively used.

According to the fourth aspect of the present invention, the update time determination unit automatically determines the update time according to a predetermined rule, so that the operator can perform complicated and difficult update time prediction work. Since the calculation of the number of updates and the number of updates can be avoided, the sweep sequence conditions can be set easily and in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a waveform generation device 1 according to an embodiment of the present invention.

FIG. 2 is a block diagram of a waveform generation unit 13 in the waveform generation device 1.

FIG. 3 is a flowchart of a data creation process in the waveform generation device 1.

FIG. 4 is a screen diagram of a sweep sequence input screen 41.

FIG. 5 is a signal waveform diagram of an analog output signal So which is a sweep waveform.

FIG. 6 is a block diagram of a conventional waveform generation device 71.

FIG. 7 is a screen diagram of a sweep sequence input screen 81 in the conventional waveform generation device 71.

[Explanation of symbols]

 Reference Signs List 1 waveform generating device 2 CPU 9 output unit 11 programmable counter 12 address counter 13 waveform generating unit 14 sequence circuit 15 sequence counter 16 sequence memory 17 loop counter 21 frequency data memory 22 amplitude data memory 23 offset data memory 24 DDS Da amplitude data DAP address Data Df Frequency data DO Offset voltage data DP Waveform parameter data

Claims (4)

[Claims] 1. A waveform parameter data memory capable of storing a plurality of sets of a plurality of sets of waveform parameter data for generating a unit sweep waveform corresponding to a sweep period having a predetermined time length, and updating the waveform parameter data by an update time having a predetermined time length. An address generation circuit for generating address data for reading from the waveform parameter data memory for each update time, based on the plurality of waveform parameter data sequentially read out from the waveform parameter data memory for each update time. In a waveform generation device configured to be able to generate a connected waveform of the plurality of unit sweep waveforms respectively corresponding to a sweep period, the update time may be individually set for each of the sweep periods. Characteristic waveform generator. 2. A sequence memory for storing the number of updates of the address data in the sweep period and the update time for each sweep period, and the address data based on the update time stored in the sequence memory. And a clock signal generation circuit that generates an update clock signal for updating the address data, wherein the address generation circuit generates the address data based on the number of updates of the address data and the number of inputs of the update clock signal. The waveform generation device according to claim 1, wherein: 3. The method according to claim 1, wherein the sequence memory stores a number of times the unit sweep waveform is repeatedly generated, and wherein the address generation circuit generates the unit sweep waveform repeatedly when the unit sweep waveform is repeatedly generated.
3. The waveform generation device according to claim 2, wherein the address data for the unit sweep waveform is repeatedly generated according to the number of repetition generations stored in the sequence memory. 4. An update time determining unit that determines the update time according to a predetermined rule when the predetermined time length corresponding to each of the plurality of sweep periods is set. Item 4. The waveform generation device according to any one of Items 1 to 3.