JP2000181859A - Data writing system from asynchronous data bus to register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the competition between data write to a master registration and data transfer from the master register to a slave register and to prevent a malfunction. SOLUTION: Data from an asynchronous data bus 4 is written to a master register 1 according to the fall of a write signal S2 given as asynchronous with a timer clock S1. On the other hand, data written to the register 1 at every rise of a load signal S8 that is given while synchronized with the clock S1 is transferred to a slave register 2. In such a case, the load signal S8 is prohibited from being generated for the period of the signal S2 from rise to fall and for a prescribed period from the fall.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for writing data from an asynchronous data bus to a register having a two-stage configuration of a master register and a slave register.

[0002]

2. Description of the Related Art When data is written from an asynchronous data bus to a register, the rate of change from the logic "1" level to the logic "0" level and the rate of change from the logic "0" level to the logic "1" level are different. May be different. If data is written to the register at the very end of the comparison timing using a compare register of a timer or the like, data that is different from the data to be written for a moment may be loaded into the register, causing a malfunction such as an incorrect match signal being generated.

Conventionally, in order to avoid such a situation, as shown in FIG. 4, a register has a two-stage configuration of a master register (master compare register) 1 and a slave register (slave compare register) 2, and a register to be compared is provided. The data from the asynchronous data bus 4 is written to the master register 1 at the falling edge of the write signal S2 which is asynchronous with the timer clock (synchronized with the timer internal operation clock) S1 to the timer 3, while being synchronized with the timer clock S1. The method of transferring the data determined in the master register 1 to the slave register 2 is adopted.

That is, the logic circuits 6-1, 6-2, 6-
3 and a timing control signal generation circuit 6 composed of an AND circuit 6-4, and after the fall of the write signal S2 (point t1 shown in FIG.
Is written into the master register 1 and then synchronized with the rise of the timer clock S1 (FIG. 5 (b)
(Point t2 shown in FIG. 5), and generates a timing control signal S3 having a logic "1" level and a clock width (FIG. 5 (f)). When the timing control signal S3 is at the logic "1" level,
In synchronization with the rise of the timer clock S1 (FIG. 5)
(T3 point shown in (b)), the data is transferred from the master register 1 to the slave register 2. The logic circuit 6-1
Is reset by the fall of the timing control signal S3. Further, the comparator 5 stores the data of the timer 3 counting the timer clock S1 and the slave register 2
And a match signal S0 is generated when they match.

[0005]

[0006] However, in the method shown in FIG. 4, as indicated by the timing A in FIG. 5, ₁ two write signals S2, S2 ₂ is given in succession, the second write signal S2 ₂ of the fall and the timer clock S
When a conflict occurs with the rising edge of the _first write signal S2, data m (write data by the _first write signal S21) and data n (the second write signal S2) are stored in the slave register 2.
₂ ) cannot be specified.

Further, as another conventional technique, there is a technique in which a coincidence interrupt signal during register rewriting is masked by a mask signal without using a master / slave configuration. In this case, since the coincidence interrupt signal itself during the rewriting of the register is masked, there is a problem that the necessary coincidence interrupt signal is masked even if a necessary coincidence interrupt signal is generated while the same data is being rewritten for noise removal.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. It is an object of the present invention to prohibit the transfer of data to a slave register and thereby to write data to the master register. It is an object of the present invention to provide a method for writing data from an asynchronous data bus to a register, which can eliminate contention for data transfer from the slave to a slave register and prevent malfunction.

[0008]

In order to achieve such an object, a first invention (an invention according to claim 1) provides an asynchronous data bus at a falling edge of a write signal provided asynchronously with an internal operation clock. The data written in the master register is transferred to the slave register at every rising edge of the load signal applied in synchronization with the internal operation clock. The generation of the load signal is prohibited for a predetermined period until the writing is completed. According to the invention,
After a predetermined period from the fall of the write signal to at least the completion of data writing, a load signal is not generated until the next internal operation clock is generated, and data is not transferred from the master register to the slave register. .

The second invention (the invention according to claim 2) writes data from an asynchronous data bus into a master register at the falling edge of a write signal given asynchronously with the internal operation clock, while synchronizing with the internal operation clock. The data written in the master register is transferred to the slave register at each rising edge of the load signal given in the period, and a period from the rising edge to the falling edge of the write signal and a predetermined period from the falling edge to at least data writing is completed. , The generation of the load signal is prohibited. According to the present invention, the load signal is not generated until the next internal operation clock is generated after a predetermined period from the fall of the write signal to at least the completion of data writing, and the data from the master register to the slave register is not generated. Is not transferred. For example, when two write signals are successively applied, a period from a rise to a fall of the first write signal and a period after a predetermined period from the fall until a next internal operation clock is generated; During the period from the rise to the fall of the second write signal and the period after a predetermined period from the fall until the next internal operation clock is generated, no load signal is generated and data is transferred from the master register to the slave register. Is not done.

Here, the generation interval between the first write signal and the second write signal is short, and the non-generation period of the load signal when the first write signal is applied and the second write signal are applied. If the load signal non-occurrence period partially overlaps, the period from the rise of the first write signal to the fall of the second write signal and the predetermined period from the fall of the second write signal After a period, a load signal is not generated until the next internal operation clock is generated, and data written to the master register by the first write signal is not transferred to the slave register. Data written to the register is transferred to the slave register.

A third invention (an invention according to claim 3) is to write data from an asynchronous data bus to a master register at the falling edge of a write signal given asynchronously with the internal operation clock, and to write data every time the load signal rises. This is a method for writing data to a register from an asynchronous data bus that transfers data written to a master register to a slave register, and a logic "1" is used during a period from a rise to a fall of a write signal and a predetermined period from a fall. As a level, a mask signal generating means for generating a mask signal as a logic "0" level in other periods, and a mask signal from the mask signal generating means as an input, and the mask signal is at a logic "1" level Selects and outputs the output signal from the selection signal capturing means, and outputs a logic "0" level. In some cases, a signal selecting means for selecting and outputting an inverted signal of an output signal from the selection signal taking means, and a selecting signal for taking a selected output from the signal selecting means in synchronization with an internal operation clock and setting it as an output signal Capture means, delay means for delaying the output signal from the selection signal capture means for a predetermined time and outputting as a delay signal, and exclusive control of the delay signal from the delay means and the output signal from the selection signal capture means. Exclusive OR means for taking a logical sum and using it as a load signal is provided.

According to the present invention, the mask signal is at the logical "1" level during the period from the rise to the fall of the write signal and for a predetermined period from the fall, and is at the logical "0" level during the other periods. . This mask signal is provided to the signal selection means. The signal selection means selects and outputs an inverted signal of the output signal from the selection signal acquisition means when the mask signal is at the logic "0" level, and outputs the inverted signal when the mask signal is at the logic "1" level. An output signal from the selection signal capturing means is selected and output. The selection signal fetching means fetches the selected output from the signal selection means in synchronization with the internal operation clock, and sets it as an output signal. This allows
When the mask signal is at the logic "0" level, the output signal from the selection signal taking means is inverted in synchronization with the internal operation clock, and when the mask signal is at the logic "1" level, the selection signal is taken. The output signal from the means is not inverted. An output signal from the selection signal capturing means is delayed by a predetermined time to be a delayed signal. The exclusive OR of this delay signal and the output signal from the selection signal taking means is taken as a load signal.

The load signal is set to a logic "1" level each time the output signal from the selection signal fetch means changes (inverts), and the data written in the master register is read every time the load signal rises. Transferred to register. Here, when the mask signal is at the logical "1" level, the output signal from the signal capturing means is not inverted even if the internal operation clock is generated. For this reason, the load signal is not generated during the period from the rise to the fall of the write signal and the period after a predetermined period from the fall until the next internal operation clock is generated, and data is transferred from the master register to the slave register. Is not done.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments. FIG. 1 is a block diagram showing an embodiment of the present invention. 4, the same reference numerals as those in FIG. 4 denote the same or equivalent components, and a description thereof will be omitted.

In this embodiment, a load signal generation circuit 7 is provided in place of the conventional timing control signal generation circuit 6. The load signal generation circuit 7 includes a logic circuit 7-1.
, A selector 7-2, a logic circuit 7-3, a delay circuit 7-4, and an exclusive OR circuit (EXOR circuit) 7-5.
It is composed of

The logic circuit 7-1 is provided as a mask signal generating means, and a period T (t1 to t2, t4 shown in FIG. 2A) from rising to falling of the write signal S2.
To t5) and a predetermined period from the fall until at least data writing is completed (t2 to t5 shown in FIG.
t3, t5 to t6) ΔT is a logic “1” level, and the rest period is a logic “0” level, and the mask signal S4
Is generated (FIG. 2C).

The selector 7-2 is provided as a signal selecting means, receives the mask signal S4 from the logic circuit 7-1 as an input, and outputs the signal from the logic circuit 7-3 when the mask signal S4 is at the logic "1" level. And outputs the selected output signal S5.
If it is at the logic "0" level, an inverted signal of the output signal S5 from the logic circuit 7-3 is selected and output.

The logic circuit 7-3 is provided as a selection signal fetch means, and outputs a selection output S6 (FIG. 2) from the selector 7-2.
(D)) is taken in synchronization with the timer clock S1, that is, taken every time the timer clock S1 rises,
Let it be an output signal S5 (FIG. 2 (e)).

The delay circuit 7-4 is provided as delay means, and outputs an output signal S5 from the logic circuit 7-3 for a predetermined time Δt
The signal is delayed to be a delayed signal S7 (FIG. 2 (f)). The EXOR circuit 7-5 is provided as exclusive OR means, and calculates the exclusive OR of the delay signal S7 from the delay circuit 7-4 and the output signal S5 from the logic circuit 7-3 to generate a load signal S8. Yes (Fig. 2 (g))

[When Write Signal S2 is Not Applied] When write signal S2 is not applied, mask signal S4 from logic circuit 7-1 attains a logic "0" level. The mask signal S4 at the logic "0" level is applied to the selector 7-2. The selector 7-2 outputs the mask signal S
When 4 is at the logic “0” level, an inverted signal of the output signal S5 from the logic circuit 7-3 is selected and output.

The logic circuit 7-3 captures the selection output S6 from the selector 7-2 at the rising edge of the timer clock S1, and sets it as an output signal S5. Thereby, the mask signal S
4 is at the logic "0" level, the output signal S5 of the logic circuit 7-3 is inverted every time the timer clock S1 rises (tm1, tm2, t shown in FIG. 2E).
m3 point).

The output signal S5 from the logic circuit 7-3 is delayed by .DELTA.t by the delay circuit 7-4 to produce a delayed signal S5.
7 (FIG. 2 (f)). The delay signal S7 and the output signal S5 from the logic circuit 7-3 are applied to an EXOR circuit 7-5. The EXOR circuit 7-5 takes an exclusive OR of the delay signal S7 and the output signal S5 to obtain a load signal S8 (FIG. 2 (g)). In this case, the load signal S8 becomes ΔΔ each time the output signal S5 from the logic circuit 7-3 changes (inverts).
The logic level is set to the logic "1" level during T (t shown in FIG. 2 (g)).
m1, tm2, tm3 points),

In accordance with the load signal S8 from the EXOR circuit 7-5, that is, the load signal S8 from the load signal generation circuit 7, the data written in the master register 1 at each rising of the load signal S8 is stored in the slave register. 2

As described above, when the write signal S2 is not supplied (normal case), the slave register 2 takes in the data of the master register 1 every time the load signal S8 rises in synchronization with the timer clock S1.

[0025] [If write signal S2 ₁ is given] If the light signal S2 ₁ is given, the logic circuit 7-1,
Period T and the falling predetermined period [Delta] T from the rise of the write signal S2 ₁ to fall, i.e. a logic "1" while the mask signal S4 period T1 (T1 = T + ΔT) shown in FIG. 2 (a) levels and I do. The mask signal S4 at the logic "1" level is applied to the selector 7-2. When the mask signal S4 is at the logic “1” level, the selector 7-2 selects and outputs the output signal S5 from the logic circuit 7-3.

The logic circuit 7-3 takes in the selection output S6 from the selector 7-2 at the rising edge of the timer clock S1 and sets it as an output signal S5. In this case, at time tm4 shown in FIG. 2B, the selected output S6 from the selector 7-2 is fetched and used as the output signal S5. In this case, the selected output S6
Is the same logic "1" level as the output signal S5 from the logic circuit 7-3 at that time, so the output signal S5 from the logic circuit 7-3 is not inverted. For this reason, t shown in FIG.
Even if the timer clock S1 rises at the point m4, the load signal S8 is not generated (see FIG. 2G), and data transfer from the master register 1 to the slave register 2 is not performed.

[0027] In point t2 past the tm4 point, when the write signal S2 ₁ falls, the writing of data from the data bus 4 to the master register 1 is performed. here,
Since during a predetermined time period ΔT from the time T and fall from the rise of the write signal S2 ₁ to fall mask signal S4 leaves a logic "1" level, the load signal Timer clock S1 is also falls during this period S8 does not occur and the data bus 4 to the master register 1
And data transfer from the master register 1 to the slave register 2 does not conflict with each other.

[0028] [Following the write signal S2 ₁ light signal S
Here if the 2 ₂ is given], the period when the write signal S2 ₂ is given subsequent to the write signal S2 _1, from the first rising edge of the write signal S2 ₁ to the falling T
And a period TA until a next timer clock S1 rises after a predetermined period ΔT from the fall, and 2
During the period T from the rise to the fall of the _second write signal S2 ₂ and the period TB after a predetermined period ΔT from the fall until the next timer clock S1 rises, the load signal S8 is not generated, and the master register 1 changes to the slave register. 2 is not transferred.

Therefore, as shown in FIGS. 2A and 2B, even if a conflict occurs between the falling edge of the _second write signal S22 and the rising edge of the timer clock S1, erroneous data is output to the slave register. 2 is not transferred. That is, if the rising and conflicts second write signal S2 ₂ falling and the timer clock S1 is occurred, the writing of data from the data bus 4 to the master register 1 by the fall of the write signal S2 ₂ is performed However, since data transfer from the master register 1 to the slave register 2 is not performed,
There is no problem that indefinite data is transferred.

Further, in the present embodiment, short interval of generation of the first write signal S2 ₁ and the second write signal S2 _2, the load signal S8 when the first write signal S2 ₁ is given Non-occurrence period TA and second write signal S
Non-generation period T of the load signal S8 when the 2 ₂ is given
When B partially overlaps (FIG. 2A shows this case), the load signal S8 is not generated during the period TA + TB (t1 to tm7), and the master register is generated by the _first write signal S21. The data m written to 1 is not transferred to the slave register 2 and the data n written to the master register 1 is transferred to the slave register 2 by the _second write signal S22. Thus, unnecessary first transfer of the write data m to the master register 1 is not performed, and malfunction such as generation of the coincidence signal S4 due to unnecessary data comparison can be prevented.

In the above-described embodiment, the period T from the rise to the fall of the write signal S2 and the predetermined period ΔT from the fall are set as the generation inhibition period of the load signal S8. The predetermined period ΔT may be set as the generation prohibition period of the load signal S8. A time chart in this case is shown in FIG. 3 corresponding to FIG.

In the above embodiment, the compare register of the timer has been described. However, any register having a master / slave two-stage configuration for synchronizing with an internal operation clock, such as an operation clock designation register, can be used. It is.

[0033]

As is apparent from the above description,
According to the first invention, the load signal is not generated during the period from the fall of the write signal to the generation of the next internal operation clock after at least a predetermined period from the end of the write operation to the completion of the data write, and the master register is transferred to the slave register Is not performed, there is no competition between data writing to the master register and data transfer from the master register to the slave register, and malfunction can be prevented.

According to the second and third aspects of the present invention,
The load signal is not generated during the period from the rise to the fall of the write signal and during the period from the fall to the next internal operation clock after at least a predetermined period from the completion of the data write, and from the master register to the slave register. Since data transfer to the master register is not performed, contention between data writing to the master register and data transfer from the master register to the slave register is eliminated, and malfunction can be prevented. in this case,
The generation interval between the first write signal and the second write signal is short, and the non-occurrence period of the load signal when the first write signal is applied and the load signal when the second write signal is applied. Assuming that the non-occurrence period partially overlaps, a period from a rise of the first write signal to a fall of the second write signal and a predetermined period from a fall of the second write signal after a predetermined period have elapsed. No load signal is generated during the period until the operation clock is generated.
The data written to the master register by the second write signal is not transferred to the slave register, and the data written to the master register by the second write signal is transferred to the slave register.
Since write data is not transferred to the master register for the second time, a malfunction such as generation of a coincidence signal due to unnecessary data comparison can be prevented.

It should be noted that Japanese Patent Laid-Open Publication No.
An "asynchronous double buffer write protection scheme" similar to the present invention is shown. In this method (the method of the prior application), the first buffer (corresponding to the master register) is set /
The reset configuration is adopted, and the first buffer is cleared after the transfer to the second buffer (corresponding to the slave register). EMPT reflecting whether or not there is data in this first buffer
The transfer signal to the second buffer is masked using the Y signal and its delay signal. On the other hand, according to the present invention, the first buffer is only set, it is not necessary to reset each buffer, and any data may be held (the EMPTY signal is unnecessary). Further, the transfer to the second buffer is always performed in synchronization with the rise of the internal operation clock, and the transfer signal to the second buffer is masked only for a certain period after the writing to the first buffer. There is a difference in that the time for determining data to be written to one buffer is guaranteed. This mask signal is generated by a write instruction to the first buffer irrespective of the data in the first buffer.

As described above, according to the present invention, even if the transfer to the second buffer is masked, desired data can be transferred to the second buffer at the next rising timing of the internal operation clock. However, in the method of the prior application, C
The PU needs to set the same data again in the first buffer. This is because the method of the prior application assumes a register for serial data transfer, whereas the present invention assumes a timer compare register. In other words, the method of the prior application is not used until the serial data transfer ends.
It is assumed that no data transfer is performed to the second buffer. Further, the present invention has an effect that, when two write commands to the first buffer are generated in succession, unnecessary first data is not transferred to the second buffer, and a malfunction of the comparison result is prevented. ing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a time chart in a case where a predetermined period from the fall of a write signal is set as a load signal generation inhibition period.

FIG. 4 is a block diagram showing a conventional configuration.

FIG. 5 is a time chart for explaining the operation of the circuit in FIG. 4;

[Explanation of symbols]

1: Master register (master compare register), 2:
Slave register (slave compare register), 3 ...
Timer, 4 asynchronous data bus, 5 comparator, 7 load signal generation circuit, 7-1 logic circuit, 7-2 selector, 7-3 logic circuit, 7-4 delay circuit, 7-5
... Exclusive OR circuit (EXOR circuit)

Claims (3)

[Claims] 1. A method for writing data from an asynchronous data bus to a master register at a falling edge of a write signal provided asynchronously with an internal operation clock, and for each rising of a load signal provided in synchronization with the internal operation clock. A method for writing data to a register from an asynchronous data bus for transferring data written to a master register to a slave register, wherein the load signal is supplied for at least a predetermined period from the fall of the write signal until data writing is completed. A method of writing data from an asynchronous data bus to a register, comprising a load signal generation prohibiting means for prohibiting the generation of the data. 2. The method according to claim 1, wherein data from an asynchronous data bus is written to a master register at a falling edge of a write signal provided asynchronously with an internal operation clock, and said data is written every time a load signal supplied in synchronization with said internal operation clock rises. A method of writing data to a register from an asynchronous data bus for transferring data written to a master register to a slave register, wherein a period from a rise to a fall of the write signal and at least data writing from the fall are completed. A method for writing data from an asynchronous data bus to a register, comprising a load signal generation inhibiting means for inhibiting the generation of the load signal for a predetermined period of time. 3. The data from the asynchronous data bus is written to a master register at the falling edge of a write signal asynchronously applied to an internal operation clock, and the data written to the master register is written to the slave register at each rising edge of a load signal. A method of writing data to a register from an asynchronous data bus for transferring data to the register, wherein a period from a rise to a fall of the write signal and a predetermined period from the fall to at least data writing are completed at a logic “1” level. During the other periods, a mask signal generating means for generating a mask signal as a logic “0” level, and a mask signal from the mask signal generating means as inputs,
When the mask signal is at the logic "1" level, the output signal from the selection signal capturing means is selected and output. When the mask signal is at the logic "0" level, the output signal from the selection signal capturing means is selected. Signal selecting means for selecting and outputting an inverted signal of the selected signal; selecting signal taking means for taking a selected output from the signal selecting means in synchronization with the internal operation clock as an output signal; A delay means for delaying an output signal from the delay means for a predetermined time and outputting it as a delay signal; and an exclusive OR of a delay signal from the delay means and an output signal from the selection signal capturing means is obtained as the load signal. A method of writing data from an asynchronous data bus to a register, comprising exclusive OR means.