JP2000181851A - Input and output controller and inter-processor data transfer method to be used in the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output controller by which necessity for data re-transfer or the like is eliminated and also data is transferred at high speed. SOLUTION: An FW(firmware) part 2 manages and controls channel devices 6-1 to 6-4 under it based on information of a MAC(memory access controller) part 3. The FW part 2 requests the connection of the channel device whose usage is designated to the channel device in a free state in accordance with a data transfer instruction from OS and transfers data by using the whole channel devices which are successfully connected. In this case, the channel devices transfer data by memory requests from a request transmitting circuit 4 based on memory request addresses which are generated in memory request address generating parts 5-1 to 5-4 corresponding to CHU(#0-#3) of the MAC part 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device and a data transfer method between processors used in the input / output control device, and more particularly, to a data transfer method between processors in a super computer system in which processors are connected via a switch device.

[0002]

2. Description of the Related Art Conventionally, in a super computer system, a plurality of processors are connected via a switching device. When performing data transfer between processors in this supercomputer system, the OS (operating system) instructs the I / O controller which physical channel device to use, and the I / O controller uses the designated physical channel device to transfer data. Performing a transfer.

As a data transfer method of this kind, there is a technique disclosed in Japanese Patent Application Laid-Open No. 4-185035. In the system described in this publication, a channel status feedback unit is provided for managing the free state of the physical channel and performing control for use with the specified physical channel, and uses the specified physical channel and the free physical channel. Data transfer.

That is, the channel status feedback unit detects and confirms the idle state of each physical channel,
When there is a free physical channel, the data is processed and generated and transmitted so that the data can be transmitted using the specified physical channel and the free physical channel.

[0005]

In the above-described conventional data transfer method, a data transmission side device detects and confirms a free physical channel, and when there is a free physical channel, uses the free physical channel to transfer data. But
When the physical channel of the data receiving apparatus cannot receive data, it may be necessary to perform processing such as retransmission.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, eliminate the need for re-transfer of data, etc. and perform high-speed data transfer, and an input / output control device and a processor used therefor. Between data transfer methods.

[0007]

SUMMARY OF THE INVENTION An input / output control device according to the present invention is an input / output control device for executing data transfer using a channel device designated by an operating system when data transfer between processors is performed. Connection request means for making a connection request to each of the designated channel device and the idle channel device when a data transfer command is input from the operating system;
Executing means for executing a data transfer instruction from the operating system using all the channel devices successfully connected to the connection request.

A method for transferring data between processors according to the present invention is a method for transferring data between processors of an input / output control device for executing data transfer using a channel device specified by an operating system when transferring data between processors. Making a connection request to each of the designated channel device and the idle channel device when a data transfer command is input from the operating system; and all the channel devices successfully connected to the connection request. Executing a data transfer instruction from the operating system using

That is, the input / output control device of the present invention manages and controls the physical channel device under the control of a firmware (FW) incorporated therein, and responds to a data transfer command from an OS (operating system). Therefore, a connection request is made between a physical channel device designated for use and a physical channel device in an idle state, and data transfer is performed using all physical channel devices that have been successfully connected.

[0010] Thus, since the data transfer is performed using only the channel device which has been successfully connected in the connection confirmation before starting the data transfer, the data transfer width can be increased, and the data transfer width and the like can be increased. It is possible to eliminate the need and perform high-speed data transfer.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an input / output control device according to one embodiment of the present invention. In the figure, an input / output control device 1 includes an FW (firmware) unit 2 and a MAC (Memory Access Content).
The MAC unit 3 is composed of a request sending circuit 4 and a memory request address generation unit (hereinafter, referred to as a memory request address generation unit) corresponding to CHU (# 0 to # 3). And 4.

The FW unit 2 includes channel devices (CHU # 0 to CHU # C).
HU # 3) State control of 6-1 to 6-4 is performed. That is,
The FW unit 2 has a switch switching table (not shown) in advance, refers to the data of the switch switching table at the time of connection request processing, and sends switch switching information to a switch device (not shown) to dynamically connect. It is possible to switch.

The MAC unit 3 controls memory transfer. That is, the request sending circuit 4 of the MAC unit 3 arbitrates the memory requests from the respective channel devices 6-1 to 6-4 and sends them to the memory (not shown). The memory request address generation units 5-1 to 5-4 are provided for each of the channel devices 6-1 to 6-
A corresponding memory request address is generated.

FIG. 2 shows the configuration of the memory request address generators 5-1 to 5-4 in FIG. 1 (hereinafter, the memory request address generators 5-1 to 5-4 are collectively referred to as a memory request address generator 5). FIG.

In the figure, memory request address generators 5-1 to 5-4 are provided with selectors 51 and 54, a transfer amount subtraction counter 52, and a memory request address element distance register (hereinafter referred to as an element distance register) 53.
, A next (NEXT) address register 55, and a next address generation circuit 56.

The selector 51 selects one of the initial value (transfer amount) from the FW unit 2 and the output of the transfer amount subtraction counter 52 and outputs it to the transfer amount subtraction counter 52. When an initial value from the FW unit 2 is set via the selector 51, the transfer amount subtraction counter 52 decrements the initial value every time a memory transfer is performed.

The inter-element distance register 53 holds an initial value (inter-element distance) from the FW unit 2. Selector 54 is FW
One of the initial value (next address) from the section 2 and the output of the next address generation circuit 56 is selected and output to the next address register 55.

The next address register 55 stores the initial value from the FW unit 2 and the value calculated by the next address generation circuit 56. The next address generation circuit 56 calculates a next memory request address from the value held in the inter-element distance register 53 and the value held in the next address register 55 every time a memory transfer is performed.

FIG. 3 is a block diagram showing a system configuration according to one embodiment of the present invention. In the figure, a system according to an embodiment of the present invention includes processors (# 0 to # 3) 7-1 to 4 having four channel units under an input / output control unit (IOP).
7-4 are connected to each other via a switch circuit 8.

FIG. 4 is a sequence chart showing an inter-processor data transfer operation during transmission according to one embodiment of the present invention, and FIG. 5 is a sequence chart showing an inter-processor data transfer operation during reception according to one embodiment of the present invention. It is.
6 to 9 are flow charts showing an inter-processor data transfer operation according to one embodiment of the present invention. The data transfer operation between processors according to one embodiment of the present invention will be described with reference to FIGS.

First, when performing an inter-processor data transfer operation during transmission, an OS (operating system) (not shown) issues an inter-processor data transfer transmission command to the input / output control device 1. The information of the inter-processor data transfer transmission instruction includes a memory initial address, a transfer amount, a used channel number, and the like. Here, a case where the used channel number is CHU # 0 will be described.

The input / output control device 1 receives an inter-processor data transfer command from the OS (step S1 in FIG. 6), and determines that the inter-processor data transfer command is a transmission command (step S2 in FIG. 6). Device 6-1
The state of 6-4 is checked (step S3 in FIG. 6), and switch switching and connection request processing are performed for the designated channel device and all other available unused channel devices with reference to the switch switching table (FIG. 6). FIG. 6 step S
4). In this case, the connection request is notified including information such as the connection source processor number.

In response to the connection request, the connection destination channel device or the switch circuit 8 notifies the connection permission or the connection rejection. The case where the switch circuit 8 notifies the connection rejection is a case where the transfer request destination channel device is performing data transfer.

The FW unit 2 waits for notification of connection permission or connection rejection for all the channel devices that have performed the connection request processing (steps S5 to S9 in FIG. 6), and confirms the channel device that has succeeded in connection (step S10 in FIG. 7). ). Here, it is assumed that four channel devices 6-1 to 6-4 have successfully connected.

The FW unit 2 sends the divided transfer data allocation information and the like to the destination channel device to all the channel devices 6-1 to 6-4 for which the connection request processing has succeeded (step in FIG. 7). S11).

The FW unit 2 sets each memory request initial address in the next address register 55 of the memory request address generation unit 5 corresponding to each of the channel devices 6-1 to 6-4 to which connection was successful (step S12 in FIG. 7). ).
For example, CHU # 0: memory request initial address CHU # 1: memory request initial address + 1 CHU # 2: memory request initial address + 2 CHU # 3: memory request initial address + 3 -4 sets a memory request initial address corresponding to each of them.

The FW unit 2 is provided with each of the channel devices 6-1 to 6-1.
A value obtained by equally dividing the number of successfully connected channel devices “4” in the 6-4 corresponding element distance register 53 by the number of successfully connected channel devices “4” in the transfer amount subtraction counter 52 is set. (Step S13 in FIG. 7).

Each of the channel devices 6-1 to 6-4 is connected to the FW unit 2
The data transfer is performed in accordance with the memory request address, the inter-element distance, and the transfer amount set from (step S14 in FIG. 7). When the data transfer of all the channel devices 6-1 to 6-4 is completed (step S15 in FIG. 7), FW part 2 is O
It reports the end of the inter-processor data transfer to S (step S16 in FIG. 7) (see FIG. 4).

The above description is based on the four channel devices 6-1 to 6-1.
6-4 shows the operation in the case where the transfer request processing is successful, but in the connection request processing for an empty channel device, if the connection fails due to the notification of connection rejection, only the channel device for which connection was successful is used. That is, the settings of the memory request initial address, transfer amount, inter-element distance, etc. of each channel device are changed to settings corresponding to the number of successfully connected channels, and data transfer is performed in the same manner as described above. Further, when the connection of the designated channel device fails, the FW unit 2 does not connect even if another free channel device succeeds in connection.
Reports the transfer failure to the OS.

Next, when performing an inter-processor data transfer operation at the time of reception, the OS issues an inter-processor data transfer instruction to the input / output control device 1. The information of this instruction includes a processor number of a transfer source, a memory initial address, a transfer amount, a used channel number, and the like. Here, a case where the used channel number is CHU # 0 will be described.

When the input / output control device 1 receives an inter-processor data transfer command from the OS (step S1 in FIG. 6) and determines that the inter-processor data transfer command is a reception command (step S2 in FIG. 6), the FW unit 2 Each channel device 6
Upon detecting the connection request notification from 1 to 6-4 (step S17 in FIG. 8), the connection request processor checks the processor number of the connection source and the state of the channel device (FIG. 8).
Step S18), the connection requesting channel device is notified of connection permission or connection rejection via the connection-requested channel device (FIG. 8, steps S21 and S23).

The state of the channel device when detecting the connection request notification is as follows: a) The channel device specified by the inter-processor data transfer instruction and the transfer source processor number match; b) The inter-processor data transfer instruction And c) the state in which the transfer source processor numbers do not match, and c) the state not specified by the inter-processor data transfer instruction.

Therefore, the FW unit 2 notifies connection permission in response to the connection request detecting the channel device in the state a) or c) (steps S19, S22, S23 in FIG. 8, b).
A connection rejection is notified in response to the connection request that has detected the channel device in the state (2) (steps S20 and S21 in FIG. 8). FW
The unit 2 repeats the above check for all the channel devices that have issued the connection request (steps S18 to S2 in FIG. 8).
4). Here, it is assumed that the connection permission has been notified to the four channel devices 6-1 to 6-4.

The FW unit 2 refers to the channel device designated by the OS and the connection information from the destination channel device of each unused channel device, and uses the channel used for the data transfer instruction between processors. The allocation information of the device and the divided data is obtained (step S25 in FIG. 9).

The input / output control device 1 sets each memory request initial address in the next address register 55 of the memory request address generator 5 corresponding to each of the connected channel devices 6-1 to 6-4 (step in FIG. 9). S2
6). For example, CHU # 0: memory request initial address CHU # 1: memory request initial address + 1 CHU # 2: memory request initial address + 2 CHU # 3: memory request initial address + 3 -4 sets a memory request initial address corresponding to each of them.

The FW unit 2 is provided with each of the channel devices 6-1 to 6-1.
A value obtained by equally dividing the number of channel devices “4” connected to the element distance register 53 corresponding to 6-4 by the number of all channel devices “4” connected to the transfer amount subtraction counter 52 is set. (Step S27 in FIG. 9).

Each of the channel devices 6-1 to 6-4 has a FW unit 2
The data transfer is performed in accordance with the memory request address, the inter-element distance, and the transfer amount set from (step S28 in FIG. 9). When the data transfer of all the channel devices 6-1 to 6-4 is completed (step S29 in FIG. 9), FW part 2 is O
It reports the end of the data transfer between processors to S (FIG. 9, step S30) (see FIG. 5).

The above description is based on the four channel devices 6-1 to 6-1.
The operation when the transfer permission is notified to 6-4 is shown. However, if the transfer is rejected due to the fact that a data transfer instruction has already been received, only the channel device for which connection has been permitted will be used. The settings of the memory request initial address, transfer amount, distance between elements, etc. of each channel device are changed to settings corresponding to the number of channels permitted to be connected,
Data transfer is performed in the same manner as described above.

FIG. 10 is a diagram showing an example of division of transfer data according to one embodiment of the present invention. In the figure, data stored at address A of the memory is transferred to each channel device CHU # 0.
To CHU # 3, each channel device C
The transfer amount for each of HU # 0 to CHU # 3 is "total transfer amount / number of channels to be used". The initial address of the transfer data is sent out in a format shifted by one word by the channel device number, and the receiving side arranges the data. Will be restored.

That is, the channel device CHU # on the transmission side
0 transfers data of address A + 0, address A + 4,..., And channel unit CHU # 1 transfers address A + 1,
The data of the address A + 5,... Is transferred, and the channel unit CHU # 2 is transferred to the address A + 2, the address A + 6,.
, And the channel device CHU # 3 transfers the data of the address A + 3, the address A + 7,...

On the other hand, the channel device CHU # 0 on the receiving side receives data a, e,
... are the addresses B + 0, B + 4,.
.., And the channel device CHU # 1 stores the data b, f,... From the transmission-side channel device CHU # 1 at addresses B + 1, B + 5,. 2 is a channel device C on the transmission side
.. Are stored at addresses B + 0, B + 4,... Of the memory, and the channel unit CHU # 3 stores the data d, h,. .. Are stored at addresses B + 0, B + 4,.

The above-described operation is performed immediately after the connection, from the transmitting-side channel devices CHU # 0 to CHU # 3 to the receiving-side channel device C.
This is performed based on the connection information sent to HU # 0 to CHU # 3. Since the data transfer of each channel device is performed simultaneously, in this case, the data transfer time is shortened to “1 / number of used channels” when data transfer is performed in one channel.

As described above, the FW unit 2 built in the input / output control device 1 manages and controls the subordinate channel devices 6-1 to 6-4, and designates use according to a data transfer command from the OS. Makes a connection request between the connected channel device and the idle channel device, and performs data transfer using all the successfully connected channel devices. Since the data transfer is performed using only the channel device
It is possible to increase the data transfer width, eliminate the necessity of re-transfer of data, and perform high-speed data transfer.

[0044]

As described above, according to the present invention, there is provided an input / output control device for executing data transfer using a channel device designated by an operating system when data is transferred between processors. When a data transfer command is input, a connection request is made to each of the designated channel device and the idle channel device, and data is transferred from the operating system using all the channel devices that have successfully connected to the connection request. By executing the instruction, it is possible to eliminate the necessity of re-transferring data and the like, and it is possible to perform high-speed data transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an input / output control device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a memory request address generator of FIG. 1;

FIG. 3 is a block diagram illustrating a system configuration according to an embodiment of the present invention.

FIG. 4 is a sequence chart showing an inter-processor data transfer operation during transmission according to one embodiment of the present invention.

FIG. 5 is a sequence chart showing an inter-processor data transfer operation during reception according to an embodiment of the present invention.

FIG. 6 is a flowchart illustrating an inter-processor data transfer operation according to an embodiment of the present invention.

FIG. 7 is a flowchart illustrating an inter-processor data transfer operation according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating an inter-processor data transfer operation according to an embodiment of the present invention.

FIG. 9 is a flowchart illustrating an inter-processor data transfer operation according to an embodiment of the present invention.

FIG. 10 is a diagram showing an example of dividing transfer data according to an embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 input / output control device 2 firmware unit 3 MAC unit 4 request transmission circuit 5-1 to 5-4 memory request address generation unit corresponding to CHU (# 0 to # 3) 6-1 to 6-4 channel device (CHU # 0 CHU #
3) 7-1 to 7-4 Processor (# 0 to # 3) 8 Switch circuit 51, 54 Selector 52 Transfer amount subtraction counter 53 Memory request address element distance register 55 Next address register 56 Next address generation circuit

Claims (8)

[Claims] 1. An input / output control device for executing data transfer using a channel device designated by an operating system when data is transferred between processors, wherein the input / output control device receives a data transfer command from the operating system. A connection request unit for making a connection request to each of the designated channel device and the channel device in an idle state; and a data transfer instruction from the operating system using all the channel devices successfully connected to the connection request. An input / output control device comprising: an execution unit that executes the operation. 2. The input / output control device according to claim 1, wherein said connection requesting means and said executing means comprise firmware. 3. The system according to claim 1, wherein data to be transmitted when the data transfer command is a transmission command from the operating system is divided and transmitted by all the channel devices that have succeeded in the connection. Item 2. The input / output control device according to Item 2. 4. The input device according to claim 3, wherein when the data transfer command from the operating system is a reception command, the received data is divided and synthesized by all the channel devices that have succeeded in the connection. Output control device. 5. An inter-processor data transfer method of an input / output control device for executing data transfer using a channel device designated by an operating system when data transfer between processors is performed, wherein the data transfer from the operating system is performed. Making a connection request to each of the designated channel device and the idle channel device when a command is input; and, from the operating system, using all the channel devices successfully connected to the connection request. Executing a data transfer instruction. 6. The method according to claim 5, wherein the step of making the connection request and the step of executing the data transfer instruction comprise firmware. 7. The transmission method according to claim 5, wherein data to be transmitted when the data transfer command is a transmission command from the operating system is divided and transmitted by all the channel devices that have succeeded in the connection. Item 7. An inter-processor data transfer method according to Item 6. 8. The processor according to claim 7, wherein when the data transfer command from the operating system is a reception command, the received data is divided and combined by all the channel devices that have successfully connected. Data transfer method.