JP2000171524A - Semiconductor integrated circuit and its inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inspect a semiconductor device driving at high speed with use of an inspecting apparatus of a lower drive speed than the device. SOLUTION: An inspection enable signal Data-En is output from a data- generating device 11 of an inspecting apparatus 10 to a DUT (device to be inspected) 20. A first logic circuit 21 in the DUT 20 converts a signal pattern of a normal signal transmission rate stored in a register 28 to a high speed signal pattern SpeedData-Tx of a high signal transmission rate, and a transmitting circuit 22 transmits the high speed signal. At an inspection, a switch circuit 24 is closed and the transmitted high speed signal is received by a receiving circuit 23. The received high speed signal is output to a second logic circuit 26. The logic circuit 26 converts the signal to a low speed signal Data-Rx of the normal rate and outputs to the inspecting apparatus 10. A comparator 12 compares the received low speed signal with an expected value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor integrated circuit which operates at a high speed, and more particularly, to a semiconductor integrated circuit which can be inspected by using an inspection device which operates at a lower speed than the operation speed of the semiconductor integrated circuit. Regarding the configuration.

[0002]

2. Description of the Related Art In recent years, research on ultra-high-speed interface technology has been advanced, and image data transmitted at high speed according to the IEEE 1394 standard can be displayed on a display.
High-speed operation of LSI has been dramatically advanced. But,
At present, there is a delay in the development of an inspection apparatus for inspecting an LSI that operates at a high speed, as compared with the development speed of the LSI.

Conventionally, an inspection apparatus for inspecting a high-speed LSI includes a data generator for generating data at a high speed corresponding to a high-speed operation of an LSI to be inspected, and a high transfer rate obtained as a result of inspection of the high-speed LSI. A high-speed comparator for comparing the high-speed signal with an expected value. Normally, when testing a device operating at high speed, in a high-speed data transmission test, low-speed data of a predetermined pattern is input to a device under test from a data generator of an inspection device, and then a PLL (phase-locked loop) in a logic circuit of the device under test is input. The input data is frequency-divided at high speed using a synchronous loop or the like to obtain high-speed data having a high transfer rate. The high-speed data is transmitted to the inspection device by a high-speed transmission circuit in the device under test, and the high-speed data is transmitted in the inspection device. The received high-speed data is compared with an expected value using a comparator.
On the other hand, in the high-speed data reception test, high-speed data having a high transfer rate is transmitted from the data generator of the inspection apparatus to the device under test, and the high-speed data is received by the high-speed reception circuit in the device under test, and then the internal Is divided into low-speed data having a low transfer rate by the logic circuit described above, and the low-speed data is compared with an expected value by a comparator in the inspection apparatus for inspection.

FIG. 7 shows an example of a configuration for testing a high-speed device using a conventional testing apparatus. An example of this is a high-speed LSI tester J from Teradyne, USA.
971 is a test configuration. In the figure, when a DUT (device under test) 70 requires high-speed transfer processing,
In the high-speed data transmission test, the data generating device 61 of the inspection device 60 inputs an ordinary input pattern having a transfer rate of, for example, 50 Mbps to the DUT 70. The input pattern is D
The first logic circuit 71 in the UT 70 receives the signal, divides it at a high speed by a PLL or the like (not shown) in the first logic circuit 71, and then converts a high-speed pattern signal having a high transfer rate, for example, 400 Mbps, to a high-speed Output from the transmission circuit 72 to the inspection device 60. In the inspection device 60, the comparator 62 compares the high-speed pattern, which is the reception result, with the expected value pattern from the data generation device 61, and outputs the inspection result.

On the other hand, in the high-speed data reception test, the high-speed data generator 63 of the inspection device 60 converts the high-speed pattern signal into a DU at a transfer rate equal to the data transfer rate of the DUT 70.
In the DUT 70, the high-speed receiving circuit 73 receives the high-speed pattern signal, and the second logic circuit 74 divides the high-speed pattern signal into a low-speed signal to generate a low-speed pattern at a normal transfer rate (50 Mbps). Then, the low-speed pattern, which is the reception result, is compared with an expected value by the comparator 64 in the inspection device 60.

Therefore, in the conventional inspection apparatus 60, it is necessary to mount the high-speed comparator 62 in the high-speed data transmission test and the high-speed data generator 63 in the high-speed data reception test.

[0007]

However, the high-speed data generator 63 and the high-speed comparator 6 of the inspection device 60
2 is very expensive, and from the viewpoint of cost, an increase in inspection cost is a major problem.

In recent years, semiconductor integrated circuits have been aiming at further higher speeds.
At present, it has not been well followed to increase the speed of semiconductor integrated circuits. Further, even if the speed of the semiconductor integrated circuit is increased, every time the speed of the semiconductor integrated circuit is increased, it is enormous cost to replace the inspection apparatus in accordance with the increase in the speed. Further, when the LSI inspection apparatus is changed every time the speed of the LSI is increased, if an LSI inspection apparatus of a different maker is used, a problem such as a long time is required for conversion of a program.

Further, as the speed of the device under test increases, it is necessary to test for the delay skew of the transferred signal and the potential drop of the transfer signal caused by the signal wiring. Worst case such as delay skew of the signal received by the device under test is possible, but the worst case of delay skew and potential drop of the signal occurring within the device under test is possible. Could not be tested.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor integrated circuit which can be inspected by an ordinary inspection apparatus for low-speed signals.

Another object of the present invention, in addition to the above-mentioned object, is to intentionally cause a potential drop and delay skew in a semiconductor integrated circuit to be inspected and to reduce the potential in a semiconductor integrated circuit during high-speed signal transfer. It is an object of the present invention to provide a semiconductor integrated circuit capable of performing a worst case test that can occur.

[0012]

In order to achieve the above object, according to the present invention, a high-speed signal transmitted by a transmitting circuit in a semiconductor integrated circuit is received by a receiving circuit in its own semiconductor integrated circuit, and the high-speed signal is received by the receiving circuit. A configuration is employed in which a high-speed signal is converted into a low-speed signal and inspection is performed based on the low-speed signal.

Further, a potential control circuit for lowering the potential of a high-speed signal is provided in a semiconductor integrated circuit to be tested, or a delay circuit for forcibly generating a delay skew between two signals constituting a high-speed differential signal. Is provided.

That is, a semiconductor integrated circuit according to the first aspect of the present invention includes a transmitting circuit for transmitting a high-speed signal having a high transfer rate, and a receiving circuit. A first logic circuit that receives a low-speed signal having a low transfer rate, generates the high-speed signal, and outputs the generated high-speed signal to the transmission circuit; a signal line that connects the transmission circuit and the reception circuit; And
A switch for closing the inspection and sending a high-speed signal transmitted from the transmission circuit to the reception circuit; and a second means for inputting the high-speed signal received by the reception circuit and converting the high-speed signal into another low-speed signal. And a logic circuit.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the first logic circuit includes a potential control circuit for controlling a potential level of a generated high-speed signal to be higher or lower. Features.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A transmission circuit for transmitting a high-speed differential signal having a high transfer rate;
A first logic for receiving a low-speed signal having a low transfer rate from the external inspection device at the time of inspection connected to the external inspection device, generating the high-speed differential signal, and outputting the generated high-speed differential signal to the transmission circuit; Circuit, a differential signal wiring composed of two wirings connecting the transmission circuit and the reception circuit, and a high-speed differential signal arranged on the differential signal wiring, closed at the time of the test, and transmitted from the transmission circuit. Switch means for sending a signal to the receiving circuit; a second logic circuit for receiving a high-speed differential signal received by the receiving circuit and converting the high-speed differential signal into another low-speed signal; A delay circuit for delaying one of the two signals constituting the high-speed differential signal input to the circuit.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the first logic circuit includes a potential control circuit for controlling a potential level of a generated high-speed differential signal to be higher or lower. It is characterized by the following.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A first logic circuit for receiving a signal having a low transfer rate from the inspection device and generating and outputting a high-speed differential signal having a high transfer rate comprising a data signal and a strobe signal at the time of inspection connected to an external inspection device; A transmission circuit for transmitting a high-speed differential signal generated by the first logic circuit; and a reception circuit for receiving the high-speed differential signal transmitted by the transmission circuit during the test by exchanging the data signal and the strobe signal. A second logic circuit that inputs a high-speed differential signal received by the receiving circuit and converts the strobe signal included in the high-speed differential signal into a low-speed signal having a low transfer rate; A storage circuit in which an expected value of the low-speed signal converted by the circuit is stored in advance.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A transmission circuit for transmitting a high-speed differential signal having a high transfer rate;
With the receiving circuit as one port, the transmitting circuit and the receiving circuit are provided with two ports, and at the time of inspection connected to an external inspection device, a low-speed signal having a low transfer rate is input from the external inspection device, and the high-speed differential signal is A first logic circuit for generating and outputting to the one set of transmission circuits, wherein the transmission circuit of one port and the reception circuit of the other port are:
The high-speed differential signal, which is connected by a differential cable during the inspection and is transmitted from the transmission circuit at the inspection and received by the receiving circuit through the differential cable during the inspection, is converted into a low-speed signal having a low transfer rate. And two logic circuits.

According to a seventh aspect of the present invention, there is provided a method for inspecting a semiconductor integrated circuit, comprising: a transmitting circuit for transmitting a high-speed signal having a high transfer rate; and a receiving circuit. The low-speed signal is received, the high-speed signal is generated, the generated high-speed signal is transmitted from the transmission circuit, the transmitted high-speed signal is received by the reception circuit, and the received high-speed signal is transmitted at a low speed. Convert it to a signal,
The converted low-speed signal is compared with an expected value of the low-speed signal.

According to an eighth aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit, comprising: a transmission circuit for transmitting a high-speed differential signal having a high transfer rate comprising a data signal and a strobe signal; and a reception circuit. In the inspection method, a high-speed differential signal transmitted from the transmission circuit is received by exchanging the data signal and the strobe signal, and a strobe signal of the received high-speed differential signal is compared with an expected value of the strobe signal. It is characterized by the following.

With the above arrangement, according to the first to seventh aspects of the present invention, the reception circuit in the device under test receives the high-speed data output from the transmission circuit to the external inspection apparatus in the conventional test, and Since the data is converted into low-speed data in the inspection device and the inspection is performed based on the low-speed data, the inspection device does not require the high-speed comparator 62 and the high-speed data generator 63 as in the related art. Therefore, a semiconductor integrated circuit that transfers data at high speed can be satisfactorily inspected using an inexpensive inspection device.

In particular, according to the present invention, at the time of testing the device under test, the potential control circuit raises the potential level of the high-speed signal transmitted from the transmission circuit from a predetermined voltage (for example, 3.3 V). In the normal operation using the device under test, it is possible to perform a worst case test of a potential drop at a time when the potential level of the high-speed signal drops to reach a malfunction. Become.

According to the third aspect of the present invention, since the delay circuit forcibly generates the skew of the high-speed differential signal, the delay of how large the skew of the high-speed differential signal leads to a malfunction may occur. Worst case inspection.

Further, according to the fifth and eighth aspects of the present invention, even if the receiving circuit exchanges and receives the data signal of the high-speed differential signal and the strobe signal at the time of inspection, the storage circuit stores the received signal in advance. Since the expected value of the original data signal received as the strobe signal is stored in the circuit,
By comparing the strobe signal received by the receiving circuit with the expectation stored in the storage circuit, the device under test can be inspected.

In addition, according to the present invention, at the time of inspection, the transmission circuit of one port and the reception circuit of the other port are connected by a differential cable, so that the high-speed differential transmitted from the transmission circuit is transmitted. The data signal included in the moving signal is received as it is by the receiving circuit as a data signal.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a block configuration for inspecting a semiconductor integrated circuit according to a first embodiment. In FIG. 1, reference numeral 10 denotes an inspection apparatus, and reference numeral 20 denotes a device to be inspected (semiconductor integrated circuit).

The inspection apparatus 10 includes a data generation apparatus 11 that outputs an inspection enable signal Data_En, an output signal pattern Data_Rx of a low transfer rate (for example, about 50 Mbps) output from a device under test (hereinafter, referred to as a DUT) 20, A comparator for comparing the expected value from the data generator with an expected value;

The DUT 20 receives a test enable signal Data_En from the data generator 11 of the tester 10.
Is input to the first logic circuit 21. The first logic circuit 21 operates at a normal transfer rate (for example, 50 Mbp).
A register 28 for storing the low-speed signal pattern of s) in advance is built in. Further, the first logic circuit 21 performs a test at the time when the test enable signal Data_En is input,
The low-speed signal pattern of the register 28 is frequency-divided and a transfer rate higher than the normal transfer rate (for example, 400
High-speed signal pattern Spe (transfer rate of about Mbps)
edData_Tx is generated, and the high-speed signal pattern S
Outputs speedData_Tx.

Further, the DUT 20 outputs the high-speed signal S
High-speed transmission circuit 22 for transmitting speedData_Tx
And a high-speed receiving circuit 23. The high-speed transmission circuit 2
2 and the high-speed receiving circuit 23 are connected by a signal wiring 27, and a switch circuit (switch means) 24 is arranged on the signal wiring 27, and the switch circuit 24 is controlled by a test control circuit 25. The test control circuit 25
When the DUT 20 receives the test enable signal Data_En from the test apparatus 10, the switch circuit 24 is closed to allow the high-speed receiving circuit 23 to receive the high-speed signal pattern SpeedData_Tx output from the high-speed transmitting circuit 22. is there.

In addition, the DUT 20 has a second logic circuit 26 for inversely converting the high-speed signal pattern SpeedData_Tx of about 400 Mbps received by the high-speed receiving circuit 23 into a low-speed signal pattern Data_Rx of a normal rate of about 50 Mbps. Be provided. The inversely converted low-speed signal pattern Data_Rx is supplied to the inspection device 10
Is output to

Next, the inspection of the semiconductor integrated circuit of the present embodiment will be specifically described. In FIG. 1, a data generation device 11 of a test device 10 has a test enable signal Data_E
n to the DUT 20, the first in the DUT 20
The logic circuit 21 of 50Mb stored in the register 28
The test pattern having a low transfer rate of about ps is converted into a high-speed signal (test pattern) SpeedData_Tx having a high transfer rate of, for example, about 400 Mbps, and the test pattern is transmitted from the high-speed transmission circuit 22.

At the time of this inspection, the switch circuit 24 in the DUT 20 is closed, and in the DUT 20, the high-speed receiving circuit 23 receives the test pattern SpeedData_Tx as it is. ON / OFF of the switch circuit 24 is controlled by a test control circuit 25. The test control circuit 25 switches the switch circuit 24 during the test.
Is turned on, and is turned off in the normal operation. Due to the short circuit inside the DUT 20, the high-speed receiving circuit 23
The test pattern SpeedData_Tx of the degree is received, and the pattern of the received result is driven to the second logic circuit 26 while maintaining the high speed. The second logic circuit 26 includes 400
Mbps reception result pattern SpeedData_Tx
This time, the comparator 12 of the inspection apparatus 10 can handle 50
Low-speed pattern Data of normal transfer rate of about Mbps
_Rx and output to the comparator 12 of the inspection apparatus 10. The comparator 12 detects the low-speed pattern Da of the DUT 20.
ta_Rx is compared with the expected value pattern of the data generator 11 of the inspection device 10 at a transfer rate of 50 Mbps.

Therefore, in FIG. 1, the high-speed transmission circuit 22 and the high-speed reception circuit 23 of the DUT 20 are internally short-circuited by the switch circuit 24 at the time of inspection, and the high-speed test pattern SpeedData_T received by the reception circuit 23.
Since x is converted into the low-speed pattern Data_Rx of the normal transfer rate, the inspection apparatus 10 can perform the high-speed data transfer inspection using the inspection enable signal Data_En of the normal transfer rate of about 50 Mbps. In other words,
The high-speed signal pattern SpeedData_Tx of about 400 Mbps output from the high-speed transmission circuit 22 is not immediately transmitted to the inspection apparatus 10 as in the related art, and the high-speed signal pattern SpeedData_Tx is received by the reception circuit 23 in the DUT 20.
a_Tx is received, and the second logic circuit 26 again receives 50 Mb
Since the frequency is divided into a low-speed pattern Data_RX of about ps and then output to the inspection device 10 and inspected by the comparator 12 in the inspection device 10, the inspection device 10 requires a data generator for high-speed signals and a comparator for high-speed signals. And not.

Since the switch circuit 24 and the test control circuit 25 are provided, when switching from the normal operation of the device under test to the test, the test can be performed by short-circuiting the high-speed transmission circuit 22 and the high-speed reception circuit 23. .

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
An embodiment will be described. In the DUT 20 'shown in the figure, a potential control circuit 29 is included in a first logic circuit 21'. The potential control circuit 29 is controlled by the first logic circuit 21 to
The central potential (for example, 1.8 V) of the high-speed signal pattern converted to a transfer rate of about 0 Mbps is lowered in an arbitrary voltage range (for example, 0.5 V range), and this high-speed signal SpeedData_Tx is output to the transmission circuit 22. .
The potential control circuit 29 has a 4-bit level control signal Level In1, Level In2, Level In3 and Level In4 from the outside.
And the combination of these control signals causes the high-speed signal S
The width of decrease or increase in the potential level of the speed_data_Tx is determined. For example, if the combination of these signals is “00”
If it is "01", it is lowered by 10 mV, and if it is "0100", it is raised by 100 mV.

The other structure is the same as that of the first embodiment. The high-speed transmission circuit 22 outputs the high-speed signal pattern SpeedData_Tx to the high-speed reception circuit 23, and outputs the second
Logic circuit 26 receives the high-speed reception signal pattern SpeedData_Tx whose central potential has dropped, and receives the 50 Mbps signal.
The signal is converted into a low-speed signal pattern Data_Rx and output to the inspection apparatus 10.

Here, since the central potential of the high-speed signal pattern SpeedData_Tx can be dropped and fluctuated within a predetermined voltage range (for example, a range of 0.5 V) by the potential control circuit 29, the DU is used during normal use of the DUT 20.
It is possible to inspect the worst case of the voltage drop of the high-speed signal occurring in T20.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described. FIG. 3 is a block diagram showing an overall configuration for testing a semiconductor integrated circuit according to the third embodiment of the present invention.

In the figure, the DUT 30 is an inspection device 1
0 is input from the data generation device 11 mounted on the data generation device 0 to the inspection enable signal Data_En shown in FIG.
Logic circuit 31. This first logic circuit 31
A normal transfer rate as shown in FIG.
A register 38 for storing a low-speed signal pattern (Mbps) in advance. Further, the first logic circuit 31 divides the low-speed signal pattern of the register 38 at the time of inspection when the inspection enable signal Data_En is input, and transfers the data at a transfer rate higher than the normal transfer rate (for example, about 400 Mbps). And a DS encoder (encoder) (not shown) that generates a high-speed differential signal pattern SpeedData_Tx having a transfer rate of (a transfer rate), and outputs the generated high-speed differential signal pattern SpeedData_Tx. The high-speed differential signal pattern SpeedData_T
x is a differential signal composed of two signals, a data signal Data and a strobe signal Strobe, as shown in FIG.

The DUT 30 is provided with a high-speed differential signal pattern SpeedDat from the first logic circuit 31.
It has a high-speed transmission circuit 32 for transmitting a_Tx and a high-speed reception circuit 33. A differential signal line 37 is disposed between the high-speed transmission circuit 32 and the high-speed reception circuit 33, and a switch circuit 34 is disposed on the differential signal line 37. The test control circuit 35 closes the switch circuit 34 at the time of inspection, and causes the high-speed reception circuit 33 to receive the high-speed differential signal pattern SpeedData_Tx output from the high-speed transmission circuit 32 in the DUT 30.

Further, the DUT 30 is connected to the second logic circuit 3
6 is provided. The second logic circuit 36 reversely converts the high-speed differential signal pattern SpeedData_Tx of about 400 bps received by the high-speed receiving circuit 33 into a low-speed differential signal pattern of a normal transfer rate of about 50 Mbps. ) (Not shown). The inversely converted low-speed differential signal pattern includes a data signal and a strobe signal, similarly to the high-speed differential signal pattern. Further, the second logic circuit 36 includes a register (storage circuit) 39. This register 39
An expected value of the inversely converted low-speed signal pattern is stored in advance. The second logic circuit 36 compares the inversely converted low-speed signal pattern with an expected value of the register 39,
The comparison result signal Data_Rx is output to the inspection device 10. This comparison result signal is shown in FIG. In FIG. 3, a delay circuit D is disposed on a line through which a strobe signal is transmitted among differential signal lines between the high-speed receiving circuit 33 and the second logic circuit 36.

Hereinafter, the inspection of the semiconductor integrated circuit according to the present embodiment will be specifically described. In FIG. 3, the data generation device 11 of the inspection device 10 has the inspection enable signal Data_E.
n to the first logic circuit 31 in the DUT 30.

In the DUT 30, the first logic circuit 31
Upon receiving the inspection enable signal Data_En of about 0 Mbps, the operating frequency (for example, 4
00Mbps) High-speed test pattern SpeedDat
Generate a_Tx. At this time, D of the first logic circuit 31
The S encoder uses the high-speed test pattern SpeedDat
As a_Tx, a differential signal pattern including a data signal and a strobe signal is generated and output to the high-speed transmission circuit 32.

In the DUT 30, the switch circuit 34 is controlled and closed by the test control circuit 35. Therefore, the high-speed differential signal S transmitted from the high-speed transmission circuit 32
The speedData_Tx is received by the high-speed receiving circuit 33 in the DUT 30 as it is. The received high-speed differential pattern SpeedData_Tx is output to the second logic circuit 36 at high speed.

The high-speed differential signal pattern SpeedDa
ta_Tx is transmitted from the high-speed reception circuit 33 to the second logic circuit 36
When the signal is output to the strobe line, the signal passes through the delay circuit D arranged on the strobe wiring. The delay circuit D forcibly delays the strobe signal pattern, and the delayed strobe signal is input to the DS decoder in the second logic circuit 36. The DS decoder of the second logic circuit 36 decodes the encoded high-speed differential signal pattern to generate a 400 Mb
ps high-speed reception result pattern SpeedData_Tx
Is returned to the low-speed differential signal pattern Data_Rx of the normal frequency of about 50 Mbps. This low-speed differential signal pattern is compared with the expected value stored in the register 39 in the second logic circuit 36, and the comparison result signal Data_Rx is output to the inspection device 10. In the inspection device 10, the comparator 12 outputs the comparison result signal Data_R from the DUT 30.
x is compared with an expected value from the data generator 11.

Here, since the delay circuit D forcibly delays the strobe signal included in the high-speed differential signal, an arbitrary skew value of the high-speed differential signal when connected to an inspection device or the like is stored in the DUT 30. You can have. Therefore,
By changing the delay value of the delay circuit D variously, the worst case (maximum skew value) of the skew of the high-speed differential signal can be inspected.

Further, since the first logic circuit 31 includes the DS encoder, it is possible to generate a differential signal pattern composed of a data signal and a strobe signal suitable for the purpose of the test at the time of the test. Further, since the clock signal is generated based on the data signal and the strobe signal, the transmission circuit 32 and the reception circuit 33 operate with the high-speed clock signal. In addition, the edge of the generated clock signal is
Since the delay is with respect to the edge of the data signal, the delay circuit D
Thus, the strobe signal delayed by the clock signal can be reliably latched by the clock signal.

In the present embodiment, the delay circuit D is arranged on the strobe signal wiring, but may be arranged on the data signal wiring. That is, the delay circuit D may be disposed on any one of the differential signal lines between the receiving circuit 33 and the second logic circuit 36.

Further, the first logic circuit 31 shown in FIG. 3 may be changed to the first logic circuit 21 'shown in FIG. 2, and a potential control circuit 29 may be provided inside the first logic circuit. good.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. This embodiment shows a case where a semiconductor integrated circuit having a transceiver circuit of a physical layer LSI of the IEEE 1394 standard is inspected.

In the same figure, by using a short-circuit structure from the signal output side to the signal input side of the high-speed transmission / reception circuit 42 inside the DUT 40, by setting the inspection mode, the data signal is converted into a strobe signal inside the high-speed transmission / reception circuit 42. Let it be received. In normal operation, a data signal cannot be received as a strobe signal. When a data signal is received as a strobe signal in the test mode, an expected value of the strobe signal is stored in a register 49 in the second logic circuit 46 in advance. This will be specifically described as follows.

The IEEE 1394 standard employs a structure in which a clock signal is generated by an exclusive OR of a data signal and a strobe signal. In the test mode, as shown in FIG. 4D, the data signal Data and the strobe signal Strobe are exchanged and received. For example, “010110” is used as a data signal.
When "10" is transmitted at high speed, the high-speed transmission / reception circuit 42 internally receives the strobe signal "000011111" at high speed. In this connection, if the register 49 has the pattern of the received strobe signal as an expected value, the inspection can be performed.

The short circuit structure in the transmission / reception circuit 42 includes the switch circuits 27 and 37 of the first and second embodiments.
Is not placed. The other configuration is the same as that of the third embodiment, and the description is omitted.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.
An embodiment will be described. This embodiment is based on IEEE1.
The case where an inspection is performed using a 394 standard differential cable is shown. FIG. 6 is a block diagram showing an overall configuration for inspecting the semiconductor integrated circuit of the present embodiment.

In FIG. 6, an inspection device 10 and a DUT 50 are provided. The DUT 50 has a configuration having two ports,
Each of the port 1 and the port 2 has a first logic circuit 31 having a register 38, a high-speed transmission circuit 32, a high-speed reception circuit 33, and a second port having a register 39, similarly to the DUT 20 of the third embodiment. And a short circuit structure from the high-speed transmission circuit 32 to the high-speed reception circuit 33. The switch circuit 34 of FIG. 3 is not arranged in the short circuit structure. The inspection device 10 has the same configuration as the inspection device 10 of the third embodiment.

The high-speed transmission circuit 32 of the port 1 and the high-speed reception circuit 33 of the port 2 are connected to the IEEE139
It is connected by a differential cable 57 of four standards. Similarly,
The high-speed transmission circuit 32 of the port 2 and the high-speed reception circuit 33 of the port 1 are connected by an IEEE1394 standard differential cable 57 at the time of inspection. At the time of inspection, the test control circuit 55 switches to an inspection mode using a plurality of ports, transmits high-speed signal data SpeedData_Tx by, for example, the high-speed transmission circuit 32 of the port 1, and transmits this high-speed signal data SpeedData_Tx to the differential cable outside the DUT 50. Port 2 in the DUT again via 57
The logic circuits 31 and 36 of each port are controlled so that the receiving circuit 33 receives the signals.

That is, in the present embodiment, the transmission and reception of a high-speed differential signal using a short-circuit structure between the output side of the transmission circuit 42 and the input side of the reception circuit 43 as in the fourth embodiment is performed. Instead, transmission and reception of the high-speed differential signal is performed by the DUT 5.
0 is looped back by an external differential cable 57.

Therefore, in the present embodiment, in the inspection mode, the differential cable 57 is used to temporarily output the high-speed differential signal transmitted from the transmission circuit 32 of one port to the external differential cable 57. The high-speed data signal included in the high-speed differential signal transmitted from the transmission circuit 32 is the same as that of the fourth embodiment because the reception circuit 33 of the other port receives the signal via the differential cable 57. Instead of being received as a high-speed strobe signal, it is received as it is as a data signal. Therefore, the expected value of the data signal may be stored in advance in the register 39 incorporated in the second logic circuit 36 of each port. Further, since the differential cable actually used during the normal operation of the DUT 50 is used, a more reliable guarantee of a high-speed differential signal can be achieved.

In the above description, the inspection enable signal Data_E is sent from the data generation device 11 of the inspection device 10.
Although n is generated, a configuration in which a low-speed signal pattern (test pattern) of 50 Mbps is generated and output to the DUT may be adopted. Further, a register for storing an expected value is provided in the second logic circuit in the DUT, and a low-speed signal obtained at the time of inspection is compared with the expected value of this register. However, the present invention is not limited to this. An expected value is stored in the inspection apparatus 10, a low-speed signal obtained at the time of inspection is output from the DUT to the inspection apparatus 10, and the inspection apparatus 10 compares the low-speed signal with the expected value. It is a thing.

[0062]

As described above, according to the first to seventh aspects of the present invention, a high-speed signal transmitted from a transmission circuit is received by its own reception circuit and converted into a low-speed signal. Even when testing a semiconductor integrated circuit that performs high-speed transfer, a high-speed comparator and a high-speed data generator of the testing device are not required, and testing using a low-cost testing device is possible.

In particular, according to the second and fourth aspects of the present invention, it is also possible to perform a drop test of a potential of a high-speed signal caused by a signal wiring length.

Further, according to the third aspect of the present invention, since the delay circuit forcibly creates the skew of the high-speed differential signal, the delay skew can be inspected.

In addition, according to the invention of claim 6, at the time of inspection, the transmission circuit of one port and the reception circuit of the other port are connected by a differential cable for inspection. It is possible to perform the inspection in almost the same situation as when using.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration when testing a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating an overall configuration when testing a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 3 is a diagram illustrating an overall configuration when testing a semiconductor integrated circuit according to a third embodiment of the present invention;

4A is a diagram illustrating a waveform of a test enable signal according to a third embodiment, FIG. 4B is a diagram illustrating a waveform of low-speed signal data stored in a register of a first logic circuit,
(C) is a diagram illustrating a high-speed differential signal waveform, (d) is a diagram illustrating a waveform of low-speed signal data converted by the second logic circuit in the fourth embodiment, and (e) is a diagram illustrating the third embodiment. FIG. 10 is a diagram showing a comparison result signal output from the second logic circuit in the embodiment to the inspection device.

FIG. 5 is a diagram illustrating an overall configuration when testing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating an overall configuration when testing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional test circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Inspection apparatus 11 Data generation apparatus 12 Comparator 20 and 30 Device under test (semiconductor integrated circuit) 21, 31 1st logic circuit 22, 32 High-speed transmission circuit 23, 33 High-speed reception circuit 24, 34 Switch circuit (switch means) 25, 35, 55 Test control circuit 26, 36 Second logic circuit 27 Signal wiring 28 Register D delay circuit 29 Potential control circuit 37 Differential signal wiring 39 Register (storage circuit) 57 Differential cable

Claims (8)

[Claims] A transmitting circuit for transmitting a high-speed signal having a high transfer rate; and a receiving circuit, wherein a low-speed signal having a low transfer rate is input from the external inspection device at the time of inspection connected to the external inspection device, A first logic circuit that generates a high-speed signal and outputs the high-speed signal to the transmission circuit; a signal line that connects the transmission circuit and the reception circuit; Switch means for transmitting a high-speed signal to be transmitted to the receiving circuit; and a second logic circuit for receiving the high-speed signal received by the receiving circuit and converting the high-speed signal into another low-speed signal. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said first logic circuit includes a potential control circuit for controlling a potential level of a generated high-speed signal to be higher or lower. 3. A transmission circuit for transmitting a high-speed differential signal having a high transfer rate, and a reception circuit, and a low-speed signal having a low transfer rate is input from the external inspection device at the time of inspection connected to the external inspection device. A first logic circuit that generates the high-speed differential signal and outputs the high-speed differential signal to the transmission circuit; a differential signal line including two lines connecting the transmission circuit and the reception circuit; A switch unit that is closed at the time of the inspection and sends a high-speed differential signal transmitted from the transmitting circuit to the receiving circuit; and a high-speed differential signal received by the receiving circuit is input. And a delay circuit that delays one of the two signals constituting the high-speed differential signal input to the second logic circuit. Characteristic semiconductor collection Product circuit. 4. The semiconductor integrated circuit according to claim 3, wherein said first logic circuit includes a potential control circuit for controlling a potential level of a generated high-speed differential signal to be higher or lower. 5. An inspection connected to an external inspection device,
A first logic circuit to which a signal having a low transfer rate is input from the inspection device and which generates and outputs a high-speed differential signal having a high transfer rate composed of a data signal and a strobe signal; and A transmission circuit for transmitting a high-speed differential signal; and a high-speed differential signal transmitted by the transmission circuit during the inspection.
A receiving circuit that exchanges and receives the data signal and the strobe signal, and receives the high-speed differential signal received by the receiving circuit, and converts the strobe signal included in the high-speed differential signal into a low-speed signal having a low transfer rate. A semiconductor integrated circuit, comprising: a second logic circuit configured to store the expected value of the low-speed signal converted by the second logic circuit. 6. A transmission circuit for transmitting a high-speed differential signal having a high transfer rate, and a reception circuit as one port, the transmission circuit and the reception circuit are provided in two ports, and the inspection circuit is connected to an external inspection device at the time of inspection. A first low-speed signal having a low transfer rate is input from an external inspection apparatus, and the first low-speed signal is generated to output the high-speed differential signal to the one set of transmission circuits.
The transmission circuit of the one port and the reception circuit of the other port are connected by a differential cable at the time of the inspection, and further transmitted from the transmission circuit at the time of the inspection to connect the differential cable. And a second logic circuit for converting the high-speed differential signal received by the receiving circuit into a low-speed signal having a low transfer rate. 7. A method for inspecting a semiconductor integrated circuit, comprising: a transmitting circuit for transmitting a high-speed signal having a high transfer rate; and a receiving circuit, comprising: receiving a low-speed signal having a low transfer rate, and generating the high-speed signal. Transmitting the generated high-speed signal from the transmission circuit, receiving the transmitted high-speed signal at the reception circuit, converting the received high-speed signal into a low-speed signal, and converting the converted low-speed signal into a low-speed signal. A method for inspecting a semiconductor integrated circuit, wherein the method is compared with an expected value of a low-speed signal. 8. A transmission circuit for transmitting a high-speed differential signal having a high transfer rate comprising a data signal and a strobe signal;
A method for testing a semiconductor integrated circuit comprising a receiving circuit, wherein the high-speed differential signal transmitted from the transmitting circuit is received by exchanging the data signal and the strobe signal, and a strobe signal of the received high-speed differential signal is provided. Is compared with an expected value of the strobe signal.