JP2000168171A - Printer and control thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively utilize a bus in a banding type printer. SOLUTION: An REPEAT signal, the repeated number of times of reading and the repeated number of times of output are set to a VIDEO register 104. During the setting of the REPEAT signal, a memory controller 101 executes the burst transmission of data to a data register 103 in the number of times designated on the basis of the repeated number of times of reading from a memory 100. An OUTPUT circuit 107 sends the data of the number of bites designated on the basis of the repeated number of times of output from the data register 103 to a printing part 208.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a printing apparatus having a function of printing one page by banding processing and a control method thereof.

[0002]

2. Description of the Related Art When a band is subjected to banding processing and printed, even if a certain band repeats the same print data at a fixed period, the transfer circuit prepares repetition data for one band and stores the data in a memory. Access to the printer and read and transfer the print data. At this time, for example, when the banding process is performed in two bands on the memory, if the transfer process of the current band is not completed, the print data of the next next band cannot be constructed, and the processing efficiency and the memory use efficiency are poor. Was.

[0003]

In particular, in general, the priority of the right to use the bus of the transfer circuit is high, and even though the repeated data can all be stored in the temporary storage means of the transfer unit, the data is repeatedly read. However, the transfer circuit occupies the bus, so that the bus efficiency is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional example. A flag for repeatedly outputting data is provided in a control register of a transfer circuit. Improve memory usage efficiency without going to access. If all data can be stored repeatedly in the temporary storage means of the transfer unit, stop access to memory when all data is read and increase printing efficiency. It is an object to provide an apparatus and a control method thereof.

[0005]

In order to achieve the above object, the present invention repeatedly reads data of a specified size from a memory while a flag indicating repetition is set, and repeats the reading of data from a memory. Output to the printing section repeatedly.
If the specified size is within the temporary memory size, no access is made to the memory.

[0006] Further, a means for inputting input data, a means for storing the input data and other data, a means for processing the input data to construct print data, and a means for storing print data stored in the storage means Means for partially reading, means for temporarily storing print data read by the reading means, means for transferring print data to a printing unit for actually printing, and printing data to be transferred to the printing unit. And a register for setting a flag that is repeated at a constant cycle.

Alternatively, a register for storing a printing section, a memory, a flag indicating repetitive reading from the memory, a size of data to be repeatedly read, and a size of data repeatedly output to the printing section, And a control unit for repeatedly reading data of the size to be repeatedly read from the memory while being set, and repeatedly outputting data of a size to be repeatedly output to the printing unit.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 shows an example of a system configuration in the present system. Reference numeral 200 denotes a CPU (central processing operator) that performs arithmetic processing. Reference numeral 201 denotes various buses (address, data, control). An input unit 202 receives print data from the outside. A RAM 203 is used to store print data taken in from the input unit and drawing data finally sent to the print unit, and a RAM used as a work area of the CPU.
(Random access memory). Reference numeral 204 denotes a ROM (Read Only Memory) for storing various data such as a CPU program and font data. Reference numeral 205 denotes a unit for processing the print data received from the unit 202 to generate drawing data. A memory control block 206 interfaces with a DMAC (Direct Memory Access Controller) and a memory. 20
A transfer unit 7 reads the drawing data stored in the RAM and sends it to the printing unit. A printing unit 208 prints out the drawing data from the transfer unit.

FIG. 1 shows a block configuration of a transfer unit according to the present invention. 100 is a memory such as a RAM and a ROM. Reference numeral 101 denotes a memory controller in a memory control unit, which arbitrates each RQ signal when an RQ signal (request signal) comes from a data request source as shown in the figure, and when it is determined, an address signal, a read / write signal, etc. Of the RQ source received at an appropriate timing.
Pass EN (data enable). The source that receives the DATAEN signal reads data from the memory or writes data to the memory based on the signal. Here, in the present embodiment, it is assumed that the address register of each request source exists in the memory controller 101, and that the address management such as the increment of the address is all performed by the memory controller. A portion surrounded by a dotted line in the center of FIG. 1 is a block diagram of a transfer unit related to the present invention. The INPUT circuit 102 is in charge of an interface with the memory controller 101, and is a circuit for writing print data from the memory to the data register 103. The VIDEO register 104 is a control register for starting the transfer unit and setting various modes. VI
The DEO sequencer 106 stores the VIDEO register 104
Are controlled in accordance with the mode set in (1). The OUTPUT circuit 107 functions to read the print data stored in the data register and transfer the print data to the print unit at an appropriate data width and transfer rate.

The printing apparatus according to the present embodiment is capable of outputting arbitrary data repeatedly to an arbitrary band, saving unnecessary memory consumption and processing, and improving each performance.

FIG. 3 shows band processing. The drawing areas 301 and 302 for two bands are provided on the memory, and the two bands are alternately processed to sequentially form and transfer the print data to the memory, thereby performing the printing process of one page. Specifically, assuming that the drawing data has already been constructed in the area 301, the transfer unit 207 sequentially transfers the drawing data to the reading and printing unit 208. During this time, the drawing unit 205 constructs drawing data in the next band.
By repeating this alternately, one page is output. Here, naturally, the number of bands may be an arbitrary number, and the bandwidth, height and start address of each band may be arbitrarily variable. Also, one page may be output as one band.

Is set in a VIDEO register 104,
The output REPEAT signal is a flag for repeatedly outputting data. As shown in FIG. 3, when the REPEAT signal is set in the VIDEO register 104 during the transfer processing of the band 301 by the transfer unit, this signal becomes valid after a band end signal indicating the end of the processing of the band is output. The next band repeats a certain range of data on the memory and is output as hardware. The method will be described with reference to FIG. In addition, REPE
The AT flag is set while the drawing unit 205 or the CPU 200 repeatedly outputs the data when it determines that the data expanded in the band memory is data to be repeatedly output.

REPEAT signal is VIDEO register 1
When set to 04, the VIDEO register 104 is enabled by the band end signal, and the REPEAT signal becomes valid from the next band. Normally, transfer unit 2
When 07 is activated, a handshake with the memory controller 101 is disclosed by the output of an RQEN signal (request enable) from the VIDEO sequencer 106 to the INPUT circuit 102. Where RE
When the PEAT signal is enabled, the INPUT circuit 10
REPEAT to memory controller 101 from 2
An EN signal is output.

FIG. 5 shows the exchange between the peripheral portion of the address register inside the memory controller 101 and the INPUT circuit 102 of the transfer section 207. Reference numeral 502 denotes an execution address register, which is a register for setting an address value when actually accessing the memory. The start address register 504 holds the start address of the execution address. By issuing the REPEATEN signal, an internal address set signal is given to the address register inside the memory controller 101, the internal address is set in the execution address register 502, and the same address is held in the head address register 504 at the same time.
The VIDEO register 104 includes, in addition to the PEPEAT signal, a register for setting the number of repetitive reads indicating how many times the memory is read from the memory and the number of repetitive outputs for the number of times (in this embodiment, the number of bytes) to be output to the printing unit 208. is there. The number of repetitions also depends on the amount of data to be repeated,
It is set by the CPU 200 and the drawing unit 205. The number of times of repetitive reading is passed to the INPUT circuit 102.

RQE to handshake block 505
When the N signal is enabled, the memory controller 10
The number of occurrences of the RQ signal issued to No. 1, that is, the number of accesses is output to the comparison circuit 506 of the number of times of repeated reading. When the access count matches the set repetition read count, a match signal is issued to the handshake block, and a SELECT signal and an ADDSET signal are output to the memory controller 101. The SELECT signal is a select signal of the selector 501 and the selector 503. The selector 501 is the memory controller 101
Internal address set bus and start address register 50
4 output buses. The selector 503 selects an internal address set signal for setting the execution address register 502 and an ADDSET signal.
When the access count matches the read count, SE
The LECT signal and the ADDSET signal are issued from the handshake block 505, the start address register 504 is selected by the selector 501, the start address held there is set in the execution address register 502, and access is started again from the start address. .

This operation is repeated until the processing of the current band is completed. This is shown in FIG. In this embodiment, the transfer unit 207 stores the data register 10
As No. 3, data registers for eight words regA and regB are provided, and it is assumed that one access is a burst access in units of four words. Here, if 5 is set as the number of times of repeated reading, that is, if access is performed 5 times and 20 words are read, the coincidence signal is compared when the RQ signal is output to capture the data 5 of FIG. The number of accesses output from the circuit 506 and output from the handshake block 505 is initialized to 1, the head address is set again in the execution address register 502 by the mechanism described above, and data 1 is read into regB again. If the number of times of repeated reading is 2 or less, the data to be repeated is
All fit in A, regB. Therefore, the VIDEO sequencer 106 determines the number of times of repetitive reading. If the number is less than 2, the RQEN signal for less than 2 times is issued to disable, and no further access is performed.

Next, the output side of the print data will be described. FIG.
, The data stored in regA and regB are cut out by selectors 402 and 403 and finally
The data width to be passed to 08 is processed to 8 bits. The selection signal of each selector is selected by a cutout counter 404 (a 5-bit counter in this embodiment) that counts the number of bytes sent to the printing unit. The extraction counter 404 is provided in the VIDEO sequencer 106 shown in the lower part of FIG.
Is controlled by VIDEO sequencer 106
The comparison circuit 405 compares the number of repetitions output from the VIDEO register 104 with the count value of the cutout counter 404. If they match, the lower 4 bits of the counter are reset. Describing the data register 401 in FIG.
When the repeated output data is completed in the middle (separated by the solid line), a coincidence signal of the number of repeated outputs is generated. As a result, the lower 4 bits of the cutout counter 404 are reset, and in the next output, cutout of print data is started from regB in which data 1 which is the head of repeated data is stored.

As described above, by the REPEAT signal and the number of repetitive readings, the data having the length designated by the number of repetitive readings can be repeatedly read out from the band memory as long as the REPEAT signal is set. If the data to be read from the band memory is stored in the data register,
While the REPEAT signal is set, no data is read from the band memory. Also, by designating the number of times of repeated output, data of the designated number of bytes can be repeatedly output to the printing unit and printed out.

As described above, when the data of the repetitive band memory is used, the data can be used repeatedly without rewriting the contents of the band memory. Memory access can also be suppressed. In addition, if the data amount can be accommodated in the data register, even the memory access is not performed, so that the bus use efficiency is further improved.

It is to be noted that each of the above-mentioned registers has a corresponding second register, and if the setting is performed on the second register during the transfer processing of a certain band, the second band register is set after the end of the current band transfer processing. The contents may be copied from the second register to the first register, and the set values thereof may be made effective in the next band processing. By doing so, the setting for the next band can be made in advance during the processing of a certain band, so that the processing can be advanced promptly.

[0022]

As described above, the flag for the repeated data output is provided, and for the band in the section where this flag is active, only the memory for the repeated data is accessed, and the memory use efficiency is increased. Further, when all the data is repeatedly stored in the temporary storage of the transfer unit, the access to the memory can be stopped when all the data is read, thereby increasing the bus use efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a transfer unit.

FIG. 2 is a block diagram of a printing apparatus.

FIG. 3 is a diagram illustrating an example of a banding process.

FIG. 4 is a diagram showing a relationship between repeated reading and output and each block.

FIG. 5 is a diagram showing a configuration and operation for a repetitive lead.

Claims (8)

[Claims] A means for inputting input data; a means for storing the input data and other data; a means for processing the input data to construct print data; and a means for storing print data stored in the storage means. Means for partially reading, means for temporarily storing print data read by the reading means, means for transferring print data to a printing unit for actually printing, and print data to be transferred to the printing unit. A register for setting a flag that repeats at a constant cycle. 2. The printing data to be transferred to a printing unit,
Means for dividing a page into any positive number of bands, including a register for holding the number of dots in one line, a register for holding the number of lines, and a counter for counting the number of dots and the number of lines; An arbitrary positive number of bands is provided in the storage means, and banding processing means for sequentially performing parallel printing data construction processing and transfer processing to print one page, and a second register for each of the registers are provided. If the setting is made to the second register during the transfer processing of a certain band, after the current band transfer processing is completed, the data is copied from the second register to the first register, and the set values are transferred to the next band processing. The printing apparatus according to claim 1, further comprising a unit that is more effective. 3. A register for holding a head address read from the storage means and a register for holding the number of times of repetitive reading, a means for starting reading processing again from the held head address when the repetition of the number of times of reading is completed. 3. The printing apparatus according to claim 2, further comprising: means for determining whether all print data can be stored in the temporary storage means. 4. A register for holding the number of repetitive outputs for outputting the same data in a certain period by the transfer means, and after the repetition of the number of repetitions, from the beginning of the print data stored in the temporary storage means again. 4. The printing apparatus according to claim 3, further comprising means for starting output. 5. A printing unit, a memory, a register for storing a flag indicating repetitive reading from the memory, a size of data to be repeatedly read, and a size of data repeatedly output to the printing unit; While the setting is being performed, control means for repeatedly reading data of the size to be repeatedly read from the memory and repeatedly outputting data of the size to be repeatedly output to the printing unit is provided. Printing device. 6. The control section has a register for temporarily storing data read from the memory, and when the size of the repeatedly read data is equal to or smaller than the size of the register, the control section reads the data from the memory. The printing apparatus according to claim 5, wherein reading is not performed. 7. A step of inputting input data, a step of storing the input data and other data in a memory, a step of processing the input data to construct print data, and a step of storing print data. A step of reading a part of the print data; a temporary storage step of temporarily storing the print data read in the reading step; a step of transferring the print data to a printing unit for actually printing; and the printing unit A setting step of setting a flag that is repeated at a certain cycle for the print data to be transferred to the printing apparatus. 8. A setting step of setting, in a register, a flag indicating that data is repeatedly read from a memory, a size of data that is repeatedly read, and a size of data that is repeatedly output to the printing unit, and while the flag is set. And a control step of repeatedly reading data of the size that is repeatedly read from the memory and repeatedly outputting data of the size that is repeatedly output to the printing unit.