JP2000166227A - Overcurrent protection circuit for switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time from the detection of overcurrent to the drop of output. SOLUTION: FET 1 switches input voltage Vin by the control of a P-WM controller 2 and converts it into pulse voltage. A comparison detection circuit 5 detects overcurrent based on primary side current Id flowing in a resistor 4. A lath circuit 6 repeats the off-control of FET and resetting for releasing off-control in synchronizing with the switching frequency of a switching power source when the comparison detection circuit 5 detects overcurrent. A time constant circuit 7 invalidates the resetting of the latch circuit 6 and maintains the off-control of FET 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an overcurrent protection circuit for a switching power supply.

[0002]

2. Description of the Related Art Conventionally, an overcurrent protection circuit for performing pulse-by-pulse control has been known as an overcurrent protection circuit for a switching power supply. In such an overcurrent protection circuit,
When overcurrent is detected, the current is limited by shortening the ON time of the switching element, and the power supply is shut down when the output voltage is sufficiently reduced due to the current limitation.

[0003]

However, in the above-described conventional overcurrent protection circuit, the time from the detection of the overcurrent to the complete dropping of the output voltage is lengthened, thereby causing damage to the power supply circuit and the load device. In addition, there is a problem that there is a danger of falling into smoke and ignition. The present invention
An object of the present invention is to provide an overcurrent protection circuit that can perform the time from overcurrent detection to output droop in a relatively short time.

[0004]

According to the overcurrent protection circuit of the present invention, an input voltage (Vin) is switched by a switching element (1) to convert the input voltage (Vin) into a pulse voltage. Rectify voltage and output voltage (Vout)
(5) a comparison detection circuit (5) for detecting an overcurrent based on a primary current flowing through a current detection resistor (4) connected in series with the switching element
And a latch circuit (6) that repeats, in synchronization with the switching frequency of the switching power supply, off control of the switching element and reset for releasing the off control when an overcurrent is detected by the comparison detection circuit. A time constant circuit (7) for invalidating the reset of the latch circuit and maintaining the OFF control of the switching element when the predetermined time has elapsed. Claim 2
And a second time constant circuit (8) for releasing the off control by the time constant circuit when the output voltage does not become lower than the reference voltage even by the off control of the switching element.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram of a switching power supply showing a first embodiment of the present invention. Power MOSFET 1 (hereinafter FE)
T) converts the input voltage Vin into a high-frequency pulse voltage by switching.

The PWM controller 2 compares an output feedback voltage Fb, which will be described later, with a triangular wave voltage Tr generated by its own oscillator, and changes the pulse width of a control pulse signal to turn on / off the FET 1 according to the comparison result. The output voltage Vout is controlled to be constant by changing the time. The driver 3 drives the FET 1 according to a control pulse signal output from the PWM controller 2.

Reference numeral 4 denotes a resistor for detecting the primary current Id. The comparison detection circuit 5 detects an overcurrent by comparing a detection voltage Det, which is a voltage drop by the resistor 4, with a predetermined reference voltage. The latch circuit 6 outputs an off control signal Coff for forcibly turning off the FET 1 when an overcurrent is detected by the comparison detection circuit 5, and outputs an off control signal in response to the latch reset signal Rr output from the PWM controller 2. The output of Coff is stopped.

[0008] The time constant circuit 7 outputs a latch reset invalidation signal Iv for invalidating the reset of the latch circuit 6 when the overcurrent state continues for a predetermined time or more. Transformer 9
Insulates the primary side (input) from the secondary side (output) and transmits the primary side pulse voltage to the secondary side.

[0009] Diodes 10 and 11, choke coil 1
The capacitor 2 and the capacitor 13 rectify and smooth the pulse voltage generated on the secondary side of the transformer 9 and convert it to a DC output voltage Vout. The resistors 14 and 15 divide the output voltage Vout to generate an output feedback voltage Fb. In the switching power supply as described above, the resistor 4, the comparison detection circuit 5, the latch circuit 6, and the time constant circuit 7 constitute an overcurrent protection circuit.

FIG. 2 is a circuit diagram of the PWM controller 2, the comparison detection circuit 5, the latch circuit 6, and the time constant circuit 7. Note that only part of the PWM controller 2 is described. The comparator 51 in the comparison detection circuit 5 compares the detection voltage Det based on the primary side current Id with a reference voltage Vref1 for detecting an overcurrent, and the comparator 52 similarly detects the detection voltage Det based on the overcurrent. With the reference voltage Vref2.

The NOR gate 53 includes a comparator 51,
The output of the inverter 52 is NORed, and the inverter 54 outputs N
The output of the OR gate 53 is logically inverted. Thus, the output of the inverter 54 is input as the latch set signal Rs to the set terminal S of the flip-flop (hereinafter abbreviated as F / F) 61 configuring the latch circuit 6.

On the other hand, a comparator 21 in the PWM controller 2 compares the triangular wave voltage Tr with a reference voltage Vref3. The AND gate 22 calculates the logical product of the output of the NOR gate 53 and the output of the comparator 21. Thus, the output of the AND gate 22 becomes the latch reset signal Rr.
Is input to the reset terminal R of the F / F 61.

The F / F 61 is set when a latch set signal Rs is output from the comparison detection circuit 5.
At this time, the inverted output signal output from the inverted output terminal bar Q of the F / F 61 becomes the off control signal Coff. On the other hand, the normal output signal P output from the normal output terminal Q of the F / F 61 is applied to the base of the transistor 71 in the time constant circuit 7.

A power supply voltage VCC is applied to one end of the resistor 72, and the other end of the resistor 72 is connected to one end of a capacitor 73. The connection point between the resistor 72 and the capacitor 73 is connected to the collector of the transistor 71 and the constant voltage diode 7.
4 cathodes are connected. Further, the anode of the constant voltage diode 74 is connected to the input of the inverter 75.
Thus, the output of the inverter 75 becomes the latch reset invalidation signal Iv.

Next, the operation of the switching power supply according to this embodiment will be described with reference to FIG. In a normal state where no overcurrent occurs, the detection voltage Det generated in the resistor 4 by the primary current Id is equal to the reference voltages Vref1 and Vref.
2 or less. Therefore, the outputs of the comparators 51 and 52 are both at the “L” level, and the latch set signal Rs output from the inverter 54 is also at the “L” level as shown in FIG.

As a result, the off control signal Coff output from the F / F 61 remains at the "L" level.
Pulse-by-pulse control for forcibly turning off ET1 is not performed. That is, the FET 1 is turned on / off determined by comparing the output feedback voltage Fb and the triangular wave voltage Tr.
Controlled by off time.

Next, when an overcurrent occurs on the secondary side of the switching power supply, the primary side current Id increases, and as a result, the detection voltage Det changes to the reference voltage Vr at time T1 in FIG.
ef1 and Vref2 are reached. As a result, at least one of the outputs of the comparators 51 and 52 becomes “H” level, so that the latch set signal Rs is inverted to “H” level.

F / F according to latch set signal Rs
61 is set, and the off control signal Coff is inverted to the “H” level. The driver 3 is turned off and the FET 1 is turned off in response to the off control signal Coff.

On the other hand, the comparator 21 in the PWM controller 2 compares the triangular wave voltage Tr with the reference voltage Vref3. Here, the triangular wave voltage Tr is equal to the reference voltage Vref.
When the value falls below 3, the output of the comparator 21 is inverted to the “H” level. At this time, since the output of the NOR gate 53 is at the “H” level, the latch reset signal Rr output from the AND gate 22 is inverted to the “H” level. The F / F 61 is reset in response to the latch reset signal Rr, and the off control signal Coff is inverted to “L” level,
The off control of the FET 1 is reset.

Thus, when an overcurrent occurs, the FET1
And the resetting of the off control is performed by the triangular wave voltage T.
A so-called pulse-by-pulse control, which is repeated every r cycle (switching cycle of the switching power supply), is performed to limit the current.

Next, when the off control signal Coff is at the "H" level, the latch non-inverting output signal P output from the non-inverting output terminal Q of the F / F 61 is at the "L" level. Transistor 71 is off. In this case, the capacitor 73 is charged by a charging current from the power supply voltage VCC via the resistor 72. On the other hand, during the period in which the off control signal Coff is at the “L” level, since the latch normal output signal P is at the “H” level, the transistor 71 is turned on and the capacitor 73 is discharged.

When the overcurrent state continues, the latch normal output signal P output from the F / F 61 is inverted to "L" every time an overcurrent is detected, and the capacitor 73 is charged. Following the charging of the capacitor 73, the capacitor 73 is discharged by resetting the off control. Since the next charging starts before the discharging is completed, the terminal voltage of the capacitor 73 gradually increases.

When the terminal voltage of the capacitor 73 reaches the Zener voltage of the constant voltage diode 74, the anode of the constant voltage diode 74 is inverted to the "H" level, so that the latch reset invalidation signal Iv output from the inverter 75 is output. Is inverted to the “L” level (at time T in FIG. 3).
2).

As a result, one input of the AND gate 22 is always at "L" level, so that the latch reset signal Rr always remains at "L" level. Therefore, the F / F 61 which has been set by the latch set signal Rs immediately before the time T2 maintains the set state without being reset, and the "H" level off control signal Coff
, Is kept off.

As described above, in the overcurrent protection circuit of this embodiment, when the overcurrent state continues for a predetermined time or more, the latch reset signal Rr input to the latch circuit 6 is invalidated, and the FET 1 is forcibly turned off. By continuing the state, the output voltage Vout can be drooped quickly.

In the overcurrent protection circuit of the present embodiment, as can be seen from FIG. 3, when a large overcurrent is continuously generated, the pulse width of the off control signal Coff (the latch non-inverting output of the "L" level) The pulse width of the signal P) gradually increases, accelerating the charging of the capacitor 73, and setting the output voltage Vo
It works to make ut droop quickly.

The reason why the charging of the capacitor 73 is accelerated is that the latch set signal Rs is generated based on the detection voltage Det, and the off control signal Co is generated based on the latch set signal Rs.
This is because ff is generated. That is, when the output voltage Vout starts to decrease by the pulse-by-pulse control, the on-timing of the FET 1 determined by comparing the output feedback voltage Fb and the triangular wave voltage Tr becomes earlier than usual, and the latch set signal Rs becomes “H The timing of inversion to "becomes earlier. On the other hand, the output timing of the latch reset signal Rr based on the comparison between the triangular wave voltage Tr and the reference voltage Vref3 does not change. As a result, the pulse width of the off control signal Coff increases, and the charging of the capacitor 73 is accelerated.

[Embodiment 2] FIG. 4 is a circuit diagram of a switching power supply showing a second embodiment of the present invention, and the same components as those in FIG. 1 are denoted by the same reference numerals. In the switching power supply of the present embodiment, a time constant circuit 7a in which the predetermined time is shorter than the time constant circuit 7 is provided instead of the time constant circuit 7, and the output voltage V is also controlled by the off control.
When out does not become lower than the reference voltage, the time constant circuit 7a
And a second time constant circuit 8 for canceling the off control by the control circuit.

FIG. 5 is a circuit diagram of the PWM controller 2, the comparison detection circuit 5, the latch circuit 6, and the time constant circuits 7a and 8. As in FIG. 2, only part of the PWM controller 2 is described. The normal rotation output signal P output from the normal rotation output terminal Q of the F / F 61 is
a to the base of the transistor 71a.

The power supply voltage VCC is applied to one end of the resistor 72a, and the other end of the resistor 72a is connected to one end of the capacitor 73a. The connection point of the resistor 72a and the capacitor 73a is connected to the collector of the transistor 71a and the cathode of the constant voltage diode 74a. Further, the anode of the constant voltage diode 74a is connected to the input of the inverter 75a.

The transistor 81 in the second time constant circuit 8
Is connected to the output of inverter 75a. The power supply voltage VCC is applied to one end of the resistor 82 and the resistor 82
Is connected to one end of the capacitor 83. And
The connection point between the resistor 82 and the capacitor 83 is connected to the collector of the transistor 81 and the cathode of the constant voltage diode 84. Further, the anode of the constant voltage diode 84 is connected to one input of the AND gate 86.

The comparator 85 compares the output feedback voltage Fb with the reference voltage Vref4. The output of the comparator 85 is connected to the other input of the AND gate 86. The output of the AND gate 86 is connected to the base of the transistor 87, and the collector of the transistor 87 is connected to the collector of the transistor 71a.

In the switching power supply described above, the pulse-by-pulse control is performed in the same manner as in the first embodiment, and when the overcurrent state continues for a predetermined time or more, the time constant circuit 7a
Invalidates the latch reset signal Rr by the FET
The forced off state of No. 1 is continued. The operation up to this point is the same as that of the first embodiment except that the predetermined time is shorter than that of the first embodiment.

Next, while the latch reset invalidation signal Iv is at the "H" level, the transistor 81 is turned on and the capacitor 83 is discharged. In addition, while the latch reset invalidation signal Iv is at the “L” level, the transistor 81 is turned off, and the capacitor 83 is charged by the charging current from the power supply voltage VCC via the resistor 82.

When the overcurrent state continues for a predetermined time or more, the latch reset invalidation signal Iv becomes "L" level, so that the capacitor 83 is charged. And
When the "L" level latch reset invalidation signal Iv is continuously output and the terminal voltage of the capacitor 83 reaches the zener voltage of the constant voltage diode 84, the anode of the constant voltage diode 84 is inverted to "H" level. . On the other hand, when the output feedback voltage Fb is higher than the reference voltage Vref4, the comparator 85 outputs an “H” level signal.

Therefore, the FET using the time constant circuit 7a
1 continues for more than the time set by the time constant circuit 8, and the output feedback voltage Fb becomes equal to the reference voltage Vre.
If f4 or less, the output of AND gate 86 is inverted to "H" level. Thereby, the transistor 8
7 is turned on, the capacitor 73a is discharged, and the latch reset invalidation signal Iv is inverted to "H" level.
The off control by the time constant circuit 7a is released. With the above configuration, a reliable current limiting operation can be performed even for a relatively short overcurrent.

[0037]

According to the present invention, as described in claim 1, when the overcurrent state continues for a predetermined time or more, the reset of the latch circuit is invalidated, and the off control of the switching element is maintained. Accordingly, the primary current can be completely cut off in a relatively short time after the occurrence of the overcurrent, and it is possible to prevent the occurrence of troubles such as smoke and ignition due to a delay in the protection operation. The reason is that when the occurrence of overcurrent is detected, a general pulse-by-pulse current limiting operation is performed first, and when the overcurrent state continues for a predetermined time or longer, the reset of the latch circuit is invalidated and the primary side current is reduced. This makes it impossible to recover the output voltage and speeds up the droop of the output voltage.

According to a second aspect of the present invention, when the output voltage does not become lower than the reference voltage even by the off control of the switching element, a second time constant circuit for releasing the off control of the switching element is provided. A reliable current limiting operation can be performed even for a relatively short overcurrent.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a switching power supply showing a first embodiment of the present invention.

FIG. 2 shows a PWM controller, a comparison detection circuit,
It is a circuit diagram of a latch circuit and a time constant circuit.

FIG. 3 is a timing chart for explaining the operation of the switching power supply of FIG. 1;

FIG. 4 is a circuit diagram of a switching power supply showing a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a PWM controller, a comparison detection circuit,
It is a circuit diagram of a latch circuit and a time constant circuit.

[Explanation of symbols]

1. Power MOSFET, 2. PWM controller, 3.
... Driver, 4, 14, 15 ... Resistance, 5 ... Comparison detection circuit, 6 ... Latch circuit, 7, 7a, 8 ... Time constant circuit, 9 ...
Transformers, 10, 11 ... diodes, 12 ... choke coils, 13 ... capacitors.

Claims (2)

[Claims] 1. A switching power supply that switches an input voltage by a switching element to convert the input voltage into a pulse voltage, rectifies the pulse voltage and obtains an output voltage, wherein a primary current flowing through a current detection resistor connected in series with the switching element is provided. A comparison detection circuit for detecting an overcurrent based on the side current, and, when an overcurrent is detected by the comparison detection circuit, synchronizing an off control of the switching element and a reset for releasing the off control with a switching frequency of the switching power supply. And a time constant circuit that disables resetting of the latch circuit and maintains off control of the switching element when an overcurrent state continues for a predetermined time or more. Overcurrent protection circuit. 2. The overcurrent protection circuit for a switching power supply according to claim 1, wherein when the output voltage does not become equal to or lower than the reference voltage by the off control of the switching element, the off control by the time constant circuit is released. An overcurrent protection circuit for a switching power supply, comprising a time constant circuit.