JP2000165761A - Receiver for digital broadcasting - Google Patents

Abstract

PROBLEM TO BE SOLVED: To share a mother board in a receiving device for receiving digital CATV broadcasting or satellite broadcasting or the like. SOLUTION: A front end circuit 121 which houses any circuit board individual for receiving CATV broadcasting and satellite broadcasting in a specified shared shield case body 131 is provided with two terminal columns 123 and 124 corresponding to each function for CATV and satellite broadcasting. At a mother board 122 side, a demodulating circuit for demodulating a transport stream is shared, and circuits individual for CATV and satellite broadcasting are formed. Therefore, even when the kind of the front end circuit 121 is different, the mother board 122 can be shared. Thus, developing efficiency can be improved, and the front end circuit 121 can be prevented from being made large for mother board sharing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for receiving a television broadcast in which digitally compressed video and audio signals are digitally modulated and transmitted.

[0002]

2. Description of the Related Art Analog video and audio signals are digitized, and the compressed data is subjected to QAM modulation or QAM.
Conventionally, transmission after digital modulation such as PSK modulation has been considered. Due to advances in semiconductor technology and digital image compression technology, digital television broadcasting can accommodate more programs, even in the same frequency band, than conventional analog television broadcasting. Services have been started with cable television (CATV) and satellite broadcasting.

FIG. 4 is a block diagram showing an electrical configuration of a general CATV broadcast receiving tuner 1 for receiving the QAM-modulated digital broadcast. VH from cable
The high-frequency signals of F and UHF are input from the antenna input terminal 2 and are fixed-frequency band-pass filters (hereinafter, referred to as “band-pass filters”).
In the BPF (abbreviated as BPF) 3, all the received frequency band components are extracted and then amplified by the amplifier circuit 5. The high-frequency signal received from the amplifier circuit 5 is input to the tuning / detection stage in the tuner 1 via the directional coupler 6, and is sent out from the external output terminal 7 to an external circuit.

In the tuning / detection stage, a received high-frequency signal is transmitted through switches 11, 21 and 31 to a BP
These are input to F12, F22, F32. As described below, V
When receiving the HFlow channel, the switch 11 is turned on. When receiving the VHF high channel, the switch 21 is turned on.
Is turned on and the switch 31 is turned on when receiving the UHF channel.
Is conducted.

The BPF 12 serves as a VHF low band input tuning circuit. The output of the BPF 12 is limited to a predetermined level range in the high frequency amplifier circuit 13, and then the BPF 14 becomes a VHF low band interstage tuning circuit. Is input to the mixing circuit 15. The BPF1
A tuning voltage from a PLLIC 41 to be described later is given to the circuits 2 and 14 and controlled so that a tuning frequency matches a signal component of a desired tuning channel. An AGC voltage corresponding to the received signal level is given to the high-frequency amplifier circuit 13 from a QAM demodulation IC 42 described later, and the level of the received high-frequency signal is limited to the predetermined level range. The mixing circuit 15 includes the PLLIC 41
And a local oscillation signal from a local oscillation circuit 16 forming a closed loop. The intermediate frequency signal of a predetermined frequency band created by the mixing circuit 15 is passed through an amplification circuit 43 and a band-limiting filter 44, It is input to the two-mixing circuit 45.

[0006] Similarly, the VHFhi from the BPF 22 is
The gh channel received high-frequency signal is supplied to the high-frequency amplifier 23
The signal is supplied to the mixing circuit 25 via the BPF 24 and mixed with the local oscillation signal from the local oscillation circuit 26 to be converted into an intermediate frequency signal, and then output from the first mixing circuit 40. The UHF channel received high-frequency signal from the BPF 32 is input from the high-frequency amplifier circuit 33 to the mixing circuit 35 via the BPF 34, mixed with the local oscillation signal from the local oscillation circuit 36, and converted into an intermediate frequency signal. , From the first mixing circuit 40.

In the second mixing circuit 45, the intermediate frequency signal is amplified by an intermediate frequency amplifying circuit 46, mixed with a local oscillation signal from a local oscillation circuit 48 in a mixing circuit 47, The signal is input to the QAM demodulation IC 42 via an amplifier circuit 50.

In the QAM demodulation IC 42, the intermediate frequency signal is digitally converted by an analog / digital converter 51, and a QAM demodulation circuit 52 and an error correction circuit 5
Demodulated into a digital signal error-corrected by 3;
The data is output from the output terminal 54 to a digital demodulation circuit at a subsequent stage as a transport stream. The operations of the analog / digital converter 51, the QAM demodulation circuit 52, and the error correction circuit 53 are controlled by a control circuit 55. The QAM demodulation IC 42 is supplied with data of a reception channel from a microcomputer (not shown) via a terminal 56. The data is written into a register (not shown), and
The data is input to the PLLIC 41. PLLIC41 is
According to the data, the switches 11, 21, 31
Of the local oscillation circuits 16, 26, and 36 and the BPFs 12, 1
4; 22, 24; 32, 34.

FIG. 5 is a block diagram showing an electrical configuration of a general satellite broadcast receiving tuner 71 for receiving the digital broadcast modulated by QPSK. A 10 GHz band signal from the satellite is converted to a frequency of about 1 GHz by a low noise block down converter (LNB) (not shown) and is provided to an antenna input terminal 72. The received high frequency signal is amplified via a high pass filter 73. The output from the amplifying circuit 74 is
The signal is supplied to the subsequent circuit via the directional coupler 75, and is output from the transmission terminal 76 as a transmission output.

The LNB is supplied with a DC power supply voltage supplied from a terminal 105. Therefore, a DC cut capacitor 106 is interposed between the input terminal 72 and the high-pass filter 73, and similarly, A DC cut capacitor 107 is also interposed between the sex coupler 75 and the sending terminal 76.

The high-frequency signal received from the directional coupler 75 is supplied to an attenuation circuit 77 and a high-frequency amplification circuit 78.
The level is limited to a predetermined level range in accordance with the AGC voltage from the I and Q demodulation circuits 79 at the subsequent stage, and is input to the mixing circuit 81 via the tracking filter 80. Mixing circuit 8
In 1, the received high-frequency signal is mixed with a local oscillation signal from the local oscillation circuit 82, and is converted into an intermediate frequency signal of a predetermined frequency (a center frequency of 479.5 MHz). The intermediate frequency signal is limited to a predetermined band range by an intermediate frequency amplifying circuit 83, an intermediate frequency filter 84, and an intermediate frequency amplifying circuit 85, and is amplified to a predetermined level before being input to the I and Q demodulation circuits 79. You.

In the I / Q demodulation circuit 79, the intermediate frequency signal is controlled to a predetermined level range by an amplification circuit 87 whose gain is controlled by an AGC control circuit 86.
Further, the two mixing circuits 89 and 9 are connected via an amplification circuit 88.
Input to 0. The oscillation circuits 9 are provided in the mixing circuits 89 and 90.
Oscillation signals from 1 are supplied via the phase shifter 92 at phases different from each other by 90 degrees. The signal separated into the I component and the Q component in this way passes through an amplifier circuit 93, a BPF 94, and an amplifier circuit 95, and an amplifier circuit 96, a BPF 97, and an amplifier circuit 98, respectively.
Given to.

A tuning signal from the microcomputer is supplied to the QPSK demodulation circuit 99 via a terminal 100. The tuning signal is written into a register (not shown) and is transmitted via a line 101. To the PLL circuit 102. The PLL circuit 102 generates a control voltage in response to the tuning signal so that the oscillation frequency of the local oscillation circuit 82 becomes a frequency corresponding to the reception channel. The trap frequency is supplied to the oscillation circuit 82 and to the tracking filter 80 to change the trap frequency. From the QPSK demodulation circuit 99, the output terminal 1
At 04, the transport stream subjected to QPSK demodulation is output.

FIGS. 6 and 7 show the tuners 1 and 7 respectively.
1 is a schematic front view for explaining a signal flow in FIG. In FIGS. 6 and 7, portions corresponding to the configurations in FIGS. 4 and 5 are denoted by the same reference numerals. CATV tuner 1
, The received high-frequency signal input from the antenna input terminal 2 is amplified by the preamplifier circuit block 61,
Via an input stage block 62 and an interstage block 63,
The signal is input to the mixing circuit block 64. The mixing circuit block 64 converts the received high-frequency signal into an intermediate frequency signal according to the local oscillation signal from the local oscillation circuit block 65 and supplies the intermediate frequency signal to the demodulation circuit block 66. The demodulation circuit block 66 is converted into a transport stream in the demodulation circuit block 66 including the intermediate frequency amplification circuit, the second frequency conversion circuit 45, the QAM demodulation circuit 42, and the like, and is output from the output terminal 54. The CATV tuner 1 is housed in a housing 67. One side of the CATV tuner 1 is provided with the output terminal 54 and the remaining input / output terminal 68.
Are arranged on a straight line.

In the satellite broadcast tuner 71, a received high-frequency signal input from an antenna input terminal 72 is amplified in an amplification block 111, and the frequency conversion block 112
In, the signal is subjected to attenuation and tracking filtering, mixed with a local oscillation signal from the oscillation circuit block 113, and converted into an intermediate frequency signal. The intermediate frequency signal is band-limited in a filter block 114, converted into I and Q signals in an I / Q demodulation block 115, analog / digital converted in a demodulation block 116, and QPSK demodulated. The output stream is output from the output terminal 104 as a transport stream. This satellite broadcast tuner 71 has a housing 117.
The output terminal 104 and the remaining input / output terminal 118 are arranged on one side in a straight line.

[0016]

The tuners 1 and 71 configured as described above receive a digital broadcast and convert both into a transport stream. However, in accordance with the modulation method and the transmission medium, each block is optimally arranged so that signal interference does not occur between them, and accordingly, as shown in FIG. 6 and FIG. In addition, the circuit layout is greatly different. Therefore, the arrangement and function of some of the terminals 54, 68; 104, 118 are different from each other. Here, Table 1 shows the terminal arrangement of the CATV tuner 1 and the satellite broadcast tuner 71.

[0017]

[Table 1]

Although the terminal arrangement and the number of terminals are equal to each other as shown in Table 1, for example, the terminal No. The terminal 6 is an external AGC voltage output in the CATV tuner 1, whereas the terminal LN in the satellite broadcast tuner 71 is
B is a clock pulse to B, and their functions are different from each other. Similarly, the terminal No. The terminals 10 and 13 also have different functions.

Therefore, in order to produce a television receiver, it is necessary to separately produce substrates for demodulating video and audio signals from the transport stream such as a motherboard, which has a problem of low development efficiency. In addition, in order to use a common substrate, it is necessary to provide the tuner portion with both functions of receiving CATV and receiving satellite broadcasting, and there is a problem that the front-end circuit becomes large.

An object of the present invention is to provide a digital broadcast receiving apparatus that can share a substrate on which a demodulation circuit is mounted for a plurality of types of front-end circuits.

[0021]

According to a first aspect of the present invention, there is provided a digital broadcast receiving apparatus comprising: a front end circuit which is housed in a predetermined housing and converts an input high-frequency signal into a signal to be digitally demodulated; In a digital broadcast receiving device configured to be mounted on at least a substrate on which a demodulation circuit is mounted, the front-end circuit side has at least one of a plurality of terminal functions corresponding to a plurality of different circuit layouts. It is characterized in that terminal rows partially different from each other are arranged in parallel with each other, and a pattern corresponding to each terminal row is formed on the substrate side.

According to the above configuration, when the types of front end circuits are, for example, a CATV reception front end circuit using QAM modulation and a satellite broadcasting reception front end circuit using QPSK modulation, On the front end circuit side, two rows of terminals corresponding to the respective front end circuits are formed, and the circuit actually housed in the housing is for the CATV or for satellite broadcasting. Depending on what, one of them will be used. Of course, at least a part of the two terminal rows is assigned to different functions, and correspondingly, on the board side on which a demodulation circuit such as a motherboard is mounted, a pattern corresponding to each of the two terminal rows is provided. Are formed.

For example, when the CATV front-end circuit is mounted, a circuit related only to satellite broadcasting is not used on the motherboard side. Similarly, a front-end circuit for satellite broadcasting is mounted. In this case, the circuit related to only the CATV is not used on the motherboard side. However, even if the type of the front-end circuit is different, the circuit for demodulating the video and audio signals from the transport stream is common, so that the development efficiency can be improved by sharing the motherboard, and the front-end circuit has It can be specific to the system or transmission medium and can be as small as necessary.

The digital broadcast receiving apparatus according to the second aspect of the present invention is characterized in that terminals having the same function are shared among a plurality of terminal rows.

According to the above configuration, it is only necessary to provide one set of terminals having mutually equal functions and a set of terminals having mutually different functions for each front-end circuit, thereby reducing the number of terminals. And cost and circuit space can be reduced.

Further, in the digital broadcast receiving apparatus according to the third aspect of the present invention, the terminal row on the board side is two rows, and the front end circuit side has a surface of the board or a board corresponding to its circuit layout. The terminal row is attached to one of the back surfaces.

According to the above configuration, although two terminal rows are formed on the substrate side, one terminal row may be provided on the front end circuit side, so that the cost of the terminals can be reduced and the terminal cost can be reduced. It is possible to effectively use the space of the board on which the is not mounted.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIG.

FIG. 1 is a perspective view showing a structure of a front end portion in a digital broadcast receiving apparatus according to an embodiment of the present invention. The front end circuit 121 is mounted on a motherboard 122 on which a back end circuit such as a demodulation circuit (not shown) is mounted. Front end circuit 121
Are two terminal rows 123 and 12 arranged in parallel with each other.
4, and correspondingly, terminal rows 125 and 126 are formed on the motherboard 122.

The terminal row 123 corresponds to the CATV broadcast receiving tuner 1 shown in FIGS. 4 and 6, and the output terminal 54 for outputting the transport stream and the input / output terminal 68 are formed in a straight line. ing. Similarly,
The terminal row 124 corresponds to the satellite broadcast receiving tuner 71 shown in FIGS. 5 and 7, and the output terminal 104 for outputting a transport stream and the input / output terminal 118 are formed in a straight line. A circuit pattern 127 corresponding to the CATV broadcast receiving tuner 1 and a circuit pattern 128 corresponding to the satellite broadcast receiving tuner 71 are formed on the motherboard 122, and a circuit pattern 129 common to the transport stream and the like, 130 are formed.

The front-end circuit 121 is configured such that a substrate on which the circuit of the CATV broadcast receiving tuner 1 shown in FIG. 4 or the satellite broadcast receiving tuner 71 shown in FIG. And
Correspondingly, the shield housing 131 has the 2
Rows of terminal rows 123 and 124 are attached. At least the locking claws 132 and 133 of the shield casing 131 are standardized, and after inserting through the locking holes 134 and 135 of the correspondingly formed motherboard 122, respectively, the folding is performed on the back side of the motherboard 122. The front end circuit 121 is fixed to the motherboard 122 in this way.

On the motherboard 122 side, the common circuit patterns 129 and 130 and the unique circuit pattern 1
Circuits corresponding to all 27 and 128 are formed.
On the other hand, on the front end circuit 121 side, as described above, one of the circuit patterns of the CATV broadcast receiving tuner 1 shown in FIG. 4 and the satellite broadcast receiving tuner 71 shown in FIG. 5 is formed. Therefore, only one of the two terminal rows 123 and 124 is used corresponding to the circuit housed in the shield housing 131.

Thus, in the digital broadcast receiving apparatus according to the present invention, the CA
TV broadcast receiving tuner 1 or satellite broadcast receiving tuner 7
Whichever one is stored, the motherboard 122 can be shared, and the motherboard 122 can be efficiently developed. When such a motherboard 122 is shared, the front-end circuit 12
1, it is not necessary to form circuits for both the CATV broadcast receiving tuner 1 and the satellite broadcast receiving tuner 71.
There is no increase in the size of the front end circuit 121.

Another embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a perspective view of a front end circuit 141 according to another embodiment of the present invention. In the front end circuit 141, the CA
TV broadcast receiving tuner 1 or satellite broadcast receiving tuner 7
1 is stored in the same manner as the front end circuit 121, but the output terminals 54 and 104 for outputting the transport stream are connected to the output terminal 142.
They differ in that they are shared as

Although not shown, a common terminal is formed on the motherboard in correspondence with the common output terminal 142. Portions corresponding to the input / output terminals 68 and 118 are the same as those in the configuration of FIG. Locking holes 134, 1 corresponding to locking claws 132, 133, respectively.
35 is the same.

With this configuration, the number of terminals can be reduced, and the cost of the terminals and the terminal space on the motherboard can be reduced.

Regarding still another embodiment of the present invention,
The following is a description based on FIG.

FIG. 3 is a perspective view of tuners 1a and 71a according to still another embodiment of the present invention. These tuners 1a and 71a are housed in the above-mentioned shield casing 131, and the motherboard 122 shown in FIG. Notable is that
In the present embodiment, in the tuner 1a shown in FIG. 3A, the terminal row 123 is provided on the upper surface side of the substrate 1b in FIG.
Is installed. On the other hand, in the tuner 71a shown in FIG. 3B, the terminal row 124 is attached to the lower surface side of the substrate 71b in FIG.

Therefore, on the front end circuit side,
Only one of the terminal arrays 123 or 124 is mounted in accordance with whether the tuner to be stored is the CATV broadcast receiving tuner 1 or the satellite broadcast receiving tuner 71. , The terminal row may be one, and the terminal cost can be reduced, and the space on the side opposite to the side where the terminal rows 123, 124 are mounted on the boards 1b, 71b can be effectively utilized.

It is needless to say that the present invention is not limited to the above-mentioned CATV broadcast receiving tuner and satellite broadcast receiving tuner, but may be applied to, for example, a tuner for terrestrial digital television broadcasting. Also, the modulation method is the OF of digital terrestrial television broadcasting.
Other modulation schemes such as a DM modulation scheme may be used.
Furthermore, although FIGS. 1 to 3 describe the case where the number of terminal rows is two, it is needless to say that three or more rows may be provided.

[0042]

As described above, the digital broadcast receiving apparatus according to the first aspect of the present invention has the following features:
Corresponding to the layout of multiple types of circuits to be housed in the housing, at least some of the functions of the multiple terminals are arranged in parallel with different terminal rows, and demodulation circuits such as motherboards On the board side on which the terminals are mounted, patterns corresponding to the respective terminal rows are formed.

Therefore, some circuits of the motherboard are not used for a plurality of types of front-end circuits. However, even if the types of front-end circuits are different, the motherboard can be shared to improve development efficiency. In addition, the front-end circuit can be specific to the modulation scheme or transmission medium, and can be as small as necessary.

Further, the digital broadcast receiving apparatus according to the second aspect of the present invention shares terminals having the same function among a plurality of terminal rows as described above.

Therefore, it is only necessary to provide a set of terminals having the same function and a set of terminals having different functions for each front-end circuit. The number of terminals can be reduced, and the cost and cost can be reduced. Circuit space can be reduced.

In the digital broadcast receiving apparatus according to the third aspect of the present invention, as described above, the terminal row on the board side is two rows, and the front end circuit side has either the front face or the back face of the board. The terminal row is attached to one side.

Therefore, although two terminal rows are formed on the substrate side, only one row is required on the front end circuit side, so that the cost of the terminals can be reduced and the side on which no terminals are mounted is provided. The space on the substrate can be effectively utilized.

[Brief description of the drawings]

FIG. 1 is a perspective view of a front end portion in a digital broadcast receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a perspective view of a front end circuit according to another embodiment of the present invention.

FIG. 3 is a perspective view of a tuner according to still another embodiment of the present invention.

FIG. 4 is a block diagram showing an electrical configuration of a general digital CATV broadcast receiving tuner.

FIG. 5 is a block diagram showing an electrical configuration of a general digital satellite broadcast receiving tuner.

FIG. 6 is a schematic front view for explaining a signal flow in the tuner shown in FIG. 4;

FIG. 7 is a schematic front view for explaining a signal flow in the tuner shown in FIG. 5;

[Explanation of symbols]

 1, 1a Digital CATV broadcast receiving tuner 1b, 71b Substrate 40 First mixing circuit 41 PLLIC 42 QAM demodulation IC 45 Second mixing circuit 54, 104; 142 Output terminal 61 Preamplifier circuit block 62 Input stage block 63 Interstage block 64 Mixing circuit block 65 Local oscillation circuit block 66 Demodulation circuit block 67, 117 Case 68, 118 Input / output terminal 71, 71a Digital satellite broadcast receiving tuner 79 I, Q demodulation circuit 99 QPSK demodulation circuit 111 Amplification block 112 Frequency conversion block 113 Oscillation Circuit block 114 Filter block 115 I, Q demodulation block 116 Demodulation block 121, 141 Front-end circuit 122 Motherboard 123, 124; 125, 126 Terminal row 127, 128; 129, 130 Circuit pattern 131 Shield housing 132, 133 Locking claw 134, 135 Locking recess

Claims (3)

[Claims] 1. A digital broadcasting system comprising: a front-end circuit housed in a predetermined housing and converting an input high-frequency signal to a signal to be digitally demodulated, mounted on a substrate on which at least a demodulation circuit is mounted in a subsequent stage. In the receiving device, on the side of the front-end circuit, corresponding to a plurality of circuit layouts different from each other, a terminal row in which at least a part of a plurality of terminal functions is different from each other is arranged in parallel with each other; A digital broadcast receiving apparatus, on the side, forming a pattern corresponding to each terminal row. 2. The digital broadcast receiving apparatus according to claim 1, wherein terminals having the same function are shared among a plurality of terminal rows. 3. The terminal row on the board side is two rows, and on the front end circuit side, the terminal row is attached to either the front surface or the back surface of the substrate in accordance with the circuit layout. 2. The digital broadcast receiving apparatus according to claim 1, wherein: