JP2000165232A - Pll circuit and communication device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an inexpensive and highly efficient PLL circuit capable of being utilized in >=3 GHz high frequency by performing PLL control of a voltage controlled oscillator by using an output of a filter extracting a fundamental wave component included in an output of a multiplier. SOLUTION: An output of a voltage controlled oscillator 2 is connected to a multiplier 11, an output of the multiplier 11 is divided into two, one of them is connected to a bandpass filter 12 and an output of the filter 12 becomes an output of a PLL circuit. The other of the two divided ones of the output of the multiplier 11 is connected to a PLL-IC 5 of a control circuit 3 through a lowpass filter 13. In a PLL circuit 10 configured in this way, an output, (i.e., fundamental wave signal) of the oscillator 2 is multiplied by the multiplier 11 and outputted as a signal with a frequency being (n) times (n is an integer >=2) as many as a fundamental wave. The oscillator 2 is subjected to PLL control by the control circuit 3 to stabilize an output frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit and a communication device using the same, particularly an automatic toll collection system for an expressway.
The present invention relates to a PLL circuit used as a local signal source of a transmission circuit or a reception circuit such as a T.T.

[0002]

2. Description of the Related Art In a current radio communication system such as an automatic toll collection system, a PLL circuit is combined with a PLL-IC, a loop filter and a voltage controlled oscillator in order to obtain a signal source for generating a local signal having a stable frequency. Is composed.

FIG. 3 shows a block diagram of a conventional PLL circuit. In FIG. 3, a PLL circuit 1 includes a voltage controlled oscillator 2
And the control circuit 3, of which the control circuit 3 is TCX
O (Temperature Compensated)
A crystal oscillator (temperature-compensated crystal oscillator) 4, a PLL-IC 5, and a loop filter 6 are provided. Further, although not shown, the PLL-IC 5 includes a frequency divider and a phase comparator. Here, the output of the voltage controlled oscillator 2 is divided into two, one of which is a PLL.
The output of the circuit 1 and the other is the PLL-IC of the control circuit 3.
5 is connected. In the control circuit 3, TCXO
4 is connected to the PLL-IC 5, which is connected to the loop filter 6, and the loop filter 6 is connected to the voltage-controlled oscillator 2.

In the PLL circuit 1 configured as described above, the output of the voltage controlled oscillator 2 is partly divided and input to the PLL-IC 5 of the control circuit 3. TCXO
4 is also input to the PLL-IC 5. PLL-IC
At 5, the output of the voltage controlled oscillator 2 and the output of the TCXO 4 are frequency-divided by a frequency divider so that they have the same frequency, and the phase comparator compares the phase difference between them. According to the phase difference, the phase comparator outputs a signal for controlling the oscillation frequency of the voltage controlled oscillator so as to eliminate the difference. PLL
Unnecessary high frequency components are removed from the signal output from the phase comparator of the IC 5 by the loop filter 6 and input to the control voltage terminal of the voltage controlled oscillator 2. Voltage controlled oscillator 2
Is the PLL-IC5 according to the output from the control circuit 3.
The frequency is slightly increased or decreased so that the phase difference between the two signals in the phase comparator is eliminated. By constantly repeating such an operation, the signal output from the voltage controlled oscillator 2 is always maintained at a stable frequency substantially equal to the signal output from the TCXO 4.

[0005]

Generally, a PLL-IC
In the case of a voltage-controlled oscillator, the price increases as the frequency handled increases. In particular, as for the PLL-IC, 3 GHz is the limit of the inexpensive Bi-CMOS which is usually used. On the other hand, a PLL-IC that can cope with high frequencies using gallium arsenide is also conceivable, but the price is about ten times as high as that of a Bi-CMOS.

For this reason, in the above-mentioned PLL circuit 3, in particular, an automatic toll collection system (using a frequency of about 6 GHz)
There is a problem that it is difficult to obtain a signal capable of outputting a signal of a stable frequency of 3 GHz or more such as z) at a low price. In addition, in order to use a part of the output of the voltage controlled oscillator 2 for PLL control, an amplifier must be provided for the output as necessary. For example, the efficiency of the output of the voltage controlled oscillator 2 is low. There is also.

It is therefore an object of the present invention to provide a low-cost and high-efficiency PLL circuit which can be used at a high frequency of 3 GHz or more, and a communication device using the same.

[0008]

In order to solve the above problems, a PLL circuit according to the present invention includes a voltage controlled oscillator, a multiplier for multiplying the output of the voltage controlled oscillator, and an output of the multiplier. And a control circuit for performing PLL control of the voltage controlled oscillator using the output of the filter.

A communication device according to the present invention is characterized by using the above-mentioned PLL circuit.

With this configuration, in the PLL circuit of the present invention, an efficient and inexpensive signal source of a high frequency of 3 GHz or more can be obtained.

Further, in the communication device of the present invention, the price can be reduced.

[0012]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In FIG. 1, the same or equivalent parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. 1, a PLL circuit 10 includes a multiplier 11, a band-pass filter 12, and a low-pass filter 13 in addition to the conventional PLL circuit 1 shown in FIG. here,
The output of the voltage controlled oscillator 2 is connected to a multiplier 11, the output of the multiplier 11 is divided into two, one of which is connected to a bandpass filter 12, and the output of the bandpass filter 12 is connected to the output of the PLL circuit 10. Has become. And a multiplier 1
The other of the two outputs is a low-pass filter 1
3 is connected to the PLL-IC 5 of the control circuit 3.

In the PLL circuit 10 configured as described above, the output of the voltage controlled oscillator 2 (ie, the fundamental wave signal) is multiplied by the multiplier 11 to obtain a signal having a frequency n times the fundamental wave (n is an integer of 2 or more). Is output as For example, if the output of the voltage controlled oscillator 2 is 1.5 GHz and the multiplier 11 is configured to multiply the fundamental by four, the output of the multiplier 11 will be 6 GHz. However, the signal output from the multiplier 11 includes a signal having an unnecessary frequency component including the fundamental wave itself in addition to a signal having a frequency n times the fundamental wave. Therefore,
The output of the multiplier 11 is divided into two parts, and one of them is extracted by the band-pass filter 12 to output only n-fold frequency components. The other of the two outputs of the multiplier 11 is input to the low-pass filter 13. The low-pass filter 13 extracts only the fundamental wave component from the signal output from the multiplier 11,
-Input to IC5. Thereafter, similarly to the conventional PLL circuit 1, the control circuit 3 performs PLL control of the voltage-controlled oscillator 2 to stabilize the output frequency. Thus, a stable signal having a frequency n times the oscillation frequency of the voltage controlled oscillator 2 can be output.

At this time, since the PLL-IC 5 used in the voltage controlled oscillator 2 and the control circuit 3 corresponds to a low frequency, it can be constructed relatively inexpensively. Also, the multiplier 11 can be configured at a much lower cost than a PLL-IC corresponding to a high frequency. As a result, the PLL
The circuit 10 itself can be configured at low cost.

The input signal to the PLL-IC 5 is not directly taken from the voltage controlled oscillator 2 but is taken out through the low-pass filter 13 from the fundamental wave signal contained in the signal outputted from the multiplier 11. ing. for that reason,
All of the output of the voltage controlled oscillator 2 can be input to the multiplier 11 without being taken to the control circuit 3. In addition, since the fundamental wave component, which is an unnecessary signal, is extracted from the signal after n-multiplication and used, most of the n-multiplied signal can be output through the band-pass filter 12 without loss. As a result, the voltage controlled oscillator 2
Is not performed, that is, a signal multiplied by n can be output with almost the same high efficiency as in the case where only the voltage controlled oscillator 2, the multiplier 11, and the band-pass filter 12 are used as signal sources.

Although the PLL circuit 11 uses the low-pass filter 13 to extract the fundamental wave component,
This may use a band-pass filter that matches the frequency of the fundamental wave.

FIG. 2 is a block diagram of a receiving circuit section of a communication device using the PLL circuit 10 of the present invention shown in FIG. 1 as one embodiment of the communication device of the present invention. In FIG. 2, a communication device 20 includes an antenna 21, a filter 22, an amplifier 23,
PLL circuit 10, mixer 24, filter 25, amplifier 2
6. It is composed of a signal processing circuit 27. Here, the antenna 21 is connected to the mixer 2 via the filter 22 and the amplifier 23.
4 is connected. The PLL circuit 10 is also connected to the mixer 24. The output of the mixer 24 is connected to a signal processing circuit 27 via a filter 25 and an amplifier 26.

In the communication device 20 configured as above, an RF signal of, for example, 5.9 GHz high frequency received by the antenna 21 is filtered by a filter 22 to remove an unnecessary signal, amplified by an amplifier 23, and amplified by a mixer 24. Is input to On the other hand, for example, 6GH generated in the PLL circuit 10
The local signal of z is also input to the mixer 24. Mixer 2
In 4, the input 5.9 GHz and 6 GHz
The two signals are mixed and an IF signal having a difference of 100 MHz is output. At this time, since a signal with a stable frequency is output from the PLL circuit 10, the frequency of the IF signal output from the mixer is also stable.

Unnecessary signals are removed from the IF signal output from the mixer 24 by a filter 25, amplified by an amplifier 26, and input to a signal processing circuit 27. Signal processing circuit 27
In, information contained in an input signal is demodulated and extracted, and processing such as calculation of a charge is performed. At this time, since the frequency of the IF signal is stable, errors during signal demodulation in the signal processing circuit 27 are reduced, and a circuit added for error correction and the like can be simplified and reduced in cost. . Also, the PLL circuit 10
The level of the local signal can be increased because of the high efficiency. Therefore, the NF (Nois
e Figure) and the gains of the amplifiers 23 and 26 can be slightly relaxed, and the price of the communication device can be reduced.

As described above, by using the PLL circuit 10 of the present invention, a low-cost and high-efficiency communication device can be configured.

[0021]

According to the PLL circuit of the present invention, a voltage controlled oscillator, a multiplier for multiplying the output of the voltage controlled oscillator,
A filter for extracting a fundamental wave component included in the output of the multiplier, and a voltage-controlled oscillator using
By having a control circuit for performing L control, a high-efficiency PLL circuit corresponding to a high frequency can be realized at a low price.

According to the communication device of the present invention, the above P
By using the LL circuit, low cost and high efficiency can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PLL circuit of the present invention.

FIG. 2 is a block diagram showing one embodiment of the communication device of the present invention.

FIG. 3 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 2 ... Voltage controlled oscillator 3 ... Control circuit 4 ... TCXO 5 ... PLL-IC 6 ... Loop filter 10 ... PLL circuit 11 ... Multiplier 12 ... Band-pass filter 13 ... Low-pass filter 20 ... Communication equipment

Claims (2)

[Claims] 1. A voltage-controlled oscillator, a multiplier for multiplying an output of the voltage-controlled oscillator, a filter for extracting a fundamental wave component included in an output of the multiplier, and the voltage using the output of the filter. A PLL circuit for controlling the control oscillator. 2. A communication device using the PLL circuit according to claim 1.