JP2000164659A - Failure analyzing system of semiconductor memory and navigation method of specimen stage of surface observation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency of failure analyzing work of a semiconductor memory by making a physical address of a bad cell and a layout information of a chip surface of a semiconductor memory a navigation information of a specimen stage and observing the surface of the bad cell. SOLUTION: A memory tester 1 detects a bad cell or a semiconductor memory which is an object of failure analysis and outputs the logic address of the bad cell to a logic address/physical address converting means 2. The address converting means 2 collects the logic address of the bad cell and coverts it to a physical address on a chip surface, refering to design data. In a surface observation device 4, the physical address of the bad cell and the layout information of the chip surface of the semiconductor memory in a layout information forming means 3 are made the navigation information of a specimen stage 5, and surface observation of the bad cell is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis system for a semiconductor memory and a method of navigation of a sample stage of a surface observation apparatus suitable for use in performing failure analysis of a semiconductor memory.

In general, a failure analysis of a semiconductor memory is performed by observing a defective cell found by an electrical inspection using a memory tester or the like as a semiconductor memory inspection device with a surface observation device such as a scanning electron microscope or an optical microscope. Will be

Therefore, in the surface observation apparatus, it is necessary to hold a semiconductor memory having a defective cell on a sample stage, navigate the sample stage, and search for a defective cell.

[0004]

2. Description of the Related Art Conventionally, as a method of navigating a sample stage of a surface observation device holding a semiconductor memory having a defective cell, for example, a logical address of the defective cell is collected from a memory tester, and the defective cell is referred to by design data. Are converted into coordinates on the chip surface, and the sample stage is navigated by the sample stage control means based on the coordinates.

Further, for example, a logical address of a defective cell is collected from a memory tester, and an operator navigates the sample stage by himself based on the logical address information of the defective cell and the layout information of the chip surface of the semiconductor memory. The method of doing is also used.

[0006]

In the former navigation method, when a failure analysis is performed on a chip on a wafer, the coordinates on the chip surface are coordinates on a wafer basis. If it is far from the origin of the chip, navigation errors will increase. However, recent semiconductor memories are highly integrated and memory cells are small in size. It becomes a big obstacle.

Here, the error between the position coordinates of the defective cell converted from the logical address collected from the memory tester and the actual coordinates of the defective cell is determined by a conversion table used when converting the logical address into the position coordinate. This is because it is made based on

That is, an actual semiconductor memory is not always manufactured according to the design data, but is often manufactured by shrinking it like “98% of the design data”. An error occurs between the position coordinates of the defective cell converted from the logical address collected from the data and the actual coordinates of the defective cell.

When the semiconductor memory is mounted on the sample stage of the surface observation apparatus, it is necessary to perform alignment (exchange of the coordinate system) between the coordinate system of the semiconductor memory and the coordinate system of the sample stage. In addition, a reference point (alignment mark) for performing alignment is required.

Here, when the wafer is not packaged like a wafer or the like, it is possible to find the center of the wafer and use it as a reference point for alignment. However, the wafer is already diced or packaged. In such a case, an alignment mark is required in the chip.

However, when packaged, the chip is covered with a resin or the like.
It is necessary to remove the resin, but at that time, without removing all the cover, often remove only the part that seems to be defective, it is not always possible to refer to the alignment mark .

However, when performing a failure analysis of a semiconductor memory, when navigating a sample stage of a surface observation device holding a semiconductor memory having a defective cell, alignment of the semiconductor memory with the sample stage is performed in any situation. It is required to perform it with high accuracy.

In view of the foregoing, the present invention does not require a special alignment mark in a semiconductor memory having a defective cell, and enables the memory cell to be used as an alignment mark. It is an object of the present invention to provide a semiconductor memory failure analysis system and a sample stage navigation method of a surface observation device, which can be realized.

[0014]

SUMMARY OF THE INVENTION A failure analysis system for a semiconductor memory according to the present invention detects a failure cell in the semiconductor memory and outputs a logical address of the failure cell. Logical address / physical address conversion means for collecting the logical address of the cell and referring to the design data of the semiconductor memory to convert the logical address of the defective cell into a physical address; Layout information creating means for creating layout information; and a surface observation device for observing the surface of the defective cell using the physical address of the defective cell and the layout information of the chip surface of the semiconductor memory as navigation information of the sample stage. Things.

According to the semiconductor memory failure analysis system of the present invention, when navigating the sample stage of the surface observation device, the layout information of the chip surface of the semiconductor memory can be used, so that a special alignment mark is used as the alignment mark. , And the memory cell can be used as an alignment mark.

Further, the method of navigating the sample stage of the surface observation device according to the present invention enables the surface observation of the defective cell by navigating the sample stage of the surface observation device holding the semiconductor memory having the defective cell. A method of navigating a sample stage of a surface observation device, wherein the sample stage of the surface observation device is navigated using position information of a defective cell on a chip surface and layout information of a chip surface of a semiconductor memory.

According to the navigation method of the sample stage of the surface observation apparatus of the present invention, since the layout information on the chip surface of the semiconductor memory is used, no special alignment mark is required as an alignment mark, and the memory cell can be aligned. It can be used as a mark.

[0018]

FIG. 1 is a conceptual diagram showing one embodiment of a semiconductor memory failure analysis system according to the present invention.
Among them, reference numeral 1 denotes a memory tester that detects a defective cell in a semiconductor memory to be analyzed and outputs a logical address of the defective cell.

Reference numeral 2 denotes logical address / physical address conversion means for collecting the logical address of the defective cell from the memory tester 1 and referring to the design data to convert the logical address of the defective cell into a physical address on the chip surface. is there.

Reference numeral 3 denotes layout information creating means for creating layout information on the chip surface of the semiconductor memory from design data such as the size of the semiconductor memory chip and the method of arranging the memory cells.

Here, the physical address refers to a distance from a reference point (for a wafer, for example, the center of the wafer, for a chip, for example, a corner of the chip) to a defective cell. Generally, a memory tester has a function of outputting a physical address from a specific reference point, and the format output by different manufacturers is the same.

Reference numeral 4 denotes a surface observation device such as a scanning electron microscope or an optical microscope; 5 a sample stage for holding a sample to be surface-observed; In addition to loading the address, the layout information on the chip surface of the semiconductor memory is loaded from the layout information creating means 3 and the sample stage 5 is loaded.
Sample stage control means for controlling the movement of the sample stage.

FIG. 2 is a schematic plan view showing a semiconductor memory to be subjected to failure analysis. In FIG. 2, reference numeral 8 denotes a chip which is a main body of the semiconductor memory, 9 denotes an origin of the chip 8, and 10 denotes a plurality of memory cells. Are memory cell blocks in which are arranged.

FIG. 3 is a schematic plan view showing the memory cell block 10. In FIG. 3, reference numeral 12 denotes memory cells arranged in a matrix, 13 denotes a peripheral circuit, and 14 denotes an origin of the memory cell block 10. In this example, each memory cell block 10 corresponds to a lower left memory cell 12 in the figure. Is the origin.

FIG. 4 is a flowchart showing an embodiment of a method for navigating the sample stage of the surface observation apparatus according to the present invention. That is, in one embodiment of the sample stage navigation method of the surface observation device of the present invention,
First, the physical address information of the defective cell and the layout information of the chip 8 are loaded into the sample stage control means 6 (step S1).

The layout information of the chip 8 includes at least the coordinates of the origin 14 of all the memory cell blocks 10 in the chip 8, the horizontal memory cell block length LX, the vertical memory cell block length LY, and the memory cell 12 In the X-axis direction and the array pitch PY of the memory cells 12 in the Y-axis direction.

The horizontal memory cell block length LX
Are the center of the leftmost memory cell 12 and the rightmost memory cell 1
2, the distance from the center of the memory cell, and the length LY of the memory cell block in the vertical direction.
Are the center of the upper memory cell 12 and the lower memory cell 1
2 is the distance from the center.

Next, the sample stage 5 in the coordinate system of the chip 8
Is calculated with respect to the coordinate system of
It is determined whether it is necessary to perform global alignment for correcting the coordinate system (step S2).

FIG. 5 is a schematic plan view for explaining global alignment. When global alignment is performed (YES in step S2), three reference positions are set so as to form an orthogonal coordinate system. Designate the memory cell blocks 10A, 10B, 10C (step S3),
The alignment error is calculated using the origin 14 of the specified memory cell blocks 10A, 10B, 10C, and the coordinate system of the chip 8 is corrected (step S4).

As shown in FIG. 5, the global alignment is performed by setting the coordinate system of the sample stage 5 to XY and the chip 8
Is defined as x′−y ′, X = X0 + x′cosθ−y′sinθ Y = Y0 + x′sinθ + y′cosθ By converting the coordinate system of the chip 8 into the coordinate system of the sample stage 5, .

Here, X0 is the amount of displacement in the X-axis direction between the origin 16 of the sample stage 5 and the origin 9 of the chip 8, and Y0 is the amount of displacement in the Y-axis direction between the origin 16 of the sample stage 5 and the origin 9 of the chip 8. , Θ are inclinations of the coordinate system of the chip 8 with respect to the coordinate system of the sample stage 5.

In this example, three memory cell blocks 10 out of the four corner memory cell blocks of the chip 8 are used.
A, 10B, and 10C are specified, but if these cannot be used for some reason, any internal memory cell block can be used.

When the global alignment is completed, or when the global alignment is not necessary (NO in step S2), a memory cell block including a defective cell is calculated (step S5).

Next, the sample stage 5 is moved under the control of the sample stage control means 6 so that the origin 14 of the memory cell block 10 including the defective cell and the origin of the field of view for observing the surface overlap each other (step S6). .

Next, the operator corrects the position of the sample stage 5 so that the origin 14 of the memory cell block 10 including the defective cell and the origin of the surface observation completely overlap (step S7).

Next, it is determined whether or not there is correction data for an alignment error of the memory cell block 10 with respect to the sample stage 5 (step S8). Local alignment is performed (step S9). This is because, even if global alignment is performed, alignment errors may remain for some reason, such as a movement error of the sample stage 5.

In the local alignment, three memory cells among the memory cells at the four corners of the memory cell block are designated so as to form a rectangular coordinate system, and an alignment error is determined using the center of the designated three memory cells. Can be calculated.

When the number of objects for surface observation increases, the number of local alignments also increases. That is, the position information of the memory cell block is improved by repeating the local alignment. The position of the memory cell is determined in advance as the distance from the origin 14 of the memory cell block 10, so that the correction error can be kept within the local alignment error range.

When the local alignment is completed or when the sample stage 5 of the memory cell block 10 is
If there is correction data of the alignment error for the defective cell, the sample stage 5 is moved under the control of the sample stage control means 6 to put the defective cell into the field of view for observing the surface (step S10). The observation is performed (step S11).

Next, it is determined whether or not to observe the surface of a defective cell of another memory cell block 10 (step S1).
2) When performing surface observation, return to step S5.
If not, the failure analysis work ends.

When the sample stage 5 is moved for observing the surface of a defective cell in another memory cell block 10, since the alignment information of the memory cell block is the same, the memory cell already subjected to local alignment Block alignment information can be used.

As described above, according to the embodiment of the sample stage navigation method of the surface observation apparatus of the present invention,
The global alignment is performed when necessary when navigating the sample stage 5. In this case, the layout information of the chip 8 is used, so that a special alignment mark is not required as an alignment mark, and the Cell block 10
Can be used as an alignment mark, so that global alignment can be easily performed.

Immediately after the global alignment, instead of navigating the sample stage 5 so that the defective cell enters the field of view for observing the surface, the origin of the memory cell block 10 containing the defective cell and the origin of the field of view for observing the surface are determined. Are overlapped, and from that position, the sample stage 5 is navigated again so that the defective cell enters the field of view for surface observation. As compared with the case of navigating the sample stage 5, highly accurate navigation of the sample stage 5 is facilitated.

As described above, according to the embodiment of the method for navigating the sample stage of the surface observation apparatus of the present invention,
Global alignment can be easily performed, and highly accurate navigation of the sample stage 5 can be easily performed. Therefore, even an unskilled operator can easily find a defective cell, and perform a failure analysis of the semiconductor memory. Work efficiency can be improved.

Further, according to one embodiment of the method of navigating the sample stage of the surface observation apparatus of the present invention, the sample origin is overlapped with the origin of the memory cell block 10 containing the defective cell and the field of view of the surface observation. When the stage control means 6 moves the sample stage 5 and the alignment error of the coordinate system of another memory cell block 10 has already been corrected, the correction data can be used. Therefore, the navigation of the sample stage 5 can be performed easily and with high accuracy.

By the way, a semiconductor memory failure analysis operation which has conventionally required one day as a work time (mostly one day is a defective cell search operation) can be performed in a few hours. became.

[0047]

As described above, according to the defect analysis system for a semiconductor memory of the present invention, since the layout information on the chip surface of the semiconductor memory can be used, a special alignment mark can be used as an alignment mark. Since the memory cell can be used as an alignment mark without requiring a memory cell, even an unskilled worker can easily find a defective cell, and the efficiency of the failure analysis work of the semiconductor memory can be improved.

Further, according to the method of navigating the sample stage of the surface observation apparatus of the present invention, the layout information on the chip surface of the semiconductor memory is used, so that a special alignment mark is not required as an alignment mark. Since the memory cell can be used as an alignment mark, even an unskilled operator can easily find a defective cell, and the efficiency of a semiconductor memory failure analysis operation can be improved.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing one embodiment of a semiconductor memory failure analysis system of the present invention.

FIG. 2 is a schematic plan view showing a semiconductor memory to be subjected to failure analysis.

FIG. 3 is a schematic plan view showing a memory cell block provided in the semiconductor memory shown in FIG. 2;

FIG. 4 is a flowchart illustrating an embodiment of a method for navigating a sample stage of the surface observation apparatus according to the present invention.

FIG. 5 is a schematic plan view for explaining global alignment executed in one embodiment of the method for navigating the sample stage of the surface observation device of the present invention.

[Explanation of symbols]

 (Fig. 1) 1 Memory tester 2 Logical address / physical address conversion means 3 Layout information creation means 4 Surface observation device 5 Sample stage 6 Sample stage control means (Fig. 2) 8 Chip 9 Chip origin 10 Memory cell block (Fig. 3) 12 Memory cell 13 Peripheral circuit 14 Origin of memory cell block (Fig. 5) 16 Origin of sample stage

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ichiro Honjo 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hirohisa Mizuno 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fujitsu Limited F term (reference) 2G032 AA07 AB20 AC01 AE04 AE12 AK00 AL02 4M106 AA01 AA02 AA04 AB07 CA26 CA38 DA14 DA15 DJ07 5F083 GA30 ZA20

Claims (6)

[Claims] A semiconductor memory inspection device for detecting a defective cell in the semiconductor memory and outputting a logical address of the defective cell; collecting a logical address of the defective cell from the semiconductor memory inspection device; Logical address / physical address conversion means for converting the logical address of the defective cell into a physical address with reference to the design data; and layout information generation for generating layout information of a chip surface of the semiconductor memory from the design data of the semiconductor memory And a surface observation device for observing the surface of the defective cell using the physical address of the defective cell and the layout information of the chip surface of the semiconductor memory as navigation information of a sample stage. Memory failure analysis system. 2. A method of navigating a sample stage of a surface observation device, wherein a sample stage of a surface observation device holding a semiconductor memory having a defective cell can be navigated to observe the surface of the defective cell. A method of navigating a sample stage of a surface observation device, wherein the sample stage is navigated using positional information of the defective cell on a chip surface and layout information of a chip surface of the semiconductor memory. 3. The semiconductor memory has a plurality of memory cell blocks in which a plurality of memory cells are arranged. The layout information on a chip surface of the semiconductor memory includes a position of an origin of the memory cell block, 3. The method for navigation of a sample stage of a surface observation device according to claim 2, wherein the length and width of the memory cell block and the arrangement pitch of the memory cells in the memory cell block are included. 4. The method according to claim 3, wherein the origin of the memory cell block is set at the center of a predetermined memory cell in the memory cell block. 5. The surface according to claim 4, further comprising a step of calculating an alignment error of a coordinate system of said semiconductor memory with respect to a coordinate system of said sample stage and correcting said coordinate system of said semiconductor memory. Navigation method of the sample stage of the observation device. 6. The calculation of the alignment error of the coordinate system of the semiconductor memory with respect to the coordinate system of the sample stage is performed by using three coordinates such that the coordinates of the origin of the chip of the semiconductor memory and the orthogonal coordinates included in the semiconductor memory. 6. The method according to claim 5, wherein the method is performed by reading the coordinates of the origin of the memory cell block.